JP2000115178A - Cell multi-address device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-cast type ATM cell multi-address device by a space type trunk system provided with the speed adjustment function of a copy cell. SOLUTION: When the cell of a multi-cast call is inputted, header converters 211-21N add a code tag for performing routing to a copy server 23 to the cell, attach an internal identifier instead of a new VPI/VCI and input it to a switch 22. The switch 22 routes the cell to an outgoing highway #(N+1)out indicated by the code tag. Inside the copy server 23, the plural sets of the code tag and the new VPI/VCI for performing routing to one of the outgoing highways #1 out-#Nout are retrieved based on the internal identifier of the ATM cell, they are replaced to the cell and the (c) pieces of the copy cells are generated. The copy cells are tentatively fetched into a copy cell read control circuit 30, the copy cells are managed for respective destination groups, and after adjusting a cell output timing for the respective groups, the copy cells are outputted to an incoming highway #(N+1)in.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a broadband ISDN (Broadba
nd Integrated Service Digital Network)
The present invention relates to a configuration of a broadcast device that realizes a broadcast function of an ATM (Asynchronous Transfer Mode) exchange.

[0002]

2. Description of the Related Art FIG. 18 is a block diagram of a conventional cell broadcast apparatus for a wideband ISDN disclosed in, for example, Japanese Patent Application Laid-Open No. 8-79253 entitled "ATM Switch with Multicast Function". A configuration using a spatial trunk system provided with a trunk, which is a broadcast device, is adopted. In the figure, # 1in~ # Nin is incoming highways, # 1out~ # Nout exits highway, 21 ₁ through 21 _N has a header conversion machine provided in each incoming highway (VCC1), 22 is 2N input / (N + 1 ) A switch unit for switching the output, 23 is a copy server, 24 _{1 to} 24 _N are header converters provided for each output link of the copy server 23
(VCC2) and 25 are call processing processors (CPUs). The copy server 23 generates the number (c ≦ N) of copy cells specified by the call processor 25 (CPU) and outputs the same to the output link. Each of the header converters 21 _{1 to} 21 _N provided in each of the incoming highways # 1in to #Nin has a routing table storing routing information up to the destination. The 24 ₁ to 24 _N each header converter comprises a routing table for routing each copy cells to prescribed outgoing highway.

FIG. 19 is a block diagram of a conventional cell broadcasting device using a conventional spatial trunk system disclosed in Japanese Patent Application Laid-Open No. 5-199257, entitled "Cell Switch". 1 shows a configuration in which a header converter (VCC2) portion is provided inside the copy server, and a single link connects the copy server and the switch. The operation is the same as in FIG.

FIG. 20 is a configuration diagram showing a detailed configuration of the copy server 23 shown in FIG. In the figure, 23
1 is an internal identifier extracting circuit for extracting the internal identifier written in the ATM cell header by the header converter, and 232 is a routing table RTBL23 based on the extracted internal identifier.
RTBL search circuit that reads out data from 3, 233 registers a new broadcast destination outgoing highway and a new VPI / VCI corresponding to the internal identifier in the input ATM cell header to broadcast cells under the control of the call processor 25 when making a call RTBL, 234 is the input ATM
235 is a cell buffer that stores cells as it is.
This is a cell buffer replacement circuit for replacing VPI / VCI. A copy cell read control circuit 30 (not shown) that adjusts the timing at which the copy cell generated by the cell buffer replacement circuit 235 is output from the copy server 23 to the switch 22 includes:
It comprises a single FIFO memory 311 for storing copy cells.

[0005] Next, the operation of an ATM switch provided with a conventional broadcasting device will be described. When an ATM cell other than a multicast call is input, the header converters (VCC1) 21 _{1 to} 21 _N output a code tag and a new VPI / VCI for routing to the ATM cells to the highways # 1out to #Nout. The code tag is obtained from the routing table in (VCC1), the code tag is added to the ATM cell, and the VPI / VCI is replaced with a new VPI / VCI and input to the switch 22. The switch 22 routes the ATM cell to the outgoing highway indicated by the code tag, removes the code tag, and sends the ATM cell to the outgoing highway.

On the other hand, when the ATM cell of the multicast call is inputted, the header converter (VCC1) 21 ₁ ~21 _N is added to code tag for routing to the copy server 23 to the ATM cell, and a new VPI / An internal identifier is added instead of the VCI and input to the switch 22. The switch 22 routes the ATM cell to the outgoing highway # (N + 1) out indicated by the code tag.

In the copy server 23, the outgoing highway # (N + 1) ou
When an ATM cell is input from t, the internal identifier extraction circuit 231 extracts the internal identifier from this ATM cell and
Transfer to On the other hand, the entire ATM cell is transferred to the cell buffer 234 and held. The routing table RTBL233 stores (1) one of the outgoing highways # 1out to #Nout in association with each of the c (≦ N) internal identifiers under the control of the call processor 25.
One code tag for specifying one outgoing highway and (2) one VPI / VCI as a regular call identifier are registered. Therefore, the RTBL search circuit 232 uses the internal identifier as a search key
By searching TBL233, (1) a code tag for routing the ATM cell to outgoing highways # 1out to #Nout and
(2) Obtain regular VPI / VCI.

Next, the cell header reordering circuit 235 reads the ATM cell from the cell buffer 234, and reads one of the c code tags retrieved based on the internal identifier and a regular VP.
The data is written to the single FIFO memory 311 in the copy cell read control circuit 30 in place of the I / VCI set. The operation of the cell header replacement circuit 235 is performed the same number of times as the copy number c (≦ N) instructed by the call processor 25. C copy cells continuously written to the single FIFO memory 311 at N times the speed of the incoming highway # 1in to Nin will enter the incoming highway # (N + 1) in at a constant speed to N times the speed of the incoming highway # 1in to Nin Read with. The switch 22 routes each of the c copy cells input from the incoming highway # (N + 1) in to the outgoing highway designated by the code tag, removes the code tag, and sends it to the outgoing highway.

FIG. 21 is an explanatory diagram showing an example of processing ATM cells other than a multicast call. Here, an example of header processing when an ATM cell other than a multicast call is input from the incoming highway # 1in. Cells are input to the incoming highway # 1in in the cell format shown in FIG. Header converter (VCC1) 21 ₁ obtains a a new VPI / VCI and # 3out a code tag old VPI / VCI as the search key of the ATM cell. Next, a code tag # 3ou is added to the ATM cell.
t is added and replaced with a new VPI / VCI, a, and input to the switch 22. The data is input to the switch 22 in the cell format shown in FIG. The switch 22 switches to the outgoing highway # 3out according to the code tag # 3out of the ATM cell. At the same time, the code tag that has become unnecessary due to the completion of the exchange is removed and sent to the outgoing highway # 3out. In the output highway # 3out, the data is output in the cell format shown in FIG.

FIG. 27 is an explanatory diagram showing an example of processing of an ATM cell of a multicast call. Here, an example of header processing when an ATM cell of a multicast call is input from an incoming highway # 2in is shown. The ATM cell is input to the incoming highway # 2in in the cell format shown in FIG. Header converter (VCC1) 21 ₂ recognizes the multicast call based on the old VPI / VCI of the ATM cell, # is a code tag for routing to the copy server 23 (N + 1) by adding out, It is input to the switch 22 after being replaced with # 2 which is an internal identifier broadcast to the outgoing highways # 1, # 2 and # 3. 23 to switch 22
Enter in cell format.

The switch 22 switches to the outgoing highway # (N + 1) out according to # (N + 1) out which is the code tag of the ATM cell. At the same time, the code tag that has become unnecessary due to completion of the exchange is removed and sent to the outgoing highway # (N + 1) out. At the outgoing highway # (N + 1) out, the ATM cell is output to the copy server 23 in the cell format shown in FIG.

The copy server 23 searches the routing table RTBL using # 2, which is the internal identifier of the ATM cell, as a search key, and obtains four sets of a code tag as a broadcast destination and a new VPI / VCI. Next, as shown in FIG. 27, a code tag # 1out is added to the ATM cell, and a new VPI / VCI
To the switch 22, and to the ATM cell, add a code tag of # 2out, and replace it with a new VPI / VCI, e, to the switch 22, and add a code tag to the ATM cell. # 3out added and new VPI / VCI a
To the switch 22, and to the ATM cell, add a code tag # 3out, and replace it with a new VPI / VCI f to connect the switch 22 to # (N + 1) in. To output a copy cell. A copy cell is input to the switch 22 in the same cell format as in FIG.

The switch 22 switches to the outgoing highway # 1out according to the code tag # 1out of the first copy cell. At the same time, the code tag that has become unnecessary due to completion of the exchange is removed and sent to the outgoing highway # 1out. In the output highway # 1out, the copy cell is output in the cell format shown in FIG. Next, the switch 22 switches to the outgoing highway # 2out according to the code tag # 2out of the second copy cell. At the same time, the code tag that has become unnecessary due to completion of the exchange is removed and transmitted to the outgoing highway # 2out.
In the output highway # 2out, the copy cell is output in the cell format shown in FIG. Next, the switch 22 outputs the highway # in accordance with # 3out which is the code tag of the third copy cell.
Exchange to 3out. At the same time, the code tag that has become unnecessary due to the completion of the exchange is removed and sent to the outgoing highway # 3out. In the output highway # 3out, the copy cell is output in the cell format shown in FIG. Next, the switch 22 switches to the outgoing highway # 3out according to the code tag # 3out of the fourth copy cell. Remove code tags that are no longer needed as a result of completing the exchange at the same time and go out on Highway # 3ou
Send to t. Figure 2 shows the copy cell on the outgoing highway # 3out
4 in the cell format.

[0014]

In a conventional cell broadcasting device using the spatial trunk system, a cell is copied by a copy server 23 shown in FIG. 18 and a header converter (VCC2) 24 _{1 is used.}
Again back to the switch 22 through to 24 _N. Because there is no description of the timing for inputting to the switch 22, the copy cell in the header converter (VCC2) 24 ₁ ~24 _N, believed to be input to the switch 22 without a timing adjustment for performing ATM cell storage. Some of the copy cells input to the switch 22 at that time may copy cells to the same outgoing highway, in which case the copy cells may arrive at a particular outgoing highway simultaneously or consecutively.
Also, in FIG. 19, the reading speed of the single FIFO memory 311 in the copy server 23 is equal to the input highway # 1in.
If the speed exceeds the speed of #Nin to #Nin, the copy cell arrives at a specific outgoing highway at the same time, and the incoming highways # 1in to #Nin.
If it is equal to the speed of in, it may arrive continuously. As a result, the number of finite buffers used in the switch 22 for waiting for incoming ATM cells addressed to the same outgoing highway rapidly increases. If an ATM cell that needs to be waited for is input while the number of unused buffers is temporarily 0, the input ATM cell is discarded. In this device, there is a problem that the above-described cell discard is likely to occur, and communication quality is deteriorated.

There is also a problem that it is necessary to have a large amount of buffers in the switch 22 in order to avoid the above-mentioned deterioration in communication quality.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and uses a relatively small-capacity buffer so that even if input cells addressed to the same output highway arrive at the same time or consecutively, a switch can be used. It is an object of the present invention to obtain a cell broadcasting apparatus that reduces the frequency of occurrence of cell discard in a cell.

[0017]

The cell broadcasting apparatus according to the first invention converts an ATM cell header into an internal header, and in the case of broadcasting, converts it into a specific internal identifier and outputs it to an incoming highway. A header conversion means for inputting an ATM cell from the header conversion means from the incoming highway, and switching between the incoming highway and the outgoing highway based on the internal header. Switch means for switching the ATM cell to a specific outgoing highway, and a predetermined number of copies of the ATM cell input from the specific outgoing highway based on the internal identifier. ) Is added to the internal header so that each of them is sent to the respective output highway, and the copy server outputs the output to the switching means. In the cell broadcasting apparatus having a multicast function of copying and routing one ATM cell to a plurality of designated outgoing highways, the copy server adjusts the output timing of the copy cell between the destination groups. Things.

Further, the cell broadcasting apparatus according to the second invention comprises:
A header conversion means for converting the header of the ATM cell into an internal header, and in the case of a broadcast, converting it to a specific internal identifier and outputting it to the incoming highway, and inputting the ATM cell from the header converting means from the incoming highway. Performs switching between the incoming highway and the outgoing highway based on the internal header, and in the case of broadcast, the A
Switch means for switching the TM cell to a specific output highway; and a predetermined number of copies of the ATM cell input from the specific output highway based on the internal identifier, and the obtained ATM cells (hereinafter referred to as copy cells). A copy server that adds an internal header to each of the outgoing highways so as to send them to the respective outgoing highways, and outputs the ATM cells to the switching means, wherein one ATM cell is copied to a plurality of designated outgoing highways for routing. In the cell broadcasting device having the function, the copy server adjusts the output timing of the copy cell for each destination group.

Further, the cell broadcasting device according to the third invention comprises:
The copy server includes a read control circuit that adjusts the output timing of the copy cell between the destination groups or for each destination group.

Further, the cell broadcasting apparatus according to the fourth invention comprises:
The copy server includes a copy cell storage address read control circuit that adjusts the timing of giving an address to a storage unit such as an output buffer memory or a common buffer memory that stores copy cell data.

Further, the cell broadcasting device according to the fifth invention comprises:
The copy cell read control circuit includes a FIFO memory for each copy cell destination group and a selector, and reads and multiplexes copy cells fairly and periodically among all destination groups.

Further, the cell broadcasting device according to the sixth invention comprises:
The copy cell read control circuit includes a copy cell continuous read count table in which the destination group number of the copy cell is associated with the continuous read count, and reads and multiplexes the copy cells according to the copy cell continuous read count table.

Further, the cell broadcasting device according to the seventh aspect of the present invention,
The copy cell read control circuit includes a FIFO memory for each copy cell destination group and a multiplexing circuit for time division multiplexing, and reads and multiplexes copy cells fairly and periodically between all destination groups.

[0024] Further, the cell broadcasting device according to the eighth invention comprises:
The copy cell read control circuit includes a plurality of destination group FIFOs.
It has a memory and a shaping circuit corresponding to each memory.

Further, the cell broadcasting device according to the ninth invention is characterized in that:
A plurality of destination group FIFO memories are provided in a one-to-many ratio for each destination group shaping circuit.

In a cell broadcasting device according to a tenth aspect of the present invention, the copy cell read control circuit includes a destination group FIFO for queuing copy cells in groups in which some output highways of the switch are bundled without overlapping. It includes a memory group, a read schedule circuit for controlling read of copy cells from the FIFO memory for each destination group, and a read schedule table for scheduling destination groups from which copy cells are read.

[0027] In the cell broadcasting device according to the eleventh aspect, the copy server may include an internal identifier extraction circuit for extracting an internal identifier written in the ATM cell header, and a cell communication device controlled by the call processor at the time of calling. The broadcast highway corresponding to the internal identifier in the input ATM cell header to be reported, and a routine table (hereinafter referred to as RTB) storing the new VPI / VCI
L), an RTBL search circuit for reading data from the RTBL a plurality of times based on the internal identifier, a header FIFO memory for temporarily storing an input internal identifier to cope with a search wait for the RTBL, A cell buffer for storing an ATM cell, an output highway to an input ATM cell of the cell buffer, a cell header changing circuit for changing a new VPI / VCI, and a timing for outputting a copy cell generated by the cell header changing circuit to a switch. And a copy cell read control circuit for adjusting

In the cell broadcasting apparatus according to the twelfth aspect, the RTBL includes an internal identifier, a code tag corresponding to the internal identifier, and information for routing to an outgoing highway, and a VPI / VCI. Things.

In the cell broadcasting apparatus according to the thirteenth aspect, the RTBL includes an internal identifier, a broadcast number corresponding to the internal identifier, a code tag, a VPI / VCI, and a valid / invalid flag. It is a thing.

[0030] In the cell broadcasting apparatus according to the fourteenth invention, the RTBL includes an internal identifier, a broadcast number corresponding to the internal identifier, a code tag, a VPI / VCI, and an end flag. The end flag is set to {1} only for the last number of the report number.

A cell broadcasting apparatus according to a fifteenth aspect of the present invention comprises a copy server for generating a copy cell by copying a plurality of ATM cells at the time of broadcasting, a plurality of incoming highways input from the copy server, A switch having a plurality of output highways outputting to the copy server, a multiplexing circuit for time-division multiplexing a plurality of output highways outputting from the switch to the copy server, and a switch from the copy server to the switch It is provided with a separation circuit for separating a plurality of input highways that are input.

The cell broadcasting apparatus according to the sixteenth aspect of the present invention provides a plurality of outgoing highways output from the switch to the copy server and a plurality of incoming highways input from the copy server to the switch in a plurality of groups. A multiplexing circuit for time-division multiplexing only the plurality of outgoing highways assigned to each group; a demultiplexing circuit for separating only the plurality of incoming highways assigned to each group; And a copy server provided in the server.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a diagram illustrating the principle of a cell broadcasting apparatus using a spatial trunk system according to the present invention. In FIG. 1, # 1in to # (N + 1) in are incoming highways, # 1out to # (N + 1) out are outgoing highways, and 21 _{1 to} 21 _N are header converters (VCC1) provided on incoming highways. , 22 is (N
+1) input / (N + 1) output switch, 2
Reference numeral 3 denotes a copy server, reference numeral 25 denotes a call processor, and reference numeral 30 denotes a copy cell read control circuit provided in the copy server 23 for adjusting the read timing of the copy cell. Except for the copy cell control circuit 30, the configuration is exactly the same as that of the prior art.

FIG. 2 is a diagram for explaining another principle of the cell broadcasting device using the spatial trunk system according to the present invention.
2, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. Reference numeral 31 denotes a copy cell storage address read control circuit provided in the copy server 23.

FIG. 3 is a block diagram showing an embodiment of a cell broadcasting device using the spatial trunk system according to the present invention, and shows a structure of a copy cell read control circuit provided in a copy server. FIG. In FIG.
231 is an internal identifier extraction circuit, 232 is a routing table (RTBL) search circuit, and 233 is a routing table (R).
TBL), 234 is a cell buffer, 235 is a cell header replacement circuit, and 30 is a copy cell read control circuit. Reference numeral 321 denotes a FIFO memory group for each destination group for queuing copy cells for each group in which several output highways of the switch 22 are bundled without overlapping. Therefore by destination group
The FIFO memory group 321 can be configured from a minimum of two destination group FIFO memory groups to a destination group FIFO memory group in which one group is assigned to one output highway (an output highway FIFO memory group). The number of outgoing highways accommodated in the FIFO memory for each destination group may be the same or different. Reference numeral 33 denotes the order and the round (0, 1, 2,..., M-1, in ascending order of the group number) of each destination group FIFO memory of the destination group FIFO memory group 321 in a time series manner. 0, 1,...) And periodically reads out to one output link.

Next, the operation will be described. In the cell broadcasting device, a copy cell read control circuit 30 is provided in the copy server 23 as shown in FIG. 1, and the output timing of the copy cell is adjusted for each output highway. As a result, the frequency of occurrence of cell discard in the switch 22 can be reduced.

In the cell broadcasting apparatus shown in FIG. 2, a copy cell storage address read control circuit 31 is provided in the copy server 23.
Is provided, and the output timing of the copy cell can be indirectly adjusted by adjusting the timing of giving an address to the output buffer memory or the common buffer memory storing the data of the copy cell. The copy cell storage address read control circuit 31 processes the address of the output buffer memory or the common buffer memory storing the copy cell. Also in the case of this indirect copy cell output timing adjustment, the frequency of occurrence of cell discard in the switch 22 can be reduced.

In the copy server 23, the outgoing highway # (N + 1) ou
When an ATM cell is input from t, the internal identifier extraction circuit 231 extracts the internal identifier from this ATM cell and
Transfer to On the other hand, the entire ATM cell is transferred to the cell buffer 234 and held. The routing table RTBL233 stores c (≦ N) internal identifiers under the control of the call processor 25.
(1) a code tag that specifies one outgoing highway out of outgoing highways # 1out to #Nout, and (2) V which is a regular call identifier
PI / VCI is registered one by one. Therefore RTB
The L search circuit 232 sets the RTBL233
(1) exiting the ATM cell, highway # 1
The code tag for routing to out to #Nout and (2) the regular VPI / VCI are obtained.

In FIG. 3, when a copy cell with a code tag and a proper VPI / VCI is input from the cell header replacement circuit 235, the copy cell read control circuit 30 identifies the code tag, and The copy cell is written in the FIFO memory 321 for each destination group accommodating the tag. The copy cells stored in the destination group-based FIFO memory 321 are periodically read out by the selector 33. In the figure, the head of the destination group-based FIFO memory 321 is indicated by a circle. In this figure, the left end of the FIFO memory 321 is the head position.

FIG. 4 shows a state in which copy cells are queued in the four FIFO memories (G # 0 to G # 3) for each destination group at time t = 0 (right side in the figure). 0,1,2,
The situation where the copy cell is read from the selector 33 over 3,..., 18 (left side in the figure) is shown. However, new queuing of copy cells is performed again after t = 19. Also, V = V0 = V1 = V2 = V3. G # 0 at t = 1
Is read out of the cell. At t = 2, it is the read time of G # 1, but the copy cell is not read because the copy cell is not queued. Similarly, t = 3
However, since no copy cell is queued in G # 2, the copy cell is not read. At t = 4, a copy cell is read from G # 3.

In FIG. 4, the selector 33 sets one copy cell to the speed V.
The ATM cell is read out from the FIFO memory 321 for each different destination group at every reading time. However, if there is a bias in copy cell queuing by destination group,
In the selector 33, one copy cell is read continuously from the same destination group-based FIFO memory 321 by multiplying an integral multiple of the reading time at the speed V. The copy cell continuous read count table 331 of FIG.
The number of copy cells to be read at consecutive times in the memory is recorded. As shown in the figure, the CPU 25 sets the continuous read count in the copy cell continuous read count table 331.

FIG. 5 shows a copy cell continuous read count table.
When the copy cell is queued at t = 0 in FIG. 4 from the state where the copy cell is queued at time t = 1 in FIG. 4, the copy cell is read from the selector 33 over time t = 1, 2, 3,. Shows the situation going on. However, new queuing of copy cells
It is a situation that is performed again after t = 19. When the continuous read count in the copy cell continuous read count table 331 is 0, the skipping operation is performed. As a result, in a transition period in which the number of use of the outgoing highway gradually increases, the destination group corresponding to the outgoing highway group to which the outgoing highway physically exists but is not assigned to use.
Since the copy cells are not queued in the FIFO memory, a flexible read can be performed by skipping the read.

From t = 1 to 4, copy cells are read four consecutive times from G # 0 according to the copy cell continuous read count table 331. At t = 5, the copy cell is read from G # 2, jumping over G # 1 where the continuous read count of the copy cell continuous read count table 331 is 0. However, no copy cell is read in G # 2 because no copy cell is queued. Similarly, at t = 6,7, G # 3, at t = 8-11, G # 0, at t = 12
At G # 2, t = 13, 14, G # 3, and at t = 15-18, copy cells are read from G # 0.

In FIG. 4, the incoming highway # (N + 1)
Even when the destination group FIFO memory 321 is operated at a low speed obtained by dividing the in speed V by the number of destination group FIFO memories 321, the same copy cell can be read. However, in this case, it is necessary that the selector 33 be a multiplexing circuit 331 for time division multiplexing. In FIG. 4, V0,
If V1, V2, V3 = V / 4, FIFO memory 321 for each destination group
Circuit operates at a speed as low as 1/4 of the incoming highway # (N + 1) in. On the other hand, when the selector 33 is a multiplexing circuit 331 having a speed ratio of 4 to 1, the same copy cell reading as in FIG. 4 is performed as shown in FIG. However, continuous read of the copy cell cannot be performed.

Embodiment 2 FIG. 7 is a block diagram showing another embodiment of the cell broadcasting apparatus using the spatial trunk system according to the present invention. In the figure, a copy cell control circuit
Configurations other than 30 are exactly the same as those in FIG. Reference numeral 321 denotes a destination group FIFO memory group for queuing copy cells for groups in which some output highways of the switch 22 are bundled without overlapping. Reference numeral 322 denotes a destination group-specific shaping circuit group for controlling reading of copy cells from each destination group-specific FIFO memory. Reference numeral 34 denotes a contention adjustment FIFO for multiplexing the output link of the FIFO memory for each destination group and queuing the copy cell in the FIFO.
Memory.

Next, the operation will be described. In FIG. 7, each destination group-based shaping circuit group 322 operates independently based on the minimum cell reading interval value (TS) and the permissible fluctuation value (TAU) set by the CPU 25 for each circuit. However, the minimum cell read interval value set for each destination group,
Average cell read speed meanVi, i calculated from fluctuation tolerance
= 0, ..., (M-1) is added to all destination groupsΣ
It is necessary to set i = 1, (M -1) meanVi not to exceed the speed V of the incoming highway # (N + 1) in.

The operations from the internal identifier extraction circuit 231 to the cell header replacement circuit 235 are the same as in the first embodiment.
The copy cells stored in the destination group FIFO memory 321 are controlled by the destination group shaping circuit 322, for example, from the minimum interval obtained by subtracting the fluctuation allowable value from the minimum cell read interval to the minimum cell read interval. Is read, only one copy cell at the head of the FIFO memory for each destination group is read out in the range up to the widest interval obtained by adding The copy cells read from the destination group FIFO memory 321 are stored in the other destination group FIFO memory as shown in FIG.
The data is time-division multiplexed with the copy cells read from the memory at a high speed and written into the contention adjustment FIFO memory 34.

FIG. 8 is a diagram showing the destination group F at time t = 0.
A state where copy cells are queued in four IFO memories (G # 0 to G # 3) and setting information of four destination group shaping circuits (G # 0 to G # 3) by the CPU 25 are shown. In FIG. 8, the head of the FIFO memory for each destination group is indicated by a circle. Further, a new queuing of copy cells is performed again after t = 19. V ≧ maxV0 + maxV1 + max
V2 + maxV3.

FIG. 9 shows the queuing status of the contention adjustment FIFO memory 34 over time t = 0, 1, 2, 3,... At t = 0, the shaping circuit 322 for each destination group
, The first copy cell is read from the destination group FIFO memory of G # 0, G # 2, G # 3. At the same time, copy cells are time-division multiplexed and written in the contention adjustment FIFO memory 34 in the order of G # 0, G # 2, G # 3. Note that TS in the drawing indicates the minimum cell reading interval. For example, when TS = 2, the time interval from the transmission of a cell to the transmission of the next cell is 2. This means that transmission and non-transmission of cells are performed alternately. When TS = 3, the time interval from the transmission of a cell to the transmission of the next cell is 2. This means that the operation of transmitting the cell once and not transmitting the cell twice is repeated. TAU indicates a permissible value of fluctuation. FIG.
0 indicates the copy cell output status from the conflict adjustment FIFO memory 34 over time t = 0, 1, 2, 3,...

At t = 0, the shaping circuit for each destination group issues a reference (start) cell reading instruction to the FIFO memory for each destination group of G # 0, G # 2, and G # 3 being queued. Accordingly, F for each destination group of G # 0, G # 2, G # 3
The first copy cell is read from the IFO memory. In the contention adjustment FIFO memory 34, copy cells of G # 0, G # 2, and G # 3 are sequentially stored by time division multiplexing.

At t = 1, according to the shaping circuit for each destination group, the copy cells have not yet been read from the FIFO memories for all destination groups, and no new copy cells are written to the FIFO memory 34 for contention adjustment. For competition adjustment
In the FIFO memory 34, the copy cells of G # 0, G # 2, G # 3 are already stored, and the copy cell of G # 0, which is queued at the head, enters the highway # (N + 1) at the speed V. Output to in.

At t = 2, in the shaping circuit G # 0 for each destination group, since the minimum cell read interval TS = 2 has elapsed from t = 0, the read instruction to the FIFO memory for each destination group of G # 0 is controlled. . G # 0 destination group FIFO accordingly
The first copy cell is read from the memory. In the conflict adjusting FIFO memory 34, the copy cell of G # 0 is written at the end, and at the same time, the copy cell of G # 2 stored in advance is output to the incoming highway # (N + 1) in at the speed V.

At t = 3, in the destination group shaping circuit G # 3, since the minimum cell read interval TS = 3 has elapsed from t = 0, the read instruction to the destination group FIFO memory of G # 3 is controlled. . G # 3 destination group FIFO accordingly
The first copy cell is read from the memory. In the conflict adjustment FIFO memory 34, the G # 3 copy cell is written at the end, and at the same time, the G # 3 copy cell stored in advance is output at a speed V to the incoming highway # (N + 1) in.

At t = 4, in the shaping circuit G # 0 for each destination group, since the minimum cell read interval TS = 2 has elapsed from t = 2, the read instruction to the FIFO memory for each destination group of G # 0 is controlled. . Accordingly, G # 0 destination group FIF
The first copy cell is read from the O memory. In the conflict adjusting FIFO memory 34, the copy cell of G # 0 is written to the end, and at the same time, the copy cell of G # 0 is output to the incoming highway # (N + 1) in at the speed V.

At t = 5, no copy cells are read from all destination group FIFO memories according to the destination group shaping circuits, and no new copy cells are written to the conflict adjustment FIFO memory 34. FIFO memory for contention adjustment
At 34, the copy cell of G # 3 enters at speed V.Highway # (N + 1) in
Is output to

At t = 7, in the destination group shaping circuit G # 2, since the minimum cell read interval TS = 7 has elapsed from t = 0, the read instruction to the destination group FIFO memory of G # 2 is controlled. . G # 2 destination group FIFO accordingly
The first copy cell is read from the memory. In the conflict adjusting FIFO memory 34, the copy cell of G # 2 is written at the end, and at the same time, the copy cell of G # 0 is output to the incoming highway # (N + 1) in at the speed V.

At t = 8, in the shaping circuit G # 0 for each destination group, since the minimum cell read interval TS = 2 has elapsed since t = 6, a read instruction to the FIFO memory for each destination group of G # 0 is controlled. . G # 0 destination group FIFO accordingly
The first copy cell is read from the memory. In the conflict adjustment FIFO memory 34, the copy cell of G # 0 is written at the end, and at the same time, the copy cell of G # 3 is output to the incoming highway # (N + 1) in at the speed V.

At t = 8, in the destination group shaping circuit G # 0, since the minimum cell read interval TS = 2 has elapsed since t = 6, the read instruction to the destination group FIFO memory of G # 0 is controlled. . G # 0 destination group FIFO accordingly
The first copy cell is read from the memory. In the conflict adjustment FIFO memory 34, the copy cell of G # 0 is written at the end, and at the same time, the copy cell of G # 3 is output to the incoming highway # (N + 1) in at the speed V.

At t = 9, in the shaping circuit G # 3 for each destination group, the minimum cell reading interval TS = 3 has elapsed since t = 6, but since there is no copy cell queuing in G # 3, the destination of G # 3 Reading to the FIFO memory for each group is not instructed.
In the conflict adjusting FIFO memory 34, the copy cell of G # 2 is output at the speed V to the incoming highway # (N + 1) in.

At t = 10, in the destination group shaping circuit G # 0, since the minimum cell read interval TS = 2 has elapsed from t = 8, the read instruction to the destination group FIFO memory of G # 0 is controlled. . G # 0 destination group FIFO accordingly
The first copy cell is read from the memory. In the conflict adjusting FIFO memory 34, the copy cell of G # 0 is written to the end, and at the same time, the copy cell of G # 0 is output to the incoming highway # (N + 1) in at the speed V.

At t = 11, no copy cells are read from the FIFO memories for all destination groups according to the shaping circuit for each destination group, and no new copy cells are written to the FIFO memory 34 for contention adjustment. FIFO memory for contention adjustment
At 34, enter the copy cell of G # 0 at speed V Highway # (N + 1) in
Output to

At t = 12, in the shaping circuit G # 0 for each destination group, since the minimum cell read interval TS = 2 has elapsed since t = 10, the read instruction to the FIFO memory for each destination group of G # 0 is controlled. . G # 0 destination group FIF accordingly
The first copy cell is read from the O memory. In the conflict adjustment FIFO memory 34, the copy cell of G # 0 is written at the end. At the same time, there is no copy cell queuing, so there is no copy cell output on the incoming highway # (N + 1) in.

At t = 13, 15, and 17, no copy cells are read from all destination group FIFO memories according to the destination group shaping circuits, and no new copy cells are written to the conflict adjustment FIFO memory 34. Competition adjustment FIFO
In the memory 34, the copy cell of G # 0 enters at a speed V.
Output to (N + 1) in.

At t = 14, 16, and 18, in the shaping circuit G # 0 for each destination group, since the minimum cell reading interval TS = 2 has elapsed since t = 12, 14, and 16, respectively, the FIF for each destination group of G # 0
A read instruction to the O memory is controlled. In accordance therewith, the first copy cell is time-division multiplexed and read out from the G # 0 destination group-specific FIFO memory. In the competition adjustment FIFO memory 34
The copy cell of G # 0 is written at the end. At the same time, there is no copy cell queuing, so highway # (N + 1) in
There is no copy cell output.

According to this embodiment, for each destination group
Since the multiplexing from the FIFO memory to the contention adjustment FIFO memory is controlled by the setting of the shaping circuit, the multiplexing ratio between the groups can be flexibly controlled.

In FIG. 7, each destination group-based shaping circuit group 322 is stored in the destination group-based FIFO memory 321.
It is provided on a one-to-one basis. On the other hand, for each destination group shaping circuit 322, a plurality of destination group FIFs are provided.
One-to-many is provided in the O memory 321. Thus, the mounting scale of the shaping circuit 322 for each destination group is reduced.

Embodiment 3 FIG. 11 is a block diagram showing another embodiment of the cell broadcasting device using the spatial trunk system according to the present invention. In the figure, the configuration other than the copy cell control circuit 30 is exactly the same as in FIG. Reference numeral 321 denotes a destination group FIFO memory group for queuing copy cells for groups in which some output highways of the switch 22 are bundled without overlapping. 35 is FI for each destination group
The read schedule circuit 35 controls the read of a copy cell from the FO memory. Reference numeral 351 denotes a readout schedule table in which destination groups from which copy cells are read out are scheduled. The FIFO memory 34 for contention adjustment existing in the configuration of FIG. 7 of the second embodiment is eliminated, and all output links of the FIFO memory group 321 for each destination group are connected as one common output link, and the common output link is connected. The output link is directly connected to the incoming highway # (N + 1) in. The output link speed connected to each destination group FIFO memory 321 is the speed V of the incoming highway # (N + 1) in.

Next, the operation will be described. In the read schedule table 351, a destination group number to be instructed to be read by the CPU 25 is set. In FIG. 11, the FIFO for each destination group
An operation of instructing the memory group 321 to read is shown. The read schedule circuit 35 instructs the FIFO memory group 321 for each destination group to perform a read operation that returns (arounds one) six times. In [Reading schedule], the access order from addresses 0 to 5 of the reading schedule table 351 is indicated by transition arrows connecting the addresses 0,. Also, in the six data areas of the read schedule table 351 corresponding to the addresses 0,.
The destination group number set by the CPU 25 is described.
In the [reading schedule] in the reading schedule circuit 35, the transition between addresses occurs every time the time t in the second embodiment has elapsed by one.

Therefore, if the address 0 of the read schedule table 351 is selected at t = 0, the destination group number # 0 which is the data of the read schedule table 351
Is read. As a result, the read schedule circuit 35
, A copy cell read instruction is issued to the destination group FIFO memory of G # 0. According to the read instruction,
If there is cell queuing in the G # 0 destination group FIFO memory, the copy cell is output to the incoming highway # (N + 1) in.

Similarly, at t = 1, the destination group number # 3, which is the data of the read schedule table 351 is read, and a copy cell read instruction is issued to the destination group FIFO memory of G # 3. If there is cell queuing in the FIFO memory for each destination group, the copy cell is output to the incoming highway # (N + 1) in.

Similarly, at t = 2, FI by destination group of G # 0
If the FO memory has cell queuing, the copy cell is output to the incoming highway # (N + 1) in.

Similarly, at t = 3, FI by destination group of G # 1
If the FO memory has cell queuing, the copy cell is output to the incoming highway # (N + 1) in.

Similarly, at t = 4, FI for each destination group of G # 0
If the FO memory has cell queuing, the copy cell is output to the incoming highway # (N + 1) in.

Similarly, at t = 5, FI for each destination group of G # 2
If the FO memory has cell queuing, the copy cell is output to the incoming highway # (N + 1) in.

At t = 6, the read instruction is returned to the same as at t = 0, and the same operation as at t = 0 is repeated. Thereafter, the same read instruction as in t = 1 to t = 6 is repeated.

According to this embodiment, for each destination group
Since the read schedule circuit controls the multiplexing of the copy cell output from the FIFO memory based on the setting of the read schedule, it is possible to flexibly control the multiplexing contention, and at the same time, the FIFO memory for contention adjustment becomes unnecessary. Become.

Embodiment 4 FIG. 12 is a configuration diagram showing another embodiment of the cell broadcasting device using the spatial trunk system according to the present invention, and shows a configuration inside a copy server. In the figures, the same symbols indicate the same or corresponding parts.
The copy server 23 includes the following components, and generates a number c (≦ N) of copy cells specified by the call processor 25 and outputs the copy cells to the output link. 231 is an internal identifier extraction circuit for extracting an internal identifier written in the ATM cell header,
232 is an RTBL search circuit that reads data from the routine table RTBL233 up to k (≦ N) times based on the internal identifier, and 236 is an RTB
A header FIFO memory for temporarily storing an input internal identifier to cope with a search waiting for L, and a header FIFO memory 233 corresponding to an internal identifier in an input ATM cell header for broadcasting a cell under the control of the call processor 25 at the time of calling. Routine table RTB that registers the code tag of the reporting highway and the new VPI / VCI
L and 234 are cell buffers for storing input ATM cells as they are, 235 is a cell header replacement circuit for replacing the input highway code tag and new VPI / VCI with the input ATM cells of the cell buffer 234, and 30 is a cell header replacement circuit 235. This is a copy cell read control circuit that adjusts the timing at which the generated copy cell is output to the switch 22. Copy cell control circuit
The configuration of 30 is the same as that of the first embodiment.

Next, the operation will be described. In the copy server 23, when an ATM cell is input from the output highway # (N + 1) out, the internal identifier extraction circuit 231 extracts the internal identifier from the ATM cell and transfers it to the RTBL search circuit 232. On the other hand, the entire ATM cell is transferred to the cell buffer 234 and held. In the RTBL 233, corresponding to the internal identifier under the control of the call processor 25 (1)
A set of a code tag specifying one of the outgoing highways # 1out to #Nout and (2) a VPI / VCI which is a regular call identifier is c (≦
N) pieces are registered. RTBL search circuit 232 is header FIFO
RTB using the internal identifier at the beginning of memory 236 as a search key
By searching L233, only (1) a code tag for routing the ATM cell to one of the outgoing highways # 1out to #Nout and (2) only k k pairs of regular VPI / VCI are obtained. .

Next, the cell header reordering circuit 235 reads the ATM cell from the cell buffer 234, and converts the ATM cell into one of a set of k code tags and a regular VPI / VCI retrieved based on the internal identifier. Replace the FIF in the copy cell read control circuit 30
Write to O memory (not shown). The operation of the cell header replacement circuit 235 is performed the same number of times as the maximum search number k (≦ N) instructed by the call processor 25. header
The FIFO memory 236 reads the internal identifier at the head from the header FIFO memory 236 until the number of registrations c ≦ k × i (i = 0, 1,...) Corresponding to the internal identifier at the head becomes i times. Not
Registration information (code tags, new VPI / VC
I) ask. Then, at the time of the i-th search for which c ≦ k × i (i = 0, 1,...) For the first time, the first internal identifier is the header FIFO.
It is read from the memory 236.

According to this embodiment, when broadcasting, RT
High-speed processing is performed to search for the BL 233, change the code tag in the cell header changing circuit 235, change or assemble the copy cell to a new VPI / VCI, and write to the copy cell read control circuit 30 continuously c times. It was necessary, but it was not affected by the number of broadcasts c. By setting a limit of performing k times in succession, if the operation speed was c> k, k / c
Slowed down. Such a lower speed facilitates hardware design.

There are several configurations of RTBL233. FIG.
3 shows a configuration example of the RTBL. In this example, the internal identifier is set by CPU 25 from 0 to 4095. For one internal identifier, among the code tags # 0 to # 31, only some code tags that copy ATM cells for broadcasting are flagged {1}, while other The code tag is set to the state with the flag lowered {0}.
Since the flag states of all the code tags are searched at once from the RTBL 233 using a certain internal identifier as a key, the search processing can be speeded up. At the same time, VPI / VCI search also searches all VPI / VCIs at once using the internal identifier as a key, and flag status
Only VPI / VCI at the bit position corresponding to the code tag of “1” is processed as valid data.

FIG. 14 shows another configuration example of the RTBL. An internal identifier and a broadcast number are set in advance by the CPU 25. In this example, the internal identifier is set in a range from 0 to 4095, and the broadcast number is set in a range from 0 to 63. One internal identifier has a code tag, a VPI / VCI, and a valid / invalid flag corresponding to each of the broadcast numbers 0 to c-1, and a total of c sets (corresponding to the cell copy number c) ) Is set. The valid / invalid flag is set to a state where the flag is raised {1} when the data of the destination group for the broadcast number of a certain internal identifier is valid, and to a state where the flag is lowered {0} when invalid. Set. As a result, the flag state of one code tag can be retrieved from the RTBL 233 at a time using a certain internal identifier and a broadcast number as keys.

The valid / invalid flag is premised on the state that the flag is raised from broadcast number 0 to c-1 {1}, and thereafter, the state where the flag is lowered {0}. In order to search all code tags for a certain internal identifier, it is necessary to repeat the search by incrementing the broadcast number (c + 1) times until searching for the state {0} with the valid / invalid flag lowered. . Compared with the configuration example of FIG. 13, the data width of the RTBL 233 does not increase in proportion to the code tag (= the number of output highways), so that it is not necessary to increase the data bit width of the table in advance. Therefore, the table is not wasted, and the use efficiency of the memory is good. Further, when the number of code tags is increased and the data bit width of the table is exceeded, there is no need to reconfigure the table, so that waste of work can be reduced.

FIG. 15 shows still another configuration example of the RTBL, in which the valid / invalid flag in FIG. 14 is replaced with an end bit flag (EB). The end bit flag is a broadcast number c among broadcast numbers 0 to c-1 corresponding to the cell copy number c in a certain internal identifier.
-1 (indicating the last broadcast number) with flag raised {1}, other broadcast numbers with flag lowered {0}
Set to ■. In order to search all code tags for a certain internal identifier, it is necessary to repeat the search by incrementing the broadcast number c times until searching for the state {1} in which the end bit flag is raised. As a result, the same effect as in FIG. 14 is obtained, but the setting is further cleared after the initial clear.
Since it is only necessary to raise the end bit flag of the end number to {1}, the setting process is easy.

Embodiment 5 FIG. FIG. 16 is a block diagram showing another embodiment of the cell broadcasting device using the spatial trunk system according to the present invention, and shows the configuration between the switch 22 and the copy server 23 of the cell broadcasting device. is there. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. Reference numeral 22 denotes a switch having a plurality of input highways input from the copy server 23 and a plurality of output highways output to the copy server 23, and reference numeral 40 denotes a plurality of output highways output from the switch 22 to the copy server 23. A multiplexing circuit 41 for time-division multiplexing of highways, and a demultiplexing circuit 41 for separating a plurality of incoming highways input from the copy server 23 to the switch 22.
Therefore, one copy server 23 is shared by a plurality of incoming and outgoing highways. Multiple outgoing highways # (N + 1) ou
t, ..., # (N + p) out speeds are Vin (1), ..., Vin (p)
It is. In addition, multiple incoming highways # (N + 1) in, ..., # (N + q) i
The speed of n is V (1),..., V (q), respectively. The speed of the input link of the copy server 23 is Vin, and the speed of the output link is V. p and q are natural numbers. Vp = Σi = 1, p Vin (i)
(That is, Vp is the sum of Vin (i) from i = 1 to p), Vq = Σi = 1, q V (i) (ie, Vq is the sum of V (i) from i = 1 to q The sum is taken).

Next, the operation will be described. When the ATM cell of the multicast call is input to the switch 22, the header converter
(VCC1) 21 _{1 to} 21 _N (not shown) are stored in the ATM cell at the copy server 23.
Switch 22 with a code tag for routing to the switch and an internal identifier instead of the new VPI / VCI.
Enter There are a total of p code tags, one for each of the p outgoing highways. For this reason, the switch 22 indicates the ATM cell of the x multicast calls with x (x is a natural number) different code tags to the output highway # (N +
1) Route to out to # (N + x) out at the same time. Where x ≦ p
It is. The multiplexing circuit 40 includes a plurality of output highways # (N + 1)
The ATM cells output from out to # (N + p) out are multiplexed by time division. The separation circuit 41 includes a plurality of input highways #
The multiplexed ATM cells from the copy server input to (N + 1) in to # (N + q) in are separated. However, Vq ≧ V and Vin ≧ Vp. The operations of the copy server 23 and the call processor 25 are the same as those of the conventional technology and other embodiments.

According to this embodiment, up to p ATM cells of a plurality of multicast calls which have been simultaneously input to the switch 22 can be simultaneously transmitted to the copy server 23, which is connected to the copy server 23 in the switch 22. It avoids using buffers for meeting on the outgoing highway. Also, since a plurality of broadcast processes can be handled simultaneously, the speed of the process can be increased.

Embodiment 6 FIG. 17 is a block diagram showing another embodiment of the cell broadcasting apparatus using the spatial trunk system according to the present invention. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. Switch 22 to copy server 23
Multiple output highways and copy server 23
Multiple highways input to switch 22 from
It has a configuration divided into r (r is a natural number) groups. 40 ₁ to 40 _r are multiplexing circuits for time-division multiplexing only a plurality of output highways assigned to each group, 41 ₁
To 41 _r separation circuit for separating only the plurality of incoming highways assigned to each group, 23 ₁ ~ 23 _r is copied server provided for each group, the switches shown in the fifth embodiment 22, 25 is a call processor for all of the r copy server 23 ₁ ~ 23 _r. Therefore, the configuration is such that the copy servers 23 ₁ ,..., 23 _r are associated with each of the r input / output highway groups.

A group in which a plurality of outgoing highways are bundled
1, ..., rate of r is obtained by summing the rates of the highway exit allocated within each group, respectively Vp _1, ..., a Vp _r. Also, the speeds of the groups 1,..., R that bundle a plurality of incoming highways are obtained by summing the speeds of the assigned incoming highways in each group, and Vq ₁ ,. _r .
Speed of the input link of the copy server 23 ₁ ~23 _r, respectively
Vin ₁ , ..., Vin _r . Speed of the output link of the copy server 23 ₁ ~23 _r is, V ₁ each, ..., it is a V _r. Where p ≧ r,
q ≧ r.

[0090] In the multiplexing circuit 40 ₁ to 40 _r, respectively group 1 were bundled highway out a plurality of, ..., are multiplexed in time division the ATM cells to be output from the r. In the demultiplexing circuits 41 _{1 to} 41 _r , a group in which a plurality of incoming highways are bundled
The ATM cells to be input to 1, ..., r are separated.

According to this embodiment, since a plurality of broadcast processes can be handled simultaneously for each group, not only can the process be speeded up, but also the group can be flexibly handled. Further, since the processing in the copy server 23 _{1-23 r} is dispersed, it is possible to suppress the processing speed of the copy server 23 _1-23 in _r lower. Therefore, by using the copy server used in FIG. 16 under the concept of grouping without any improvement, the scale of the broadcast processing device can be easily expanded, and the number of simultaneous processes can be increased.

In each of the above embodiments, the description has been made on the assumption that the FIFO memory stores copy cells. However, the present invention is not limited to this.
The same effect can be obtained by storing the address of the memory such as the AM (including the cell buffer 234 and the RTBL 233) in the FIFO memory.

[0093]

As described above, according to the first aspect, the copy server adjusts the output timing of the copy cell between the destination groups, so that the frequency of cell discarding at the switch can be reduced. Play.

According to the second aspect of the present invention, the copy server adjusts the output timing of the copy cells for each destination group, so that the frequency of cell discarding at the switch can be reduced.

According to the third aspect of the present invention, since the copy server is provided with the copy cell read control circuit for adjusting the output timing of the copy cell between the destination groups or for each destination group, the frequency of occurrence of cell discard in the switch is provided. Can be reduced.

According to the fourth aspect of the present invention, a copy cell storage address read control circuit is provided in the copy server, and a timing adjustment for giving an address to an output buffer memory or a common buffer memory storing copy cell data is performed. Since a copy cell storage address read control circuit is provided, the frequency of cell discarding at the switch can be reduced by indirectly adjusting the output timing of the copy cells.

Further, according to the fifth aspect, the copy cell read control circuit reads cells from the FIFO memory for each destination group in accordance with the periodic operation of the selector, thereby ensuring fairness among all the destination groups. There is an effect that reading can be performed.

According to the sixth aspect of the present invention, the copy cell read control circuit includes a copy cell continuous read count table in which the copy cell destination group number and the continuous read count are associated with each other. The copy cells are read and multiplexed continuously according to the following formula, and the copy cells are not queued in the destination group FIFO memory corresponding to the output highway group to which the continuous read count is 0 and the use is not allocated. This has the effect of enabling accurate reading.

According to the seventh aspect, the copy cell read control circuit reads cells from the FIFO memory for each destination group in accordance with the periodic operation of the multiplexing circuit, so that the copy cell read control circuit operates between all the destination groups. Fair reading is possible, and the FI for each destination group is determined according to the rate of time division multiplexing.
Since the operation speed of the FO memory group has been reduced, an effect is obtained that the hardware design becomes easy.

According to the eighth aspect, the multiplexing from the destination group FIFO memory to the contention adjustment FIFO memory is controlled by the setting of the shaping circuit, so that the multiplexing ratio between the groups can be flexibly adjusted. This has the effect that control is possible.

According to the ninth aspect, a plurality of destination group FIs are provided to each destination group shaping circuit.
Since the FO memories are provided in a one-to-many ratio, the size of the shaping circuit for each destination group can be reduced.

According to the tenth aspect, the multiplexing of the copy cell output from the FIFO memory for each destination group is controlled by the read schedule circuit based on the setting of the read schedule, so that the contention control of the multiplex can be flexibly controlled. This can be performed at the same time, and there is an effect that the conflict adjustment FIFO memory becomes unnecessary.

According to the eleventh aspect, at the time of broadcasting,
High-speed processing is performed to search the RTBL 233, change the code tag in the cell header changing circuit 235, change or assemble the copy cell to a new VPI / VCI, and write to the copy cell read control circuit 30 continuously c times. Although it was necessary, the operation speed was reduced by setting a limit of performing k times continuously without being affected by the number of broadcasts,
This has the effect of facilitating hardware design.

According to the twelfth aspect, the RTBL includes the internal identifier, the code tag corresponding to the internal identifier, and the VPI / VCI. Since the flag state is searched from the RTBL 233, the speed of the search process can be increased.

According to the thirteenth aspect, the RTBL includes an internal identifier, a broadcast number corresponding to the internal identifier,
Equipped with code tags, VPI / VCI, and valid / invalid flags, the data width of RTBL233 does not increase in proportion to the number of code tags (= number of output highways), so memory usage efficiency Is good. Further, when the number of code tags is increased and the data width of the table is exceeded, there is no need to reconfigure the table, so that there is an effect that waste of work can be reduced.

According to the fourteenth aspect, the RTBL includes an internal identifier, a broadcast number corresponding to the internal identifier,
Since a code tag and an end flag are provided, and the end flag is set to {1} only for the last number of the broadcast number, there is an effect that the setting process is easy.

According to the fifteenth aspect, a multiplexing circuit for multiplexing a plurality of input highways and a demultiplexing circuit for separating a plurality of output highways are provided on the input side and the output side of the copy server, respectively. Since the copy server is shared by a plurality of incoming and outgoing highways by being arranged, the switch 2
ATM for multiple multicast calls that were simultaneously input to 2
Up to p cells can be sent to the copy server 23 at the same time, so that it is possible to avoid using a buffer for queuing on the outgoing highway connected to the copy server 23 in the switch 22, and to perform a plurality of broadcast processes. Since they can be handled at the same time, there is an effect that the processing can be speeded up.

According to the sixteenth aspect, a plurality of incoming highways are grouped into several groups, and a multiplexing circuit for multiplexing for each group, and a plurality of output highways are separated for each group. And the demultiplexing circuit
Since the copy server is arranged on the input side and the output side of the copy server and shared by a plurality of input / output highways, not only can the processing be speeded up for each group, but also the group can be flexibly handled. It works. Further, since the processing in the copy server 231~23r is dispersed, it is possible to suppress the processing speed of the copy server 23 _1-23 in _r lower. Therefore, by using the copy server used in FIG. 16 under the concept of grouping without any improvement, the scale of the broadcast processing device can be easily expanded, and the number of simultaneous processes can be increased. It works.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of a cell broadcasting device using a spatial trunk system according to the present invention.

FIG. 2 is another principle explanatory diagram of the cell broadcasting device using the spatial trunk system according to the present invention.

FIG. 3 is a configuration diagram showing an embodiment of a cell broadcasting device using a spatial trunk system according to the present invention.

FIG. 4 is an explanatory diagram showing a copy cell read management and control method.

FIG. 5 is an explanatory diagram showing a copy cell read state according to a copy cell continuous read number table.

FIG. 6 is an explanatory diagram showing a copy cell reading situation when a 4-to-1 multiplexing circuit is used.

FIG. 7 is a configuration diagram showing another embodiment of the cell broadcasting device using the spatial trunk system according to the present invention.

FIG. 8: FIFO memory 4 for each destination group at time t = 0
(G # 0 to G # 3), and the destination group shaping circuit (G # 0
FIG. 3 is an explanatory diagram showing setting information of G # 3).

FIG. 9 is an explanatory diagram showing the queuing status of the contention adjustment FIFO memory over time t = 0, 1, 2, 3,.

FIG. 10 is an explanatory diagram showing a copy cell output status from the contention adjustment FIFO memory over time t = 0, 1, 2, 3,.

FIG. 11 is a configuration diagram showing another embodiment of the cell broadcasting device using the spatial trunk system according to the present invention.

FIG. 12 is a configuration diagram showing another embodiment of the cell broadcasting device using the spatial trunk system according to the present invention.

FIG. 13 is a diagram illustrating a configuration example of an RTBL.

FIG. 14 is a diagram showing another configuration example of the RTBL.

FIG. 15 is a diagram showing still another configuration example of the RTBL.

FIG. 16 is a configuration diagram showing another embodiment of the cell broadcasting device using the spatial trunk system according to the present invention.

FIG. 17 is a configuration diagram showing another embodiment of the cell broadcasting device using the spatial trunk system according to the present invention.

FIG. 18 is a configuration diagram of a conventional cell broadcasting device for wideband ISDN.

FIG. 19 is a configuration diagram of a cell broadcasting device using a conventional spatial trunk system.

20 is a configuration diagram illustrating a detailed configuration of a copy server 23 illustrated in FIG. 19;

FIG. 21 is an explanatory diagram showing an example of processing an ATM cell other than a multicast call.

FIG. 22 is an explanatory diagram showing a cell format input from incoming highways # 1in to #Nin.

23 is an explanatory diagram showing a cell format input from inputs 21 _{1 to} 21 _{N + 1 of the} switch 22. FIG.

FIG. 24 is an explanatory diagram showing a cell format to be output to outgoing highways # 1out to #Nout.

FIG. 25 is an explanatory diagram showing a cell format to be output to outgoing highway # (N + 1) out.

FIG. 26 is an explanatory diagram showing a cell format input from an input highway # (N + 1) in.

FIG. 27 is an explanatory diagram showing an example of processing an ATM cell of a multicast call.

[Explanation of symbols]

 Reference Signs List 21 header converter (VCC1) 22 switch 23 copy server 24 header converter (VCC2) 25 call processor (CPU) 30 copy cell read control circuit 31 copy cell storage address read control circuit 33 selector 34 contention adjustment FIFO memory 35 read Schedule circuit 40 multiplexing circuit 41 demultiplexing circuit 231 internal identifier extraction circuit 232 routing table (RTBL) search circuit 233 routing table (RTBL) 234 cell buffer 235 cell header replacement circuit 311 single FIFO memory 321 destination group FIFO memory group 322 destination Grouping shaping circuit group 351 Readout schedule table

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yasutaka Saito 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Munenori Tsuzuki 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F term in Ryo Denki Co., Ltd. (reference) 5K030 GA06 GA11 HA10 HB14 HB29 HC06 JA01 KA03 KA15 KA22 KX13 KX28 LB06 LC02 LD02

Claims (16)

[Claims] 1. A header conversion means for converting a header of an ATM cell into an internal header and, in the case of a broadcast, a specific internal identifier and outputting it to an incoming highway; Switching means for inputting from an entry highway, switching between the incoming highway and outgoing highway based on the internal header, and in the case of broadcasting, switching the ATM cell to a specific outgoing highway based on the internal identifier; A predetermined number of copies of the ATM cells input from the specific outgoing highway are copied based on the internal identifier, and an internal header is provided so that each of the obtained ATM cells (hereinafter referred to as copy cells) is transmitted to the respective outgoing highway. And a copy server for adding the ATM cell to the switching means, and outputting one ATM cell to a plurality of designated output cells. In the cell broadcast apparatus having a multicast function for routing copy the way,
The cell broadcasting device, wherein the copy server adjusts output timing of a copy cell between destination groups. 2. A header conversion means for converting a header of an ATM cell into an internal header, and in the case of a broadcast, converting the header into a specific internal identifier and outputting it to an incoming highway; Switching means for inputting from an entry highway, switching between the incoming highway and outgoing highway based on the internal header, and in the case of broadcasting, switching the ATM cell to a specific outgoing highway based on the internal identifier; A predetermined number of copies of the ATM cells input from the specific outgoing highway are copied based on the internal identifier, and an internal header is provided so that each of the obtained ATM cells (hereinafter referred to as copy cells) is transmitted to the respective outgoing highway. And a copy server for adding the ATM cell to the switching means, and outputting one ATM cell to a plurality of designated output cells. In the cell broadcast apparatus having a multicast function for routing copy the way,
A cell broadcasting device, wherein the copy server adjusts output timing of a copy cell for each destination group. 3. The cell broadcasting device according to claim 1, wherein the copy server includes a read control circuit for adjusting the output timing of the copy cells between the destination groups or for each destination group. 4. The copy server includes a copy cell storage address read control circuit that adjusts a timing of giving an address to a storage unit such as an output buffer memory or a common buffer memory storing copy cell data. The cell broadcasting device according to claim 1 or 2, wherein 5. The copy cell read control circuit includes a copy cell destination group FIFO memory and a selector, and reads and multiplexes copy cells fairly and periodically among all destination groups. 2. The cell broadcasting device according to 1. 6. The copy cell read control circuit includes a copy cell continuous read count table in which a destination group number of a copy cell is associated with a continuous read count, and reads and multiplexes copy cells according to the copy cell continuous read count table. The cell broadcasting device according to claim 1, wherein: 7. The copy cell read control circuit includes a copy memory for each destination group of copy cells and a multiplexing circuit for time division multiplexing, and reads and multiplexes copy cells fairly and periodically among all destination groups. Claim 1 characterized by the following:
A cell broadcasting device according to claim 1. 8. The cell broadcasting apparatus according to claim 2, wherein the copy cell read control circuit includes a plurality of destination group FIFO memories and a corresponding shaping circuit. 9. The cell broadcasting apparatus according to claim 8, wherein a plurality of destination group FIFO memories are provided for each destination group shaping circuit in a one-to-many ratio. 10. A copy cell read control circuit for queuing copy cells in groups in which some output highways of a switch are bundled without overlapping, for each destination group
A FIFO memory group, a read schedule circuit for controlling read of a copy cell from the FIFO memory for each destination group,
The cell broadcast apparatus according to claim 1, further comprising: a read schedule table that schedules a destination group from which a copy cell is read. 11. A copy server for extracting an internal identifier written in an ATM cell header and an internal identifier in an input ATM cell header for broadcasting a cell under the control of a call processor at the time of calling. A broadcast table storing a new VPI / VCI, an RTBL search circuit for reading data from the RTBL a plurality of times based on the internal identifier, and a search for the RTBL. A header FIFO memory for temporarily storing an input internal identifier to cope with waiting, a cell buffer for storing input ATM cells, and an input AT for the cell buffer;
High-speed output to M cells, a cell header replacement circuit that replaces a new VPI / VCI, and a copy cell read control circuit that adjusts the timing of outputting a copy cell generated by the cell header replacement circuit to a switch. The cell broadcasting device according to claim 1 or 2, wherein 12. The cell according to claim 11, wherein the RTBL includes an internal identifier, a code tag corresponding to the internal identifier, which is information for routing to an outgoing highway, and a VPI / VCI. Broadcast device. 13. The RTBL includes an internal identifier, a broadcast number corresponding to the internal identifier, a code tag, a VPI / VCI
The cell broadcast apparatus according to claim 11, further comprising: a valid / invalid flag. 14. The RTBL includes an internal identifier, a broadcast number corresponding to the internal identifier, a code tag, a VPI / VCI
The cell broadcast apparatus according to claim 11, further comprising: an end flag and an end flag, wherein the end flag is set to {1} only for the last number of the broadcast number. 15. A copy server for generating a copy cell by copying a plurality of ATM cells at the time of broadcasting, a plurality of input highways input from the copy server, and a plurality of output highways output to the copy server. A switch having a highway, a multiplexing circuit for time-division multiplexing a plurality of output highways output from the switch to the copy server, and a plurality of input highways input from the copy server to the switch. 3. The cell broadcasting device according to claim 1, further comprising a separation circuit. 16. A plurality of output highways output from the switch to the copy server and a plurality of input highways input from the copy server to the switch are divided into a plurality of groups, and a plurality of highways assigned to each group are divided. A multiplexing circuit for time-division multiplexing only outgoing highways, a demultiplexing circuit for separating only a plurality of incoming highways assigned to each group, and a copy server provided for each group. The cell broadcasting device according to claim 1 or 2, wherein: