JP2000115174A - Packet line processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a packet line processor of simple constitution capable of accelerating a device, preventing the increase of memory consumption in the entire device, fixing the processing time of respective packets and time division multiplexing and processing the packets. SOLUTION: This packet line processor is provided with a line side reception part 3 for receiving variable length packets from a line 2, buffer memories 4 and 7 divided into plural pages, a switch side transmission part 5 for transmitting the packets to an external switching devices 1, a switch side reception part 6 for receiving fixed length packets from the external switching device 1 and a line side transmission part 8 for transmitting the variable length packets to the line 2. The line side reception part 3 is provided with a reception control packet generation part 10 for generating a reception control packet whose contents are the page information of the packet stored in a reception buffer memory 4 and sending it to the switch side transmission part 5. The switch side reception part 6 is provided with a transmission control packet generation part 15 for generating a transmission control packet whose contents are the page information of the stored packet and sending it to the line side transmission part 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet line processing apparatus, and more particularly to a packet line processing apparatus connected between an external switching device for switching fixed-length packets at high speed and a line for transmitting variable-length packets. Related to the device.

[0002]

2. Description of the Related Art This type of packet line processing apparatus is used, for example, in a packet switching apparatus, a router and the like. FIG.
1 is a block diagram showing a configuration of a conventional packet line processing device. As shown in FIG. 5, a conventional packet line processing device includes a plurality of line-side receiving units 51 that receive variable-length packets from a plurality of lines 50, and a variable-length packet received by the line-side receiving unit 51. A receiving buffer memory 52 for storing, a switch-side transmitting unit 53 for transmitting a packet stored in the receiving buffer memory 52 to the external switching device 54, and a switch-side receiving unit 55 for receiving a fixed-length packet from the external switching device 54. And its switch-side receiving unit 5
5 has a transmission buffer memory 56 for storing the fixed-length packets received in 5 and a plurality of line-side transmission units 57 for transmitting the packets stored in the transmission buffer memory 56 to the line 50 as variable-length packets.

[0003] The conventional packet line processing apparatus also has a line 5
0, a control memory 59 for storing information related to the storage of the packet in the reception buffer memory 52, and a switch-side transmission unit based on the information in the control memory 59. A microprocessor 60 for controlling the operation of the communication unit 53; and a contention control unit 61 for controlling a process of transmitting a contention packet to the line 50.
And a control memory 62 for storing information related to storage in the transmission buffer memory 56, and a microprocessor 63 for controlling the operation of the line-side transmission unit 57 based on the information in the control memory 62.

Writing of a packet from the line side receiving unit 51 to the receiving buffer memory 52 is performed by using a DMA (Direct Memory).
Access) transfer, and the completion of the transfer is notified to the microprocessor 60 by an interrupt from the CPU, and the microprocessor 60 that has received the notification reads the information in the control memory 59 and performs processing.

The transmission of a packet to the line 50 is performed in the same manner as described above.

[0006]

With the recent increase in the line speed and the speed of the external switching unit, there has been a demand for a high-speed operation of the packet line processing unit. In addition, due to the increase in speed, the memory consumption in the entire apparatus tends to increase.

However, in the conventional packet line processing device, a DMA controller or the like is provided in an input / output circuit with the line, and is operated according to an instruction from a microprocessor to broadcast or schedule data. Has been moved to each processing mechanism inside the apparatus, and it is difficult to increase the speed of the apparatus, and it is also difficult to prevent an increase in memory consumption in the entire apparatus.

In a conventional packet line processing device,
Information necessary for reading and writing data, such as buffer memory pointer information, is stored in a dedicated control memory. Completion of DMA transfer is notified to the microprocessor by an interrupt of the CPU. Variations occur. For this reason, it has been difficult to process the packets by time division multiplexing.

Furthermore, the conventional packet line processing device requires a control memory, a microprocessor and a contention control unit, and thus has a complicated configuration.

An object of the present invention is to provide a packet line processing apparatus which can increase the speed of the apparatus and can prevent an increase in memory consumption in the entire apparatus.

Another object of the present invention is to provide a packet line processing apparatus in which the processing time of each packet is constant and the packet can be processed by time division multiplexing.

Another object of the present invention is to provide a control memory,
An object of the present invention is to provide a packet line processing apparatus which does not require a microprocessor and a contention control unit and has a simple configuration.

[0013]

SUMMARY OF THE INVENTION The present invention relates to a packet line processing device connected between an external switching device for switching fixed-length packets and a line through which variable-length packets are transmitted. A line-side receiving unit that receives long packets, a variable-length packet received by the line-side receiving unit is stored, and a reception buffer memory divided into a plurality of pages of a predetermined buffer size and stored in the reception buffer memory And a switch-side transmitting unit for transmitting the received packet to the external switching device. The line-side receiving unit generates a reception control packet containing page information of the packet stored in the reception buffer memory, and receives the reception control packet. A reception control packet generation unit that sends the control packet to the switch-side transmission unit, wherein the switch-side transmission unit receives the reception control packet from the reception control packet generation unit; A control unit for controlling to transmit a packet packets stored in the reception buffer memory based on the page information of the external switching device, it is characterized in.

According to another aspect of the present invention, there is provided a packet line processing apparatus comprising: a switch-side receiving unit for receiving a fixed-length packet from an external switching unit; a fixed-length packet received by the switch-side receiving unit; A transmission buffer memory divided into a plurality of pages of a size, and a line-side transmission unit for transmitting a packet stored in the transmission buffer memory to a line as a variable-length packet, and a switch-side reception unit includes: A transmission control packet generation unit that generates a transmission control packet containing page information of the packet stored in the memory and sends the transmission control packet to the line-side transmission unit; A control unit for controlling transmission of the packet to the line based on page information of the transmission control packet sent from the unit. It is intended to.

Still another aspect of the present invention provides a packet line processing apparatus for receiving a variable length packet from a line, storing the variable length packet received by the line side receiving unit, and storing a predetermined buffer size. A receiving buffer memory divided into a plurality of pages, a switch-side transmitting unit for transmitting packets stored in the receiving buffer memory to the external switching device, and a switch-side receiving unit for receiving fixed-length packets from the external switching device And a transmission buffer memory storing fixed-length packets received by the switch-side reception unit and divided into a plurality of pages of a predetermined buffer size, and a packet stored in the transmission buffer memory as a variable-length packet. And a line-side transmitting unit that transmits the page information of the packet stored in the receiving buffer memory. A reception control packet generation unit that generates a reception control packet to be transmitted and sends the reception control packet to the switch-side transmission unit, wherein the switch-side transmission unit transmits a page of the reception control packet transmitted from the reception control packet generation unit. A control unit that controls the packet to be transmitted to the external switching device based on the information, and the switch-side receiving unit includes:
A transmission control packet generation unit that generates a transmission control packet containing page information of the packet stored in the reception buffer memory and sends the transmission control packet to the line-side transmission unit; Having a control unit that controls to transmit the packet to the line based on the page information of the transmission control packet sent from the packet generation unit,
It is characterized by the following.

The switch-side transmission section includes a reception buffer memory management section having a link list for linking and managing each page of the reception buffer memory, a link list of the reception buffer memory management section, and a page of the reception control packet. A packet transmission unit that transmits a packet in the reception buffer memory to the external switching device based on the information, and the line-side reception unit refers to the link list in the reception buffer memory management unit and stores the variable-length packet in the reception buffer memory. It may have a packet receiving unit for storing.

The switch-side receiving section refers to a transmission buffer memory management section provided with a link list for linking and managing each page of the transmission buffer memory, and refers to the link list of the transmission buffer memory management section to fix the page. A packet receiving unit that stores the long packet in the transmission buffer memory; and the line-side transmission unit transmits the packet in the transmission buffer memory to the line based on the link list of the transmission buffer memory management unit and the page information of the reception control packet. It may have a packet transmission unit.

A plurality of line-side receiving units are provided corresponding to the plurality of lines, and a multiplexing unit for time-division multiplexing a packet from each line is provided between the line-side receiving unit and the receiving buffer memory. Good.

A plurality of line-side transmission units are provided corresponding to the plurality of lines, and a demultiplexing unit is provided between the line-side transmission unit and the transmission buffer memory for separating a time-division multiplexed packet into each line. May be.

The reception buffer memory may be divided into pages having the same buffer size as the data length switched by the external switching device.

The transmission buffer memory may be divided into pages having the same buffer size as the data length switched by the external switching device.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the packet line processing device of the present invention.

As shown in FIG. 1, the packet line processing device of the present invention is connected between an external switching device 1 for switching fixed-length packets and a line 2 for transmitting variable-length packets.

The packet line processing apparatus of the present invention
A line-side receiving unit 3 for receiving a variable-length packet from the network, a receiving buffer memory 4 storing the variable-length packet received by the line-side receiving unit 3 and divided into a plurality of pages of a predetermined buffer size; A switch-side transmitting unit 5 for transmitting the packet stored in the receiving buffer memory 4 to the external switching device 1, a switch-side receiving unit 6 for receiving a fixed-length packet from the external switching device 1, and a switch-side receiving unit 6 , A transmission buffer memory 7 divided into a plurality of pages of a predetermined buffer size, and a packet stored in the transmission buffer memory 7 transmitted to the line 2 as a variable length packet. And a side transmission unit 8.

The line-side receiving section 3 generates a packet receiving section 9 for storing the variable-length packet in the receiving buffer memory 4 and a receiving control packet containing page information of the packet stored in the receiving buffer memory 4, It has a reception control packet generator 10 that sends the reception control packet to the switch-side transmitter 5.

The switch-side transmission unit 5 includes a reception buffer memory management unit 11 having a link list for linking and managing each page of the reception buffer memory 4, and a reception control packet transmitted from the reception control packet generation unit 10. A control unit 12 for controlling transmission of the packet to the external switching device 1 based on the page information of the packet, and a packet stored in the reception buffer memory 4 based on the link list of the reception buffer memory management unit 11 and the page information of the reception control packet. And a packet transmission unit 13 that transmits the packet to the external switching device 1.

The control unit 12 of the switch-side transmitting unit 5 manages the schedule of the packet transmission time, and in the case of the broadcast transmission, copies the reception control packets necessary for the transmission.

The packet receiving section 9 of the line side receiving section 3 stores the variable length packet in the receiving buffer memory 4 with reference to the link list of the receiving buffer memory managing section 11 and receives the page information of the stored packet. It is sent to the control packet generator 10.

The switch-side receiving section 6 includes a transmission buffer memory management section 14 having a link list for linking and managing each page of the transmission buffer memory 7, and a transmission including page information of a stored packet. A transmission control packet generation unit 15 that generates a control packet and sends the transmission control packet to the line-side transmission unit 8 and a link list of the transmission buffer memory management unit 14 refers to a fixed-length packet from the external switching device 1. A packet reception unit 16 that stores the page information of the stored packet to the transmission control packet generation unit 15 while storing the packet information in the transmission buffer memory 7.

The line-side transmitting section 8 includes a control section 17 for controlling transmission of a packet stored based on the page information of the transmission control packet sent from the transmission control packet generating section 15 to the line 2, and a transmission buffer. A packet transmission unit for transmitting a packet in the transmission buffer memory to the line based on the link list of the memory management unit and the page information of the reception control packet.

The control unit 17 of the line side transmission unit 8 manages the schedule of the packet transmission time, and in the case of the broadcast transmission, copies the transmission control packets required for the transmission.

The reception buffer memory 4 and the transmission buffer memory 7 are divided into the same buffer size as the data length switched by the external switching device 1. Hereinafter, one divided unit is called a page, and the head address of each page is called a pointer.

The reception buffer memory management unit 11 of the switch-side transmission unit 5 manages unused pages of the reception buffer memory 4 and generates a link list for packets having a data length exceeding one page.

The transmission buffer memory management unit 14 of the switch side reception unit 6 manages unused pages of the transmission buffer memory 7 and generates a link list for packets having a data length exceeding one page.

FIG. 4A is an explanatory diagram for explaining an example of a buffer memory, and FIG. 4B is an explanatory diagram for explaining an example of a link list.

The buffer memories 4 and 7 are, for example, as shown in FIG.
As shown in (A), n of page 0 to page (n-1)
Pages, and each page has pointers 0, 1, 2
(N-1) is given (the data length of one page is, for example, 64 bytes). And page 1 is page 3
, Page 2 is linked to page 5, page 3 is linked to page 4, page 4 is linked to page 7, page 5 is linked to page 6, and so on. Has become. Therefore, the packets are stored in the order of page 1 → 3 → 4 → 7, and the next packet is stored in the order of page 2 → 5.

On the other hand, as shown in FIG. 4B, the link list 20 defines the link relation of each page, and includes as a data a pointer of the page to which the next link is to be made.
For example, since the next link destination of page 1 is page 3, the data of the address (pointer) 1 of the link list is 3.

Each packet is managed by such a link list, and a link list is formed for pages not used as packets. When a page to be written to the buffer memory becomes necessary, the pages are taken in order from the free list that is not used to form a link list of valid packets. The pages that have become unnecessary after transmission are linked to the end of this unused page (unused free list) to be used when a new packet comes in the future.

Next, the operation of the packet line processing device of the present invention will be described. The packet receiving unit 9 of the line side receiving unit 3
When the pointer of the unused page is received from the reception buffer memory management unit 11 of the switch-side transmission unit 5 and a packet of one page is received, it is written into the reception buffer memory 4 and the pointer of the next page is stored in the switch-side transmission unit 5. Is received from the reception buffer memory management unit 11.

The reception control packet generator 10 of the line side receiver 3 stores the last page packet in the reception buffer memory 4.
At the same time, the switch-side transmitting unit 5 controls the reception control packet containing the page information such as the pointer of the first page of the link list constituting the packet, the number of used pages of the packet, and the effective packet length of the last page. Transmit to the unit 12.

The switch-side transmission unit 5 puts the reception control packet in the transmission queue of the switch-side transmission unit 5 and receives the packet at the transmittable time based on the page information of the reception control packet and the link list of the reception buffer memory management unit 11. The packet in the buffer memory 4 is read out, and the packet transmission unit 1
3 to the external switching device 1.

On the other hand, every time a packet is received from the external switching device 1, the packet receiving unit 16 of the switch-side receiving unit 6 stores the packet in the page of the transmission buffer memory 7 while referring to the link list of the transmission buffer memory management unit 14. I do.

The transmission control packet generator 15 of the switch-side receiver 6 writes the last page in the transmission buffer memory 7 and simultaneously transmits the transmission control packet to the controller 17 of the line-side transmitter 8.

The line-side transmitting section 8 puts the transmission control packet in the transmission queue of the line-side transmitting section 8 and, based on the page information of the transmission control packet and the link list of the transmission buffer memory management section 14 when the transmission possible time comes. , Reads out the packet from the transmission buffer memory 7 and sends the packet
8 to the line 2.

FIG. 2 is a block diagram showing the configuration of another packet line processing device according to the present invention. As shown in FIG.
This packet line processing device is provided with a plurality of line-side receiving units 3 and a plurality of line-side transmitting units 8 corresponding to the plurality of lines 2, and each line is connected between the line-side receiving unit 3 and the receiving buffer memory 4. A multiplexing unit 30 for time-division multiplexing of packets from the transmission line 2 is provided. A multiplexing / demultiplexing unit 31 for separating the time-division multiplexed packets into each line 2 is provided between the line side transmission unit 8 and the transmission buffer memory 7 ing.

The configuration of the line-side receiving unit 3, the receiving buffer memory 4, the switch-side transmitting unit 5, the switch-side receiving unit 6, the transmitting buffer memory 7, and the line-side transmitting unit 8 is shown in FIG.
Is the same as that shown in FIG.

In this packet line processing device, information on unused pages in the reception buffer memory 4
Is configured to not conflict. Each line side receiver 3
Receives a packet from the line 2 and writes the packet to a given unused page. At the same time as writing, a pointer for the next unused page is requested to the switch-side transmitting unit 5, and the switch-side transmitting unit 5 sends an unused page pointer to the requested line-side receiving unit 3. The line-side receiving unit 3 sends the reception control packet to the control unit 12 of the switch-side transmitting unit 5 at the same time as finishing writing the last page packet.

This reception control packet is used only inside the device as a substitute for the received packet, and contains page information such as the pointer of the first page of the received packet, the number of used pages of the packet, and the effective packet length of the last page. And The control unit 12 of the switch-side transmitting unit 5 that has received the reception control packet performs schedule management of the transmission time and copies the reception control packet in the case of the broadcast transfer. When the determined transmission time comes, the packet transmission unit 13 is instructed to read the packet from the reception buffer memory 4 and transmit the packet to the external switching device 1. When all the packets are transmitted, the link list of this packet is passed to the reception buffer memory management unit 11, and the link list of this packet is linked to the end of the link list of the unused page.

The line transmitting side is almost the same as the line receiving side. The switch side receiving section 6 manages the unused pages of the transmission buffer memory 7 and stores the packets received from the external switching device 1 in the transmission buffer memory 7. A link list of packets to be written and stored in the transmission buffer memory 7 is generated.

At the same time that the last page has been written, the switch-side receiver 6 transmits a transmission control packet to the line-side transmitter 8 to be transmitted. Upon receiving this, the line side transmission unit 8 determines the transmission time, reads out the packets in the transmission buffer memory 7 sequentially from the top page obtained from the page information of the transmission control packet at the transmission time, and sends the packet to the line 2 from the packet transmission unit 18. Send out.

Since the link list of the transmission buffer memory 7 on the transmission side is managed by the switch side reception unit 6, the transmission of the packet from the transmission buffer memory 7 to the line 2 is started simultaneously with the transmission of the packet by the switch side reception unit 6. It requests the buffer memory management unit 14 for the pointer of the page that is the next link destination, and transfers it sequentially. When the transfer of the last packet is completed, the transfer completion of the packet is notified to the transmission buffer memory management unit 14 of the switch side reception unit 6. The transmission buffer memory management unit 14 links the used link list to the end of the unused page link list.

FIG. 3 is a sequence diagram for explaining the operation on the receiving side in the packet line processing apparatus shown in FIG.

Before receiving a packet from the line 2, the reception buffer memory management unit 11 of the switch side transmission unit 5 sends an unused page pointer to the packet reception unit 9 of the line side reception unit 3. The reception buffer memory management unit 11 of the switch-side transmission unit 5 uses this pointer as the head of the packet link list. When a packet is received from the line 2, the packet receiving unit 9 of the line-side receiving unit 3 writes the packet from the received page pointer. During this writing, the packet receiving unit 9 of the line side receiving unit 3 requests the reception buffer memory management unit 11 of the switch side transmitting unit 5 for the pointer of the next page. Prepare to continue writing. When the writing of one page is actually completed, the received packets are written in order from the pointer of the next page. Like the operation of the previous page, the pointer of the next page is requested and obtained during packet writing.
When the writing of the last page is completed, the reception control packet generation unit 10 of the line side reception unit 3 sends the reception control packet to the control unit 12 of the switch side transmission unit 5, and at the same time, the packet reception unit 9 Request and get a page pointer for

The control unit 12 of the switch-side transmission unit 5 that has received the reception control packet performs scheduling for controlling the transmission time. In the case of broadcast transmission, the reception control bucket is copied and scheduled. When the transmission time comes, the packet transmission unit 13 reads the packet in the reception buffer memory 4 from the pointer of the first page based on the page information of the reception control packet, and transmits the packet to the external switching device 1. Thereafter, the packet transmission unit 13 sequentially obtains page pointers from the reception buffer memory management unit 11,
The packet in the reception buffer memory 4 is sent to the external switching device 1. When all the packets are transmitted, the reception buffer memory management unit 11 links the used link list to the unused page list.

The above operation is similar to the operation on the side transmitting a packet to the line 2. That is, the packet receiving unit 16 of the switch-side receiving unit 6 sequentially writes the packets received from the external switching device 1 into the transmission buffer memory 7 and simultaneously generates a packet link list. All the packets for one packet are written in the transmission buffer memory 7 and at the same time a transmission control packet is sent to the control unit 17 of the line side transmission unit 8.

The line-side transmitting unit 8 that has received the transmission control packet
The control unit 17 performs scheduling for controlling the transmission time. When performing broadcast transfer, the transmission control bucket is copied and scheduled. Packet transmission unit 1
When the transmission time is reached, the packet 8 reads out the packet in the transmission buffer memory 7 from the pointer of the first page based on the page information of the transmission control packet, and transmits the packet to the line 2. 1
During the page transmission, the packet transmission unit 18 obtains the next page pointer from the transmission buffer memory management unit 14 of the switch-side reception unit 6. Thereafter, the page pointer is sequentially obtained from the transmission buffer memory management unit 14 of the switch-side reception unit 6, and the packet of the transmission buffer memory 7 is transmitted to the line 2. When transmitting all the packets, the transmission buffer memory management unit 14 links the used link list to the unused page list.

In the packet line processing apparatus shown in FIG. 2, the line side receiving unit 3 and the line side transmitting unit 8 corresponding to the plurality of lines 2
Can be processed by time-division multiplexing by defining a time slot in which. Operates. When a plurality of lines 2 are bundled by time division multiplexing, an elastic buffer having a length equal to or greater than the maximum packet length input / output from the line 2 at intervals of a frame pulse for operating the time division multiplexing is provided to the line side receiving unit 3 and the line side transmitting unit 8. Implement. In this case, since the packet speed of the line 2 is slower than the writing speed to the buffer memory and the number of lines is large, one frame worth of packets is temporarily stored in the elastic buffer for each line.
It will write to the buffer memory at once.

The present invention is not limited to the above-described embodiment, and various changes can be made within the technical scope described in the claims. For example, the contents of the page information of the reception control packet and the transmission control packet may include a pointer of the first page of the packet, a pointer of the last page, and an effective packet length of the last page.

[0059]

According to the packet processing apparatus of the present invention, a reception control packet and a transmission control packet which substitute an actual packet while storing an actual packet in the buffer memory are generated, and these control packets are used inside the apparatus. By doing so, there is no need to copy the actual packet or move the data from the memory to the memory in the scheduling or the broadcast transfer, and it is sufficient to copy the control packet. Therefore, it is possible to prevent an increase in memory consumption in the entire apparatus.

Further, in the management of the buffer memory used for transmitting and receiving packets, each operation can be pipelined so as not to require the operation of the processor other than the setting of the configuration packet necessary for starting the operation. Higher speed can be achieved.

Further, since the intervention of the microprocessor is unnecessary, there is no variation in the processing time of each packet generated due to an interrupt or the like generated in the processor processing. Therefore, the processing time becomes constant, and it becomes possible to process the packets by time division multiplexing.

Further, since the control memory, the microprocessor and the conflict control unit are not required, the configuration is simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a packet line processing device according to the present invention.

FIG. 2 is a block diagram showing a configuration of another packet line processing device of the present invention.

FIG. 3 is a sequence diagram for explaining an operation of the packet line processing device shown in FIG. 2;

FIG. 4A is an explanatory diagram for explaining a buffer memory, and FIG. 4B is an explanatory diagram for explaining a link list.

FIG. 5 is a block diagram showing a configuration of a conventional packet line processing device.

[Explanation of symbols]

 1: External switching device 2: Line 3: Line side receiving unit 4: Receiving buffer memory 5: Switch side transmitting unit 6: Switch side receiving unit 7: Transmission buffer memory 8: Line side transmitting unit 9: Packet receiving unit 10: Receiving Control packet generation unit 11: reception buffer memory management unit 12: control unit 13: packet transmission unit 14: transmission buffer memory management unit 15: transmission control packet generation unit 16: packet reception unit 17: control unit 18: packet transmission unit 20: Link list 30: Multiplexer 31: Multiplexer / demultiplexer

Claims (9)

[Claims] 1. A packet line processor connected between an external switching device for switching fixed-length packets and a line through which variable-length packets are transmitted, wherein the line side receives variable-length packets from the line. A receiving unit, a receiving buffer memory storing variable-length packets received by the line-side receiving unit, divided into a plurality of pages of a predetermined buffer size, and the external exchange of the packets stored in the receiving buffer memory. And a switch-side transmission unit for transmitting to the device, wherein the line-side reception unit generates a reception control packet containing page information of the packet stored in the reception buffer memory, and A reception control packet generation unit for transmitting to the switch-side transmission unit, wherein the switch-side transmission unit receives the reception control packet from the reception control packet generation unit. The packets stored in the reception buffer memory based on the page information of the control packet comprises a control unit for controlling to transmit to said external switching device, the packet line processor, characterized in that. 2. A packet line processing device connected between an external switching device for switching fixed-length packets and a line for transmitting variable-length packets, the fixed-length packet being received from the external switching device. A switch-side receiver, a fixed-length packet received by the switch-side receiver, a transmission buffer memory divided into a plurality of pages of a predetermined buffer size, and a packet stored in the transmission buffer memory variable. A line-side transmitting unit for transmitting to the line as a long packet, and the switch-side receiving unit generates a transmission control packet containing page information of the packet stored in the transmission buffer memory, A transmission control packet generation unit for transmitting a transmission control packet to the line side transmission unit, wherein the line side transmission unit A control unit for controlling to transmit the packet to the line based on the page information of the transmission control packet sent from the preparative generation unit, the packet line processor and wherein the. 3. A packet line processing device connected between an external switching device for switching fixed-length packets and a line on which variable-length packets are transmitted, wherein the line side receives variable-length packets from the line. A receiving unit, a receiving buffer memory storing variable-length packets received by the line-side receiving unit, divided into a plurality of pages of a predetermined buffer size, and the external exchange of the packets stored in the receiving buffer memory. A switch-side transmitting unit for transmitting to the device, a switch-side receiving unit for receiving a fixed-length packet from the external switching device, and a fixed-length packet received by the switch-side receiving unit. A transmission buffer memory divided into a plurality of packets, and a packet stored in the transmission buffer memory as a variable-length packet. A line-side transmitting unit for transmitting, wherein the line-side receiving unit generates a reception control packet containing page information of the packet stored in the reception buffer memory, and transmits the reception control packet to the switch-side transmission. A reception control packet generation unit that sends the packet to the external switching device based on page information of the reception control packet sent from the reception control packet generation unit. A control unit for controlling, wherein the switch-side receiving unit generates a transmission control packet containing page information of the packet stored in the reception buffer memory, and transmits the transmission control packet to the line-side transmission unit. A control packet generating unit, wherein the line-side transmitting unit is configured to transmit the control packet based on page information of the transmission control packet transmitted from the transmission control packet generating unit. There has a control unit for controlling to transmit the packet to the line, the packet line processor and wherein the. 4. A receiving buffer memory managing unit having a link list for linking and managing each page of the receiving buffer memory, a link list of the receiving buffer memory managing unit, A packet transmission unit that transmits a packet in the reception buffer memory to an external switching device based on page information of a reception control packet, wherein the line-side reception unit refers to a link list of the reception buffer memory management unit, The packet line processing device according to claim 1, further comprising a packet receiving unit configured to store a variable-length packet in the reception buffer memory. 5. A transmission buffer memory management unit having a link list for linking and managing each page of the transmission buffer memory, and a switch list of the transmission buffer memory management unit. And a packet receiving unit that stores a fixed-length packet in the transmission buffer memory, wherein the line-side transmission unit performs the transmission based on a link list of the transmission buffer memory management unit and page information of the reception control packet. The packet line processing device according to claim 2, further comprising a packet transmission unit configured to transmit a packet in the buffer memory to the line. 6. A plurality of line-side receiving units are provided corresponding to a plurality of lines, and a multiplexing unit is provided between the line-side receiving unit and a reception buffer memory for time-division multiplexing packets from each line. 5. The method according to claim 1, wherein
The packet line processing device according to any one of the above items. 7. A demultiplexer for providing a plurality of line-side transmission units corresponding to a plurality of lines and separating a time-division multiplexed packet between the line-side transmission unit and a transmission buffer memory into each line. The packet line processing device according to claim 2, wherein a unit is provided. 8. The apparatus according to claim 1, wherein said reception buffer memory is divided into pages having the same buffer size as the data length switched by said external switching device. The packet line processing device as described in the above. 9. The transmission buffer memory according to claim 1, wherein the transmission buffer memory is divided into pages having the same buffer size as the data length switched by the external switching device. The packet line processing device as described in the above.