JP2000114480A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device, which can improve a redundancy circuit utilizing rate by reducing the occurrence rate of a defect on a group of redundant memory cells. SOLUTION: A memory cell 12 constituting a group of normal memory cells, a word line redundancy 14 constituting a group of redundant memory cells, and a bit line redundancy (16) have layers such as active areas 24, word lines 28, a bit line (34), storage nodes 38 and 102 thereon. The storage node 102, which is formed in the word line redundancy 14 and the bit line redundancy (16), has larger width 'b' than width 'a' of the storage node 38 formed in the memory cell 12, in a direction along the word line 28. Or the storage node 102 has larger width (d) than width (c) in a direction along the bit line (34) of the storage node 38.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a structure of a redundancy repair section of a semiconductor memory device in which normal memory cell groups and redundant memory cell groups are arranged in a matrix.

[0002]

2. Description of the Related Art In a semiconductor memory device such as a dynamic random access memory (hereinafter, referred to as a "DRAM"), as the capacity of a memory cell array increases, a decrease in yield due to defective memory cells becomes a problem. Therefore, conventionally, a redundant memory cell group is added to the normal memory cell group, and a memory column or memory row including a defective memory cell in the normal memory cell group is replaced with a spare memory row or memory column in the redundant memory cell group. By replacing, redundancy relief is performed and the yield is improved.

[0003]

In recent years, the number of memory cells requiring redundancy relief has been increasing in accordance with miniaturization and higher integration of elements. Accordingly, among non-defective products, the ratio of the redundant non-defective products that have been redundantly repaired is high. However, in the conventional redundant structure, the normal memory cell group and the redundant memory cell group have the same structure (design rule). Had occurred. Therefore, even if a defect of a level at which redundancy can be remedied occurs in the normal memory cell group, if a defect such as a pattern defect occurs in the corresponding redundant memory cell group, there is a problem that the redundancy cannot be remedied. Was.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the conventional semiconductor device, and has as its object to reduce the redundancy even when the elements are miniaturized and highly integrated. An object of the present invention is to provide a new and improved semiconductor device capable of suppressing an increase in a defect occurrence rate in a memory cell group and increasing a redundancy repair rate.

[0005]

According to the present invention, there is provided a semiconductor device in which a normal memory cell group and a redundant memory cell group are arranged in a matrix according to the present invention. In a semiconductor device, a design rule of a redundant memory cell group is stricter than that of a normal memory cell group. As described above, by increasing the redundancy by loosening the design rule of the redundant memory cell group, it is possible to relatively lower the defect occurrence rate in the redundant memory cell group, and as a result, the redundancy repair rate of the entire device Can be improved. In particular, if the present invention is applied to a semiconductor device having a very strict design rule, for example, a semiconductor memory of substantially quarter-micron or less, the redundancy repair ratio of the semiconductor memory can be greatly improved.

[0006] In this specification, a memory cell means at least a word line (word line), a bit line (bit line), an active memory, and the like. , Transfer gates, and memory cells in which bit line contacts are formed. The design rules are various minimum dimensions that are used as references when designing the structure of a semiconductor device. For example, the area of a storage node,
The information includes a word line pitch, a transfer gate length, a minimum active interval, a bit line contact diameter, a bit line pitch, and the like. Further, the redundancy of the design rule means that at least one of the above dimensions is relaxed.

To increase the redundancy of the design rules in order to relatively reduce the failure rate in the redundant memory cell group, an optimum method must be selected according to the actual processing steps and required specifications. can do.
For example, as described in claim 2, the redundancy is increased with respect to the area of the storage node, as described in claim 3, the redundancy is increased with respect to the word line pitch, or described in claim 4. The redundancy may be increased with respect to the transfer gate length as described in (5), or as described in claim 5, the redundancy may be increased with respect to the minimum active interval, or as described in claim 6,
Increased redundancy with regard to bit line contact diameter,
Alternatively, as described in claim 7, the redundancy is increased with respect to the bit line pitch, or as described in claim 8, the redundancy is increased with respect to the cell size. Redundancy can be increased by any combination.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description is omitted.

First Embodiment (1) Configuration of Conventional Memory Cell Unit First, before describing a memory unit 100 of a DRAM according to a first embodiment, referring to FIGS. , The memory unit 10 of the conventional DRAM compared with the memory unit 100
Will be described. FIG. 1 is a schematic plan view showing a conventional memory unit 10, and FIG. 2 is a schematic cross-sectional view showing the memory unit 10 cut along a plane along the line AA shown in FIG. is there. FIG. 3 is a schematic cross-sectional view showing the memory unit 10 taken along a plane along the line BB shown in FIG. 1, and FIG. 4 is a sectional view taken along a plane along the line CC shown in FIG. 1 is a schematic cross-sectional view illustrating a memory unit 10 according to an embodiment. FIG. 5 is a schematic plan view showing an active region (n ⁺ diffusion layer) 24 constituting the memory unit 10 shown in FIG. 1. FIG. 6 is a plan view showing a word constituting the memory unit 10 shown in FIG. FIG. 2 is a schematic plan view showing a line 28. FIG. 7 shows the memory unit 10 shown in FIG.
FIG. 8 is a schematic plan view showing a bit line 34 constituting the memory unit 10, and FIG. 8 is a schematic plan view showing a storage node 38 constituting the memory unit 10 shown in FIG.

As shown in FIG. 1, a conventional memory unit 10 includes a memory cell unit 12 forming a normal memory cell group arranged in a matrix and a word line forming a redundant memory cell group (redundant relief unit). It comprises a redundant section 14, a bit line redundant section 16, and a peripheral circuit section 18. Further, each element described later formed in the memory cell section 12, the word line redundant section 14, and the bit line redundant section 16 is formed by substantially the same design rule. That is, as shown in FIGS. 2 to 4, both the memory cell section 12, the word line redundant section 14 and the bit line redundant section 16 are oxidized at predetermined intervals on the p-type silicon substrate 20 of the memory section 10, for example. A field oxide film 22 such as a silicon film is formed, and each memory cell is separated by each field oxide film 22.

As shown in FIG. 1 and FIG. 5, an active region 24 doped with phosphorus or arsenic is formed on the silicon substrate 20 which is not covered with each field oxide film 22, for example. ing. Further, on the field oxide film 22 and the active region 24, as shown in FIGS. 1 to 3 and FIG. Consisting of doped polycrystalline silicon,
A word line 28 serving as a transfer gate is formed, and thereby a transistor is formed.

As shown in FIGS. 2 to 4, the field oxide film 22, the active region 24 and the word lines 28 are covered with an interlayer insulating film 30 made of, for example, silicon oxide formed by a CVD method. As shown in FIGS. 1, 3, 4, and 7, a bit line contact 32 communicating with the active region 24 is formed on the interlayer insulating film 30 by, for example, an etching method. Further, in the bit line contact 32,
For example, a part of the bit line 34 formed of N-type polysilicon by the CVD method and disposed on the interlayer insulating film 30 is formed. The bit lines 34 and the word lines 28 are arranged so as to be substantially orthogonal to each other.

As shown in FIGS. 1, 2 and 8, a cell line contact 36 communicating with the active region 24 is formed in the interlayer insulating film 30 by, for example, an etching method. Furthermore, this cell line contact 3
As shown in FIG.
A storage node 38 made of N-type polysilicon is formed by the VD method. As shown in FIG. 2, a cell plate made of, for example, N-type polysilicon is formed on the storage node 38 via a capacitor insulating film 40 made of a dielectric material such as silicon oxide formed by a CVD method. An electrode 42 is formed, which forms a capacitor.

(2) Configuration of Memory Cell Unit of this Embodiment Next, the configuration of the memory cell unit 100 of this embodiment will be described with reference to FIGS. In addition,
FIG. 9 is a schematic plan view showing the memory unit 100 of the present embodiment. FIG. 10 shows the memory unit 1 shown in FIG.
FIG. 10 is a schematic explanatory diagram for explaining the operation of FIG.
FIG. 10A is a schematic sectional view showing the conventional memory unit 10 shown in FIG. 2, and FIG. 10B is a DD line (corresponding to the line AA in FIG. 1) shown in FIG. FIG. 1 is a schematic cross-sectional view illustrating the memory unit 100 of the present embodiment cut along a plane along).

As shown in FIGS. 9 and 10B, the storage nodes 102 formed in the word line redundant portion 14 and the bit line redundant portion 16 of the memory portion 100
The word line redundant portion 14 and the bit line redundant portion 16 of the memory portion 10 shown in FIG.
0 (b), the memory cell unit 1 of the memory units 10 and 100
2 has a relatively larger storage node area than the storage node 38 formed. That is, in the example shown in FIG. 9, the storage node 102 according to the present embodiment has a width (b) that is relatively larger than the width (a) of the storage node 38 in the word line 28 direction.
Or expanded to a width (d) that is relatively larger than the width (c) of the storage node 38 in the direction of the bit line 34. The other configuration of the memory unit 100 is substantially the same as the memory unit 10 described above.

The present embodiment is configured as described above, and includes a word line redundant unit 14 and a bit line redundant unit 1.
6 is relatively larger than the total area of the storage nodes 102 arranged in the memory cell section 12 and the conventional word line redundant section 14 and the conventional bit line redundant section 16. , The capacitance of the storage node 102 (redundant portion) can be increased. As a result, it is possible to reduce the jump failure due to the hold time failure, and it is possible to improve the redundancy repair ratio.

(Second Embodiment) Next, the configuration of a memory section 200 of a DRAM according to a second embodiment will be described in detail with reference to FIGS. FIG. 11 is a schematic plan view showing the memory unit 200 of the present embodiment. FIG. 12 is a schematic explanatory diagram for explaining the memory unit 200 shown in FIG.
FIG. 12A is a schematic sectional view showing the conventional memory unit 10 shown in FIG. 2, and FIG. 12B is a sectional view taken along line EE (line AA in FIG. 1) shown in FIG. FIG. 7 is a schematic cross-sectional view illustrating the memory unit 200 according to the present embodiment, which is cut along a plane along (a).

As shown in FIGS. 11 and 12 (b),
Each word line 202 formed in the word line redundant section 14 and the bit line redundant section 16 of the memory section 200
FIG. 12B shows the word line redundant portion 14 and the bit line redundant portion 16 of the memory unit 10 shown in FIG. 12A by increasing the cell size of the redundant units 14 and 16 relatively. The pitch (interval) of each word line 28 formed in the memory cell unit 12 of the memory units 10 and 100 shown in FIG. That is, in the example shown in FIGS. 11 and 12, the pitch (e) of each word line 202 according to the present embodiment is
Are expanded in the direction of the word lines 28 and 202 beyond the conventional pitch (f) of each word line 28. In addition,
Other configurations of the memory unit 200 are the same as those of the memory unit 1 described above.
0.

The present embodiment is configured as described above, and includes a word line redundant unit 14 and a bit line redundant unit 1.
6 is relatively larger than the pitch of each word line 28 disposed in the memory cell unit 12 and the conventional word line redundant unit 14 and the conventional bit line redundant unit 16. , Each redundant part 14, 16
Between the word lines 202 at each point (short path),
Short circuit between each cell line contact 36 and each word line 202 and short circuit between each bit line contact 32 and each word line 202 can be suppressed. As a result, it is possible to reduce the jump defect,
The redundancy rescue rate can be improved.

(Third Embodiment) Next, the configuration of a memory section 300 of a DRAM according to a third embodiment will be described in detail with reference to FIGS. FIG. 13 is a schematic plan view showing the memory unit 300 of the present embodiment. FIG. 14 is a schematic explanatory diagram for explaining the memory unit 300 shown in FIG.
FIG. 14A is a schematic sectional view showing the conventional memory unit 10 shown in FIG. 2, and FIG. 14B is a sectional view taken along line FF (line AA in FIG. 1) shown in FIG. FIG. 4 is a schematic cross-sectional view illustrating the memory unit 300 according to the present embodiment, which is cut along a plane along (a).

As shown in FIGS. 13 and 14B,
Each word line 302 formed in the word line redundant section 14 and the bit line redundant section 16 of the memory section 300
Are the word lines 202 of the second embodiment described above.
Similarly, the cell sizes of the redundant sections 14 and 16 are relatively widened, so that the word line redundant section 14 and the bit line redundant section 16 of the memory section 10 shown in FIG.
Each word line 28 formed in the memory cell section 12 of the memory sections 10 and 300 shown in FIG.
The pitch (f) is set to be relatively larger than the pitch (e).

Each of the word lines 302 according to the present embodiment is, as shown in FIGS.
The word line redundant portion 14 and the bit line redundant portion 16 of the conventional memory portion 10 shown in FIG. 14A and the memory cell portion 12 of the memory portions 10 and 100 shown in FIG. The width (h) is set to be relatively larger than the width (transfer gate length) (g) of each of the word lines 28.
It is enlarged in the 302 direction. The other configuration of the memory unit 300 is substantially the same as the memory unit 10 described above.

The present embodiment is configured as described above, and comprises a word line redundant unit 14 and a bit line redundant unit 1.
6, the pitch and the transfer gate length of each word line 28 arranged in the memory cell unit 12 and the conventional word line redundant unit 14 and the conventional bit line redundant unit 16 are determined. , Each of the redundant parts 14, 16
Off leak of the current of the transistor constituting each memory cell can be reduced. As a result, the jump failure can be reduced, and the redundancy remedy rate can be improved.

(Fourth Embodiment) Next, the configuration of a memory section 400 of a DRAM according to a fourth embodiment will be described in detail with reference to FIGS. FIG. 15 is a schematic plan view showing the memory unit 400 according to the present embodiment. FIG. 16 is a schematic plan view showing an active area 402 included in the memory unit 400 shown in FIG.

As shown in FIGS. 15 and 16 (b),
The cell sizes of the word line redundant section 14 and the bit line redundant section 16 of the memory section 400 are the same as those of the word line redundant section 14 and the bit line redundant section 16 of the memory section 10 shown in FIG. Memory unit 1 shown in (b)
The cell size of each of the memory cell sections 12 of 0 and 100 is set relatively larger. Therefore, as shown in FIGS. 15 and 16 (b), each active area 402 formed in the word line redundant section 14 and the bit line redundant section 16 of the memory section 400 corresponds to the memory section shown in FIG. 16 (a). Ten word line redundant portions 14 and bit line redundant portions 16 and the memory portion 1 shown in FIG.
Each of the active regions 24 formed in the 0,400 memory cell unit 12 is formed to have a relatively smaller minimum active interval (j) than the minimum active interval (i). The other configuration of the memory unit 400 is substantially the same as the memory unit 10 described above.

The present embodiment is configured as described above, and includes the word line redundant unit 14 and the bit line redundant unit 1.
6, the word line redundant section 14 and the bit line redundant section 16 of the memory section 10 shown in FIG.
Since the memory cells 10 and 400 shown in FIG. 16 and FIG. 16B are relatively wider than the memory cells 12 and the minimum active interval of the active area 402 is expanded, the distance between the cells in each of the redundant sections 14 and 16 is increased. Current leakage can be reduced. As a result, the jump failure can be reduced, and the redundancy remedy rate can be improved.

(Fifth Embodiment) Next, the configuration of a memory section 500 of a DRAM according to a fifth embodiment will be described in detail with reference to FIGS. FIG. 17 is a schematic plan view showing the memory section 500 of the present embodiment. FIG. 18 is a schematic explanatory diagram for explaining the memory unit 500 shown in FIG.
FIG. 18A is a schematic cross-sectional view showing the conventional memory unit 10 shown in FIG. 3, and FIG. 18B is a GG line (BB line in FIG. 1) shown in FIG. FIG. 5 is a schematic cross-sectional view illustrating the memory unit 500 according to the present embodiment, which is cut along a plane along (a).

As shown in FIGS. 17 and 18 (b),
The bit line contacts 502 formed in the word line redundant section 14 and the bit line redundant section 16 of the memory section 500 correspond to the word line redundant section 14 and the bit line redundant section 16 of the memory section 10 shown in FIG. , And the inner diameter of each bit line contact 32 formed in the memory cell section 12 of the memory section 10 or 500 shown in FIG. 18B is relatively larger. That is, in the example shown in FIGS. 17 and 18B, each bit line contact 5 according to the present embodiment is
02 is the direction of the word line 28 and the bit line 34
The inner diameter (k) of each bit line contact 32 shown in FIG. 17 and FIG.
It has a relatively large inner diameter (l). The other configuration of the memory unit 500 is substantially the same as the memory unit 10 described above.

The present embodiment is configured as described above, and includes the word line redundant unit 14 and the bit line redundant unit 1.
6, the inner diameter of each bit line contact 502 is determined by the memory cell unit 12 or the conventional word line redundant unit 1
4 and the inner diameter of each bit line contact 32 arranged in the bit line redundant portion 16 is relatively larger than that of the bit line contact 502. As a result, the jump failure can be reduced, and the redundancy remedy rate can be improved.

(Sixth Embodiment) Next, referring to FIGS. 19 and 20B, the DR of the sixth embodiment will be described.
The configuration of the memory unit 600 of the AM will be described in detail. FIG. 19 is a schematic plan view showing the memory unit 600 according to the present embodiment. FIG. 20 is a schematic explanatory diagram for explaining the memory unit 600 shown in FIG. 19, and FIG. 20A shows the conventional memory unit 10 shown in FIG.
FIG. 20B is a schematic cross-sectional view showing FIG.
FIG. 2 is a schematic cross-sectional view showing the memory unit 600 of the present embodiment, taken along a plane along the line HH (corresponding to the line CC in FIG. 1) shown in FIG.

As shown in FIGS. 19 and 20, each bit line 602 formed in the word line redundant section 14 and the bit line redundant section 16 of the memory section 600 is
0 (a), the word line redundant section 14 of the memory section 10
20 and FIG. 20 (b)
Are set relatively larger than the bit line pitch between the bit lines 34 formed in the memory cell unit 12 of the memory units 10 and 600 shown in FIG. That is, in the example shown in FIGS. 19 and 20B, each bit line 602 according to the present embodiment is
4, 602, and has a pitch (n) that is relatively larger than the bit line pitch (m) of each bit line 34 shown in FIG. In addition,
Other configurations of the memory unit 600 are the same as those of the memory unit 1 described above.
0.

The present embodiment is configured as described above, and includes the word line redundant unit 14 and the bit line redundant unit 1.
6 is smaller than the bit line pitch between the bit lines 34 arranged in the memory cell unit 12 and the conventional word line redundant unit 14 and the conventional bit line redundant unit 16 arranged in the bit line redundant unit 16. Since the bit lines are relatively large, it is possible to suppress the occurrence of the bit line short-circuit in the redundant portions 14 and 16 and to reduce the opening failure of each bit line contact 32. As a result, the jump failure can be reduced, and the redundancy remedy rate can be improved.

(Seventh Embodiment) Next, referring to FIG. 21, a memory 70 of a DRAM according to a seventh embodiment will be described.
0 will be described in detail. FIG. 21 is a schematic explanatory diagram showing the memory unit 700 of the present embodiment.

As shown in FIG. 21, each redundant memory cell 702 formed in the word line redundant section 14 and the bit line redundant section 16 of the memory section 700 is
2 is set to be relatively larger than the size of each normal memory cell 704 formed. That is, in the illustrated example, each redundant memory cell 702 is connected to the word line 28.
Direction and the direction of the bit line 34, and are larger than the cell size (o, p) of each normal memory cell 704.
The relatively large redundant cell size (q, r) is set. The other configuration of the memory unit 700 is substantially the same as the memory unit 10 described above.

The present embodiment is configured as described above. Since the cell size of each redundant memory cell 702 is relatively larger than the cell size of each normal memory cell 704, each of these redundant memory cells 702 is 702 can be improved, and the redundancy remedy rate can be improved.

Although the preferred embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to such configurations. In the scope of the technical idea described in the claims, those skilled in the art
Various changes and modifications can be conceived, and it is understood that these changes and modifications also belong to the technical scope of the present invention.

For example, in the above embodiment, the area of the storage node of each redundant memory cell group, the word line pitch, the transfer gate length, the minimum active interval, the bit line contact diameter, and the bit Although the configuration in which the line pitch and the expansion of the cell size are individually and independently applied to the memory unit has been described as an example, the present invention is not limited to such a configuration, and these configurations may be arbitrarily arbitrarily determined. The present invention can be implemented even when applied to a semiconductor device in combination.

Further, in the above-described embodiment, the configuration in which the minimum active interval of the redundant memory cell group is extended has been described as an example. However, the present invention is not limited to this configuration. The present invention can also be applied to a configuration in which the maximum active interval is widened independently or independently.

Further, in the above-described embodiment, a configuration in which each of the above-described configurations is applied to a memory portion of a DRAM has been described as an example. However, the present invention is not limited to such a configuration. For example, an EPROM (Erasable and Programmable R
ead Only Memory), storage nodes,
Even if transfer gates and bit line contacts are not formed, the present invention can be applied to any semiconductor device as long as the normal cell group and the redundant cell group are arranged in a matrix.

[0040]

According to the present invention, since the design rule of the redundant memory cell group is relaxed compared to the design rule of the normal memory cell group, the defect occurrence rate of the redundant memory cell group is reduced, and the yield is improved. Can be. as a result,
It is possible to improve the redundancy repair ratio for the normal memory cell group in which a defect has occurred.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a conventional memory unit.

FIG. 2 is a schematic cross-sectional view illustrating a memory unit cut along a plane along line AA shown in FIG.

FIG. 3 is a schematic cross-sectional view showing a memory unit cut along a plane along line BB shown in FIG. 1;

FIG. 4 is a schematic cross-sectional view illustrating a memory unit cut along a plane along line CC shown in FIG. 1;

FIG. 5 is a schematic plan view illustrating an active area included in the memory unit illustrated in FIG.

FIG. 6 is a schematic plan view illustrating a word line included in the memory unit illustrated in FIG. 1;

FIG. 7 is a schematic plan view illustrating a bit line included in the memory unit illustrated in FIG.

FIG. 8 is a schematic plan view illustrating a storage node included in the memory unit illustrated in FIG.

FIG. 9 is a schematic plan view showing a memory unit according to the first embodiment of the present invention.

FIG. 10 is a schematic explanatory diagram for explaining a memory unit shown in FIG. 9;

FIG. 11 is a schematic plan view showing a memory unit according to a second embodiment of the present invention.

FIG. 12 is a schematic explanatory diagram for explaining a memory unit shown in FIG. 11;

FIG. 13 is a schematic plan view showing a memory unit according to a third embodiment of the present invention.

FIG. 14 is a schematic explanatory diagram for explaining a memory unit shown in FIG. 13;

FIG. 15 is a schematic plan view showing a memory unit according to a fourth embodiment of the present invention.

16 is a schematic plan view illustrating an active area included in the memory unit shown in FIG.

FIG. 17 is a schematic plan view showing a memory unit according to a fifth embodiment of the present invention.

18 is a schematic explanatory diagram for describing a memory unit shown in FIG.

FIG. 19 is a schematic plan view showing a memory unit according to a sixth embodiment of the present invention.

FIG. 20 is a schematic explanatory diagram for describing a memory unit shown in FIG. 19;

FIG. 21 is a schematic explanatory view showing a memory unit according to a seventh embodiment of the present invention.

[Explanation of symbols]

10, 100, 200, 300, 400, 500, 60
0,700 memory unit 12 memory cell unit 14 word line redundant unit 16 bit line redundant unit 24,402 active area 28,202,302 word line 32,502 bit line contact 34,602 bit line 38,102 storage node 702 redundant memory Cell 704 Normal memory cell

Claims (8)

[Claims] 1. A semiconductor device in which a normal memory cell group and a redundant memory cell group are arranged in a matrix, wherein a design rule of the redundant memory cell group is less strict than that of the normal memory cell group. Semiconductor device. 2. A storage node is formed in each of the redundant memory cell groups;
2. The semiconductor device according to claim 1, wherein the area is larger than an area of a storage node of each normal memory cell group. 3. The semiconductor device according to claim 1, wherein a word line pitch of each of said redundant memory cell groups is wider than a word line pitch of each of said normal memory cell groups. 4. A transfer gate is formed in each of the redundant memory cell groups;
4. The semiconductor device according to claim 1, wherein said semiconductor memory device is wider than a transfer gate length of each normal memory cell group. 5. The device according to claim 1, wherein a minimum active interval of each of the redundant memory cell groups is wider than a minimum active interval of each of the normal memory cell groups. Semiconductor device. 6. A bit line contact is formed in each of the redundant memory cell groups; the bit line contact diameter is wider than the bit line contact diameter of each of the normal memory cell groups. 1,2,
6. The semiconductor device according to any one of 3, 4, and 5. 7. The semiconductor memory device according to claim 1, wherein a bit line pitch of each of said redundant memory cell groups is wider than a bit line pitch of each of said normal memory cell groups.
7. The semiconductor device according to any one of 4, 5, and 6. 8. The cell size of each of the redundant memory cell groups is:
8. The semiconductor device according to claim 1, wherein a cell size of each of the normal memory cell groups is larger than that of each of the normal memory cell groups.