JP2000114377A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain stable operation even after an anti-fuse is used by forming a hollow part which a passivation film does not enter inside a gap of an antifuse covered with a passivation film. SOLUTION: A first layer insulation film 16, a second layer insulation film 20 and a third layer insulation film 24 are deposited one by one all over a silicon board 11 and flattened. An aluminum wiring layer is deposited on the third layer insulation film 24, the aluminum wiring layer is subjected to patterning, and anti-fuse wirings 26a, 26b with a specified gap 26G are formed in an aluminum wiring layer. The entirety of such an aluminum wiring layer is covered by depositing a passivation film such as a silicon nitride film. In the process, deposited silicon nitride forms a hollow part which a passivation film does not enter in a space inside a clearance of the gap G. As a result, an anti-fuse can be connected effectively and yield can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having an antifuse.

[0002]

2. Description of the Related Art As the density and capacity of semiconductor memories have increased, it has become impossible to require that the entire chip be defect-free. Even if defective cells are included, they must be formed in advance. To repair with a spare cell of a redundancy circuit, a memory LSI and an LS with a memory
I is widely used. To use a spare cell in place of a defective cell, a tester usually memorizes the address of the defective cell, then cuts a fuse formed of a wiring layer such as polysilicon or aluminum with a laser, and replaces the defective cell with a spare cell. There is a technique for configuring so that is selected.

[0003]

However, since cutting a fuse by a laser requires a certain amount of energy, a wiring or a semiconductor element is disposed below a wiring layer on which the fuse is formed. If they are formed, they will cause serious damage. This is one of the reasons that the degree of integration of the LSI cannot be further improved.

Generally, if the uppermost aluminum wiring can be used as a wiring layer serving as a fuse, laser irradiation can be performed directly, which is convenient in the process. However, the uppermost aluminum wiring is 1 μm or more in order to reduce resistance. It is a thick film, which is much thicker than the thickness of other wiring layers of 0.6 μm or less. For this reason, if the uppermost aluminum wiring is used for the fuse, a laser with a large energy must be used for cutting the fuse, and it is inevitable that a wiring or an element cannot be formed below the fuse. Was.

Therefore, instead of cutting a metal layer made of aluminum or the like with a laser, a technique has been proposed in which a redundant circuit is operated using an anti-fuse that connects a metal layer on both sides of a gap formed in advance in a wiring layer with a laser. Have been. The use of this anti-fuse allows connection with much lower energy than cutting the fuse, which is advantageous in forming wirings and elements below the fuse.

However, when the antifuse is formed in the uppermost layer, the connection portion by the laser is exposed, so that the stability is low mechanically and chemically, and the operation of the subsequent circuit may be unstable. . Therefore, the present invention
It is an object of the present invention to provide a semiconductor device capable of performing a stable operation even after using an antifuse.

[0007]

A semiconductor device according to the present invention includes an anti-fuse formed on a semiconductor substrate by a metal wiring layer having a gap, the anti-fuse being covered with a passivation film, and the inside of the gap of the anti-fuse is formed. Is characterized in that a hollow portion into which the passivation film does not enter is formed.
With the above configuration, the gap can be connected by irradiating the laser through the passivation film, so that the operation after the connection of the antifuse is stabilized.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1 to 5 are views showing a manufacturing process of a first embodiment in which the present invention is applied to a three-layer metal wiring LSI.

First, in FIG. 1, a plurality of device isolation regions 12a and 12b are formed on a silicon substrate 11, and the device formation regions separated by the device isolation regions 12a and 12b are provided with a passive device formed of a diffusion layer 13 or a diffusion device. An active element such as MOSFET 14 composed of layers 14a and 14b and gate electrode 14c or MOSFET 15 composed of diffusion layers 15a and 15b and gate electrode 15c is formed.

Next, as shown in FIG. 2, a first interlayer insulating film 16 such as a BPSG film is deposited on the entire surface of the silicon substrate 11,
The first interlayer insulating film 16 is planarized by using a normal CMP method. Next, the respective diffusion layers 13, 14a, 14b,
A first contact hole 17 is formed through the first interlayer insulating film 16 by using photolithography for the layers 15a and 15b. These first contact holes 17
Is filled with a first tungsten 18 using a CVD method. The respective tips of the first tungsten 18 are connected to the diffusion layers 13, 14a, 14b, 15a, 15b.

Thereafter, an aluminum layer is deposited on the entire surface of the first interlayer insulating film 16, and a first aluminum wiring layer 19 having a predetermined shape is formed by patterning using photolithography.

Next, in FIG. 3, a second interlayer insulating film 20 such as a SiO ₂ film is deposited on the first aluminum wiring layer 19, and the second interlayer insulating film 20 is planarized by using the CMP method. Thereafter, a second contact hole 21 for making a connection with the first aluminum wiring layer 19 is opened at a predetermined position in the second interlayer insulating film 20, and the second contact hole 21 is formed by a CVD method. The second tungsten 22 is embedded.

Further, an aluminum layer is deposited on the entire surface of the second interlayer insulating film 20 and patterned by photolithography as a second aluminum wiring layer 23 having a predetermined shape.

Next, as shown in FIG. 4, a third interlayer insulating film 24 such as an SiO ₂ film is deposited on the second aluminum wiring layer 23, and the third interlayer insulating film 24 is flattened by using the CMP method. Become Thereafter, a third contact hole for making a connection with the second aluminum wiring layer 23 is opened at a predetermined location in the third interlayer insulating film 24, and a third contact hole is formed in the third contact hole.
The third tungsten 25 is embedded using the VD method.

Further, an aluminum layer is deposited on the entire surface of the third interlayer insulating film 24, and is patterned as a third aluminum wiring layer 26 having a predetermined shape by photolithography. The third aluminum wiring layer 26 includes anti-fuse wirings 26a and 26b having a predetermined gap 26G. The width G of the gap 26G of the antifuse is set to, for example, 1 micron or less.

Finally, the entire third aluminum wiring layer 26 is covered by depositing a passivation film 27 such as a silicon nitride film (Si ₃ N ₄ ). At this time, since the gap G of the gap 26G of the antifuse is formed to have a dimension of only 1 micron or less, the deposited silicon nitride does not enter so as to completely fill the space in the gap G of the gap 26G. A hollow portion remains inside.

In this embodiment, in order to prevent the passivation film 27 from entering the gap 26G at the time of deposition, the thickness T of the anti-fuse wires 26a and 26b of the third aluminum wiring layer 26 is set to 1 μm and the gap T is set to 1 μm. Although the width of 26G is set to 1 micron, generally, the ratio between the height and the width of the gap 26G, that is, the aspect ratio is 1 μm.
With the above settings, good results can be obtained.

The passivation film 27 is etched using a photolithography method to form a partial opening of the third aluminum wiring layer 26 to form a pad 26P.

As described above, the anti-fuse wirings 26a and 26a are formed on the third aluminum wiring layer 26 which is the uppermost layer of the multilayer wiring structure.
6b to form an antifuse with a gap G formed between
With the configuration in which the hollow portion is left inside the gap 26G by covering with the passivation film 27, the passivation film 27 is interposed near the gap 26G to use the redundancy circuit connected to the anti-fuse wirings 26a and 26b. When the laser beam is irradiated from the outside, the opposing portions of the anti-fuse wirings 26a and 26b are melted by receiving the energy of the laser beam, and are connected to each other in the hollow portion inside the gap 26G. Since the passivation film 27 transmits the laser well, the laser energy is efficiently used for the connection of the anti-fuse, and since the connection portion is covered with the passivation film 27 even after the connection of the anti-fuse, the reliability is improved. high.

At this time, most of the energy of the irradiated laser beam is absorbed by the opposed portions of the anti-fuse wirings 26a and 26b and is used for melting these portions. The laser beam slightly reaching the third and second interlayer insulating films 24 and 2
It is absorbed by 0 and does not reach the lowermost MOSFET 14.

When the opposed portions of the anti-fuse wires 26a and 26b are melted in the hollow portion inside the gap 26G and connected to each other by receiving the energy of the laser beam, the temperature of the aluminum used becomes high. Therefore, the surface is thermally oxidized to become chemically and mechanically stable alumina, and there is no fear of causing corrosion.

In this embodiment, the anti-fuse wiring 2 is formed on the third aluminum wiring layer 26 which is the uppermost layer of the multilayer wiring structure.
An antifuse having a gap G formed between 6a and 26b was formed. In addition to aluminum, any one of silicon, cobalt, tungsten, carbon, tantalum, titanium, copper, nickel, molybdenum and ruthenium or a combination thereof was used. If a metal wiring is formed by using the method described above, and an anti-fuse is formed at the time of forming the metal wiring, it can be similarly used as a good anti-fuse, and the number of steps does not increase.

FIG. 6 is a cross-sectional view showing the final stage of the manufacturing process of another embodiment in which the present invention is applied to a three-layer metal wiring LSI. The difference from the embodiment shown in FIG. It is only that the dummy pattern DP made of metal is formed immediately below the gap 26G. Therefore, in the configuration of FIG. 6, the steps of sequentially forming the first interlayer insulating film 16, the first aluminum wiring layer 19, and the second interlayer insulating film 20 on the semiconductor substrate 11 are the same as those shown in FIGS. Exactly the same.

Further, an aluminum layer is deposited on the entire surface of the second interlayer insulating film 20 and patterned by photolithography as a second aluminum wiring layer 23 having a predetermined shape. The dummy pattern DP is formed at the position directly above. Since the formation of the dummy pattern DP is formed at the same time as the patterning of the second aluminum wiring layer 23, the number of steps does not increase during manufacturing. This dummy pattern DP is not connected to any circuit element, while the other aluminum wiring layer 23 is connected to the first aluminum wiring layer 19 via the tungsten contact 22, and is electrically floating. , But may be connected to the ground potential, for example.

After the patterning of the second aluminum wiring layer 23 including the dummy pattern DP is completed, a third interlayer insulating film 24 such as a SiO ₂ film is formed on the second aluminum wiring layer 23 as in the process shown in FIG. On the third layer using a CMP method.
The interlayer insulating film 24 is flattened. Thereafter, a third contact hole for making a connection with the second aluminum wiring layer 23 is opened in a predetermined location in the third interlayer insulating film 24 except for the dummy pattern DP, and the third contact hole is formed by CVD.
The third tungsten 25 is embedded by using the method. Further, an aluminum layer is deposited on the entire surface of the third interlayer insulating film 24, and is patterned as a third aluminum wiring layer 26 having a predetermined shape by using a photolithography method. This third
The aluminum wiring layer 26 includes anti-fuse wirings 26a and 26b having a predetermined gap 26G.

Finally, the entire third aluminum wiring layer 26 is covered by depositing a passivation film 27 such as a silicon nitride film (Si ₃ N ₄ ), and is patterned by etching to form a pad 26P. Thus, the three-layer metal interconnection LSI shown in FIG. 6 is formed.

In the structure shown in FIG. 6, when a laser beam is applied to the gap 26G from the outside via the passivation film 27 in order to use the redundancy circuit connected to the anti-fuse wirings 26a and 26b, the laser beam Of the antifuse wirings 26a and 26b is melted by the energy of
Are connected to each other in a hollow portion inside the.

Also in this case, since the passivation film 27 transmits the laser well, the laser energy is efficiently used for the connection of the antifuse, and the connection portion is covered with the passivation film 27 even after the connection of the antifuse. High reliability. Most of the energy of the irradiated laser beam is
a and 26b are absorbed by the opposing portions and are used for melting these portions. The laser beam that does not reach the lower layer much, but slightly reaches the third interlayer insulating film 2.
4 is surely absorbed by the dummy pattern DP formed in the lower layer, and does not reach the MOSFET 14 below it.

FIG. 7A is a top view of the antifuse portion shown in FIG.
A gap 26G is formed between the opposing end faces of 6a and 26b with a gap G interposed therebetween. The length of the I-shaped gap 26G is the same as the width of the antifuse wirings 26a and 26b. . Therefore, the spot diameter SP of the laser beam for melting the end portion is set to be approximately the same as the width of the antifuse wirings 26a and 26b, for example, as shown in the figure, so that the antifuse is connected efficiently. be able to.

FIG. 7B is a view of the antifuse and the dummy pattern DP shown in FIG. 6 as viewed from above.
In this case, a gap 26G is formed between opposing end faces of the anti-fuse wirings 26a and 26b with a gap G interposed therebetween. The opposing portions of the anti-fuse wirings 26a and 26b through the gap 26G are T-shaped. The length of the gap 26G is, for example, the length of the anti-fuse wiring 26a,
It is about twice the width of 26b. Therefore, the spot diameter SP of the laser beam for melting this end portion
7A is the same as the case of FIG. 7A, the melting and connection are performed in portions wider than the widths of the anti-fuse wirings 26a and 26b, so that the anti-fuse connection can be performed more efficiently, and the yield can be improved. Is improved.

In addition, even when the tip shape of the antifuse is a combination of a convex shape and a concave shape, a combination of a comb shape and a comb shape, or a combination of an L shape and an inverted L shape, the efficiency of melting and connection is similarly improved. It is expected that the yield will be improved.

[0032]

As described in detail above, according to the present invention,
Since the antifuse is covered with the passivation film so that a hollow portion remains in the gap of the antifuse, a semiconductor device capable of performing a stable operation even after using the antifuse can be provided.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a three-layer metal wiring LSI on a silicon substrate according to an embodiment of the present invention.

FIG. 2 is a process chart of forming a first interlayer insulating film and a first aluminum layer following FIG. 1;

FIG. 3 is a process chart of forming a second interlayer insulating film and a second aluminum layer following FIG. 2;

FIG. 4 is a process chart of forming a third aluminum layer including a third interlayer insulating film and an antifuse following FIG. 3;

FIG. 5 is a view showing a step of coating the passivation film following FIG. 4;

FIG. 6 is a sectional view showing a final manufacturing process of a three-layer metal wiring LSI according to another embodiment of the present invention;

FIG. 7 is a plan view showing a shape of a gap portion of the antifuse used in the embodiment of FIGS. 5 and 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Silicon substrate 14 ... MOSFET 24 ... 3rd interlayer insulating film 26a, 26b ... Anti-fuse wiring 26G ... Gap 27 ... Passivation film

Claims (7)

[Claims] An antifuse formed of a metal wiring layer having a gap on a semiconductor substrate is covered with a passivation film, and a hollow portion in which the passivation film does not enter is formed in the gap of the antifuse. A semiconductor device characterized by being formed. 2. The anti-fuse according to claim 1, wherein the anti-fuse is made of any one of aluminum, silicon, cobalt, tungsten, carbon, tantalum, titanium, copper, nickel, molybdenum and ruthenium, or a combination thereof. 13. The semiconductor device according to claim 1. 3. A lower metal wiring layer including a dummy wiring pattern formed immediately below the anti-fuse is formed below the metal wiring layer on which the anti-fuse is formed. 2. The semiconductor device according to 1. 4. The semiconductor device according to claim 3, wherein a wiring or a semiconductor element is formed further below the dummy wiring pattern. 5. The antifuse according to claim 1, wherein a metal oxide film is formed on a surface of said antifuse.
The semiconductor device according to any one of the above items. 6. The semiconductor device according to claim 1, wherein a gap of said anti-fuse is 1 μm or less. 7. The semiconductor device according to claim 1, wherein an aspect ratio of a gap of the antifuse is 1 or more.