JP2000113668A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device whose refresh current consumption can be reduced even if a cache selects either a writing- through method or a writing-back method as its writing operation method. SOLUTION: A central processing unit(CPU) 2 containing a primary cache and a secondary cache 3 are provided on a consolidated memory microcomputer chip 1. A secondary cache control circuit 4, a secondary cache tag memory 5 and a secondary cache data memory 6 are provided in the secondary cache 3. It is to be noted that the secondary cache tag memory 5 and a secondary cache data memory 6 are composed of DRAM's.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device provided with a cache, and more particularly, to a semiconductor integrated circuit device with reduced power consumption.

[0002]

2. Description of the Related Art In recent years, a number of memory-embedded microcomputer chips have been proposed in which a dynamic random access memory (DRAM) is mounted inside a chip and used as a secondary cache memory. Advantages of using a DRAM as a cache memory instead of a conventionally used static random access memory (SRAM) include a small area and a small power consumption when compared with the same capacity. On the other hand, one of the problems when configuring the cache memory with a DRAM is that the DRAM inherently requires a refresh operation unlike the SRAM.

[0005] Hereinafter, five conventional examples will be described in terms of a processing method of a refresh operation.

A first conventional example is disclosed in Japanese Patent Laid-Open No. 6-314240.
This is a cache memory described in Japanese Patent Application Laid-Open Publication No. H10-26095. FIG. 19 is a block diagram showing a conventional cache memory described in JP-A-6-314240.

The cache memory described in this publication includes a data memory 107 for copying and storing data of a main memory in block units, and a tag memory 1 for storing an address of the main memory corresponding to the stored block.
05 and a V-bit memory 104 for outputting validity / invalidity of data stored in the data memory 107 are provided.
The 5-bit and V-bit memory 104 is constituted by a DRAM.

In the first conventional example, when the V bit is "1", the validity is set, and when the V bit is "0", the invalidity is set. By setting shorter than that of the memory 105, the contents of the cache memory are invalidated before the information is lost.

As a result, the refresh operation of the DRAM is omitted. Although the cache memory in which the refresh operation is omitted has a difference in circuit configuration, for example, Japanese Patent Application Laid-Open No. HEI 9-198313 and the document "Dynami
c RAM for On-chip Instruction Caches (Computer Arc
hitecture News Vol. 16, No. 4, Sept. 1988) ".

A second conventional example is disclosed in Japanese Patent Laid-Open No. 6-337815.
Is a data processing device described in Japanese Unexamined Patent Publication (Kokai) No. H10-26095. Also in this example, the refresh operation for the DRAM is not performed while the data processing unit is operating, as in the first conventional example.

The second prior art employs a method of changing the flag indicating the validity of a data that has not been accessed after the refresh time from a valid state to an invalid state and discarding the data. When the data processing unit is on standby, the refresh circuit is activated. That is, D
Refresh address data is generated at regular time intervals shorter than the refresh time of the RAM, and the data memory and the tag memory are sequentially refreshed row by row.

A third conventional example is disclosed in Japanese Patent Laid-Open No. 7-200404.
Is a data processing system described in Japanese Unexamined Patent Publication (Kokai) No. H10-26095. In the third conventional example, a period in which no activity occurs in the secondary cache (secondary cache miss,
A method is employed in which a refresh operation is performed during an I / O access to conceal a refresh cycle, thereby suppressing a decrease in processor performance.

Also in the third conventional example, a refresh address counter is provided because the refresh operation is performed in units of rows of each memory. This counter is 1
Each time the refresh operation of one row is completed, +1 is incremented. And the refresh cycle of 16m
If the counter does not indicate the last line after s,
Since there are memory rows that have not been refreshed, the remaining memory rows are collectively refreshed only in this case.

A fourth conventional example is a semiconductor memory device described in Japanese Patent Application Laid-Open No. 3-66092. In the fourth conventional example, while a refresh operation is performed on an area where a memory access operation for actually reading or writing data is performed, a remaining memory area where a memory access operation is not performed is performed. No refresh operation has been performed for this. Therefore, power consumption is reduced.

A fifth conventional example is disclosed in Japanese Unexamined Patent Publication No. 9-237492.
Is a memory control device described in Japanese Unexamined Patent Publication (Kokai) No. H10-26095. The fifth conventional example aims at flexibly controlling the number of banks and the combination thereof in which refresh operations are performed simultaneously.

Here, the structure of the secondary data cache of the Intel Pentium (registered trademark) processor will be described. The structure of the secondary data cache of the Pentium processor is described in the document "PENTIUM PROCESSOR SYSTEM ARC".
HITECTURE, page 166 (by MINDSHARE, INC.) ". In the secondary data cache of the Pentium processor, write-back is adopted as a write operation method, 2-way set associative is adopted as an index method, and LRU (least-r
ecently used) algorithm. FIG.
FIG. 4 is a schematic diagram showing a structure of a secondary data cache of the Pentium processor.

To the secondary data cache of the Pentium processor, two addresses are input from a superscalar CPU and one address is input from a main memory by a snoop operation. The directory (DIRECTOR
The two areas indicated by Y) are the tag memory and the way (WAY)
The two areas indicated by correspond to the data memory. Then, of the physical addresses input to the secondary cache,
The line address is input to the tag memory, from which tag data and status bits are output. This tag data is compared with the page address in the physical address, and the logic with the status bit is taken to determine a cache miss / hit.

FIG. 21 is a schematic diagram showing a state transition of the secondary data cache of the Pentium processor. In a write-back type cache in a multi-CPU system, the status bits are set to 2 in order to express four states of shared (SHARE), modified (MODIFIED), exclusive and invalid (INVALID).
There are bits. Here, SHARED is
A state in which the data in the secondary cache matches the data in the main memory, and the data is modified (MODIFIE
D) is a state in which only the data in the secondary cache is rewritten, and the data in the secondary cache and the data in the main memory do not match.
IVE) means 1 only 2 in a multi-CPU system
This is a state in which data matching the main memory is stored in the next cache, and "INVALID" is a state in which the secondary cache is not operating and is invalid.

Then, as shown in FIG. 21, for example, when the status bit is shared (SHARED) and a write hit (WRITE HIT) occurs, the status bit remains SHARED or EXCLUSIVE. ). If the status bit is modified (MODIFIED)
In the case of, if a write hit (WRITE HIT) occurs, it remains modified (MODIFIED). Note that FIG.
In, External Snoop (EXTERNAL SNOOP)
Is a snoop operation between the secondary cache and the main memory, and an internal snoop (INTERNAL SNOOP)
Is a snoop operation between the secondary cache and the primary cache.

In such a secondary cache, for example, if the status bit is invalid (INVALID), it is always determined that a cache miss has occurred, without being restricted by the result of comparison between the tag data and the page address.
The LRU bit is a bit indicating which cache data of way (WAY) 0 or way (WAY) 1 has not been used recently in line address units. The cache data is replaced. Of the physical addresses input to the secondary cache, all addresses (line addresses and bank selection addresses) other than the page address are input to the data memory, and data input / output (read and write operations) with the outside of the secondary cache is performed. Operation) is performed.

[0019]

However, when the data processing unit is operating in the first conventional example or the second conventional example, data that is not accessed after the refresh time is discarded. I have. In both cases, the existence of a dirty bit (modified bit) indicating whether the data written to the cache memory is the same as or different from the data existing in the main memory is not specified. Therefore, in either case, it is considered that the write-through method is assumed as the method of the write operation to the cache memory. Actually, in the case of these conventional examples, the write-through method has to be adopted. This is because, in the write-back method, the period in which the data written to the cache memory is different from the data existing in the main memory may exceed the refresh time sufficiently, and in such a case, the write-back method This is because data cannot be discarded from the viewpoint of coherency. In general, the write-through method has the disadvantage that the system bus is more likely to be occupied by the data transfer to the main memory than the write-back method, resulting in a decrease in system performance. Is a major problem.

In the second conventional example or the third conventional example, it is not necessary to perform a refresh operation on a memory cell in an area whose contents are in an invalid state. The refresh operation is performed on all the memory cells in the memory cells.
Therefore, waste (overhead) from the viewpoint of power consumption
Will occur. This overhead becomes more noticeable in a standby state (standby mode) for the purpose of reducing the power consumption of the entire chip.

Further, in the fourth conventional example, the effect of reducing power consumption is not sufficient because a refresh operation is performed in an area where memory access has been performed. Also, it is not clear whether the refresh operation can be controlled in units of memory cells accessed by an input address when tag data exists.

Further, in the fifth conventional example, reduction in power consumption is not achieved.

The present invention has been made in view of such a problem, and a semiconductor device capable of reducing refresh current consumption regardless of whether a cache employs a write-through system or a write-back system for its write operation system. It is an object to provide an integrated circuit device.

[0024]

A semiconductor integrated circuit device according to the present invention controls a cache provided with a dynamic random access memory and a refresh operation of the dynamic random access memory in association with a status bit of an address in the cache. And a cache control circuit.

In the present invention, since the refresh operation of the dynamic random access memory is controlled in association with the status bit, the refresh operation is performed not only in the area where the memory access is not performed but also in the area where the memory access is performed. It is possible not to do it. Accordingly, the refresh current consumption can be reduced regardless of which of the write-through method and the write-back method is employed as the cache write operation method.

The cache control circuit may perform a refresh operation of the dynamic random access memory when the status bit indicates that the cache is valid.

The cache control circuit may perform a refresh operation of the dynamic random access memory when the status bit indicates that data stored in an external main memory does not match the dynamic random access memory. It can be performed.

Further, the cache control circuit, when the status bit indicates that the data stored in the external main memory and the dynamic random access memory match, invalidates the status bit of the cache. Can be changed as shown.

Furthermore, the cache block arrangement method may be a two-way set associative method.

Further, the refresh operation may be performed for each line address of the cache.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit device according to an embodiment of the present invention will be specifically described below with reference to the accompanying drawings. The first embodiment is a microcomputer chip with embedded memory using a DRAM as a secondary cache. FIG. 1 is a block diagram showing a microcomputer chip with embedded memory according to the first embodiment of the present invention.

Microcomputer chip 1 with embedded memory
Central processing unit (CPU) 2 including a primary cache
And a secondary cache 3. The secondary cache 3 includes a secondary cache control circuit 4, a secondary cache tag memory 5, and a secondary cache data memory 6. The secondary cache tag memories 5 and 2
The next cache data memory 6 is composed of a DRAM.

FIG. 2 is a block diagram showing a computer system using a microcomputer chip with embedded memory according to the first embodiment of the present invention. In this system, two microcomputer chips 7 and 8 with embedded memory, a main memory 9 having a DRAM and a DRAM control circuit for controlling the DRAM, and a peripheral device 10 such as a hard disk are connected to a system bus 11. . Further, in this system, a tightly-coupled system is adopted in which two CPUs provided respectively in the memory-comprising microcomputer chips 7 and 8 share one main memory 9.

In the cache of the write-back system in such a multi-CPU system, as described above, the status bits are 4 bits of SHARED, MODIFIED, EXCLUSIVE, and INVALID. There are two bits to represent one state.

In the secondary data cache according to the first embodiment, similarly to the Pentium processor shown in FIG. 20, write back is adopted as a write operation method, and 2-way set associative is used as an index method. LRU (l
east-recently used) algorithm is employed.
Further, the secondary cache 3 employs a unified cache system which does not distinguish between data and instructions. Further, in general, a virtual address system is used as a system for managing the memory of the system. In the present embodiment, the CPU 2 converts a virtual address into a physical address. , The physical address is used.

FIG. 3 is a block diagram showing a tag memory used in the first embodiment of the present invention. This tag memory corresponds to the directory 0 of the Pentium processor shown in FIG. The tag memory provided in the first embodiment is provided with a memory cell array composed of one DRAM, and this memory cell array has m word lines WL1 ₀ , WL1 ₁ ,. , WL
1 _m-2 and WL1 _m-1 and _one bit line (data line) BL1 ₀ , BL1 ₁ ,..., BL1 _l-2 intersecting therewith
And BL1 _l-1 are provided. m word lines WL
1 ₀ to WL1 _m-1 are connected to the row decoder circuit RD1. Also, l bit lines BL1 _{0 to} BL1 _l-1 are connected to sense amplifier circuits SA1 ₀ , SA1 ₁ ,.
1 _l-2 and SA1 _{l-1 and the} data latch circuit DL1 ₀ ,
DL1 _1, · · ·, are connected to DL1 _l-2 and DL1 _l-1.

Furthermore, the tag memory, the sense amplifier control circuit SAC1 controls each sense amplifier circuits SA1 ₀ to SA1 _l-1, the row decoder control circuit RDC1 controls the row decoder circuit RD1, the row decoder circuit RD1
And a refresh address counter circuit RAC1 for incrementing the line address by +1 in the self-refresh mode.
Is provided.

The line address input to the tag memory is latched by the address latch circuit AL1, and then input to the row decoder circuit RD1, and one word line is selected. At the time of the read operation, one piece of data read from the memory cell is stored in each sense amplifier circuit SA1.
After being sense amplifier at ₀ to SA1 _l-1, it is transferred to the data latch circuits DL1 ₀ to DL1 _l-1. Two bits of this data are status bits, and the rest are compared with the tag address. On the other hand, during a write operation, the data latch circuits DL1 ₀ to DL1 _l-1 from the sense amplifier circuit SA1
_The l data transferred to _{0 to} SA1 _l-1 are respectively written in the selected memory cells. Incidentally, the sense amplifier circuit SA1 ₀ to SA1 _l-1 and row decoder circuit RD1
Are controlled by a sense amplifier control circuit SAC1 or a row decoder control circuit RDC1, respectively.

In the self-refresh mode,
The line address is incremented by +1 by the refresh address counter circuit RAC1, and the word line selected by the row decoder circuit RD1 is sequentially changed.

FIG. 4 is used in the first embodiment of the present invention.
FIG. 3 is a block diagram showing a data memory. This tag memory
Is in way 0 of the Pentium processor shown in FIG.
It is equivalent. Data provided in the first embodiment
The memory has a memory cell composed of k DRAMs.
Memory array is provided in each memory cell array.
m word lines WL2₀, WL2₁, ..., WL2_m-2
And WL2_m-1And n bit lines crossing it
(Data line) BL2₀, BL2₁, ..., BL2_{n- Two}Passing
And BL2_n-1Is provided. For each memory cell array
Here, m word lines WL2₀To WL2_m-1Is Roude
Coder circuit RD2₀Or RD2_k-1It is connected to the. Ma
In addition, n bit lines BL2₀Or BL2_n-1Is sense
Amplifier circuit SA2₀, SA2₁, ..., SA2_n-2as well as
SA2_n-1And data latch circuit DL2 ₀, DL2₁,
..., DL2_n-2And DL2_n-1It is connected to the.

[0041] Further, in the data memory, the sense amplifier control circuit SAC2 controls each sense amplifier circuit SA2 ₀ to SA2 _n-1, each row decoder circuit RD2 ₀ to RD
2 _k-1 row decoder control circuit controls the RDC 2, the row decoder circuit RD2 ₀ to RD2 _k-1 connected to the address latch circuit AL2 and the bank decoder circuit BD2,
A refresh address counter circuit RAC2 for incrementing the line address by +1 in the self refresh mode and a bank decoder address latch circuit BAL2 connected to the bank decoder circuit BD2 are provided.

The bank selection address input to the data memory is a bank decoder address latch circuit BAL2.
After that, the data is input to the bank decoder circuit BD2, and a bank selection decode signal is output. Bank selection decode signal, the row decoder circuit RD2 ₀ to RD2
_One sense amplifier circuit group including a memory cell array, a row decoder circuit, and n sense amplifier circuits, which is input to _k-1 and the sense amplifier control circuit SAC2 and activated at the time of access, is selected.

The line address input to the data memory, after being latched by the address latch circuit AL2, are input to the row decoder circuit RD2 ₀ to RD2 _k-1, 1 word line is selected. As described above, since the line address is also input to the tag memory, the address latch circuit AL2 uses the address latch circuit AL1 in the tag memory. At the time of the read operation, n pieces of data read from the memory cell, after being sense amplifier in the sense amplifier circuit SA2 ₀ to SA2 _n-1, is transferred to the data latch circuit DL2 ₀ to DL2 _n-1 You. On the other hand, during the write operation, the data latch circuit DL
2 ₀ to the sense amplifier circuit SA2 from DL2 _{n-1 0} to S
The _n data transferred to A2 _n-1 are written in each selected memory cell. Note that the sense amplifier circuit S
A2 ₀ to SA2 _n-1 and row decoder circuit RD2 ₀ to RD2 _k-1 is controlled by a respective sense amplifier control circuit SAC2 or row decoder control circuit RDC 2.

In the refresh operation, the data memory is controlled in line address units. In the self-refresh mode, first, the line address is incremented by +1 by the refresh address counter circuit RAC2 in the tag memory. Then, when the refresh operation of the tag memory is performed, only the status bits are read from the tag memory. The presence / absence of the refresh operation of the data memory is controlled according to the value of the status bit. This control method will be described in detail below. In the case of normal access, only one memory cell array is activated, but in the case of a refresh operation, all memory cell arrays can be activated simultaneously. In that case, the bank selection address is in the all-selected state.

Next, the operation of the first embodiment configured as described above will be described. Note that 2 in the present embodiment.
The status bit of the next cache takes the same state transition as that of the Pentium processor shown in FIG. In the present embodiment, the feature is particularly at the time of the refresh operation. Therefore, this feature will be described in detail.

FIG. 5 is a flowchart showing a refresh operation in the secondary cache provided in the first embodiment. During the refresh operation, the tag memory and the data memory are simultaneously refreshed in line address units.

When the refresh operation is started (step S1), the line address is input to the tag memory (step S2). Next, the memory cell in the tag memory selected based on the line address is refreshed (step S3). Next, the sense amplifier circuit SA ₀
Only the status bit is extracted from the data read to SA _l-1 to the outside, and the determination circuit determines whether or not the status bit is invalid (INVALID) (step S4). As a result, if the status bit is INVALID, the refresh operation ends without performing the refresh operation of the data memory (step S6). On the other hand, if the status bit is EXCLUSIVE, SHARED, or MODIFIED, the memory cell in the data memory selected based on the line address is refreshed (step S5). Then, the refresh operation ends (step S6).

FIG. 6 is a flowchart showing a self-refresh operation in the secondary cache provided in the first embodiment. During the self-refresh operation, the refresh address counter circuit RAC1 in the tag memory
Increments the line address by +1.

When the self-refresh operation is started (step S11), the line address is initialized to 0 (step S12). Next, the line address is input to the tag memory (step S13). Next, the memory cell in the tag memory selected based on the line address is refreshed (step S14). afterwards,
Only the status bit is taken out of the data read to the sense amplifier circuits SA _{0 to} SA _l−1 , and the determination circuit determines whether or not the status bit is INVALID (step S15). as a result,
When the status bit is INVALID, the line address is incremented by +1 by the refresh address counter circuit RAC without performing the refresh operation of the data memory (step S1).
7). On the other hand, if the status bit is EXCLUSIV
E), SHARED, or MODIFIE
In the case of D), the memory cell in the data memory selected based on the line address is refreshed (step S16), and thereafter, the line address is incremented by +1 by the refresh address counter circuit RAC1 (step S17).

Thereafter, it is determined whether or not the line address is the last address (step S18). As a result, if the address is not the final address, the line address is input to the tag memory again (step S13). On the other hand, if it is the last address, it is determined whether or not the self-refresh operation signal has been released (step S19).
As a result, if the self-refresh operation signal has not been released, the line address is initialized again (step S12). On the other hand, if the self-refresh operation signal has been released, the self-refresh mode ends (step S20).

During the self-refresh operation, the refresh interval of the memory cell selected by each line address is controlled by a timer circuit (not shown).

FIG. 7 is a flowchart showing the operation of the secondary cache when the mode is switched from the normal mode to the standby mode in the microcomputer chip with embedded memory according to the first embodiment. In the standby mode, the operation of the CPU needs to be stopped in order to reduce power consumption.
This is performed in a self-refresh mode.

In this embodiment, after switching from the normal mode to the standby mode (step S21),
The self-refresh operation shown in FIG. 6 is performed (steps S11 to S20). However, the self-refresh mode ends after returning from the standby mode.

As described above, in this embodiment, the DRA
In a microcomputer chip with embedded memory in which M is used as a secondary cache, the value of the status bit stored in the tag memory is read, and it is determined whether the information stored in the data memory is valid or invalid. : INVALID), the refresh operation is not performed on the memory cell selected by the line address in the data memory. Therefore, current consumption in the secondary cache is reduced. This effect is more remarkable in the standby mode for reducing the current consumption of the entire microcomputer chip with embedded memory.

In the first embodiment, the tag memory 4 and the data memory 5 are each provided with a memory cell array composed of a DRAM, but only the tag memory 4 is composed of an SRAM. May be provided. Also in this case, the refresh control of the data memory is performed by referring to the status bits in the tag memory, as in the first embodiment. SR in tag memory
When a memory cell array composed of AMs is provided, unnecessary access operations are added to the DRAM. Has the effect of reducing the current consumption.

Further, it may be used for a single CPU system. Further, in the secondary cache of the first embodiment,
Although a unified cache system is employed, a configuration in which data and instructions are separated can be employed. In this case, a tag memory and a data memory exist for each of data and instructions.

Further, the secondary cache of the first embodiment employs a two-way set associative as an index system. However, there is another method such as a system in which the number of ways is changed or a direct mapped system. It is also possible to take the configuration of

Although the secondary cache of the first embodiment employs a write-back method as a write operation method, a structure employing a write-through method may be employed. In this case, unlike the write-back method, the status bits represent only two states, VALID and INVALID.
Only one bit is required. FIG. 8 is a schematic diagram showing a state transition of the write-through secondary cache. The refresh operation is the same as that of the write-back type secondary cache shown in FIGS. 5 to 7 except that the exclusive (EXCLUSIVE), shared (SHARED), and modified (MODIFIED) are replaced with a valid. .

Next, a second embodiment of the present invention will be described. In the second embodiment, the data memory and the tag memory in the secondary cache are both constituted by DRAM memory cells. The secondary cache adopts a write-back method, and its state transition is the same as that of the Pentium processor shown in FIG. FIG. 9 is a flowchart showing the operation of the secondary cache when the mode is switched from the normal mode to the standby mode in the microcomputer chip with embedded memory according to the second embodiment of the present invention.

In this embodiment, after switching from the normal mode to the standby mode (step S31),
The line address is initialized to 0 (step S3
2). Next, the line address is input to the tag memory (step S33). Next, only the status bit is extracted from the data read to the sense amplifier circuit, and the status bit is determined by the determination circuit (step S34). As a result, when the status bit is INVALID, SHARED, or EXCLUSIVE, the line address is incremented by +1 by the refresh address counter circuit without performing the write-back operation (step S1). S36). On the other hand, if the status bit is modified, the data memory selected based on the line address is written back (step S35).
Thereafter, the refresh address counter circuit increments the line address by +1 (step S3).
6).

Thereafter, it is determined whether or not the line address is the last address (step S37). As a result, if it is not the final address, the line address is input to the tag memory again (step S33). On the other hand, if it is the last address, the operation enters the standby mode (step S38).

When the write-back operation for the entire secondary cache is completed, the contents of both the data memory and the tag memory are discarded, and the refresh operation for the secondary cache is not performed in the standby mode. Therefore, the current consumption of the microcomputer chip with memory in the standby mode is reduced.

FIG. 10 is a flowchart showing the operation of the secondary cache when the mode is switched from the standby mode to the normal mode in the microcomputer with embedded memory according to the second embodiment of the present invention.

After switching from the standby mode to the normal mode (step S41), the line address is initialized to 0 (step S42). Next, the line address is input to the tag memory (step S43). After that, the status bit is changed to INVALID (step S44). Next, the refresh address counter circuit increments the line address by +1 (step S45). Then, it is determined whether or not the line address is the last address (step S46). As a result, if the address is not the final address, the line address is input to the tag memory again (step S4).
3). On the other hand, if it is the last address, the operation enters the standby mode (step S47).

In the second embodiment, the tag memory is also
Although it is composed of RAM memory cells, the contents of the status bits are lost because no refresh operation is performed during standby. Therefore, when returning from the standby mode to the normal mode, all the status bits in the tag memory need to be changed to INVALID.

Next, a third embodiment of the present invention will be described. In the third embodiment, the data memory in the secondary cache is composed of SRAM memory cells, and the value of the status bit is stored even in the standby mode. Also,
The write-back method is adopted for the secondary cache, and its state transition is the same as that of the Pentium processor shown in FIG. FIG. 11 is a flowchart showing the operation of the secondary cache when the mode is switched from the normal mode to the standby mode in the microcomputer with embedded memory according to the third embodiment of the present invention.

In this embodiment, after switching from the normal mode to the standby mode (step S51),
The line address is initialized to 0 (step S5)
2). Next, the line address is input to the tag memory (step S53). Next, only the status bit is taken out of the data read to the sense amplifier circuit, and the status bit is determined by the determination circuit (step S54). As a result, the status bit becomes shared (SHAR
If it is ED) or EXCLUSIVE, the content of the status bit is changed to INVARID without performing a write-back operation (step S56). On the other hand, if the status bit is modified (MO
If it is (DIFIED), the data memory selected based on the line address is written back (step S55), and then the contents of the status bit are changed to INVARID (step S56). Then, in any case, the line address is incremented by +1 (step S57). If the status bit is INVALID, the line address is directly incremented by +1 (step S5).
7).

Thereafter, it is determined whether or not the line address is the last address (step S58). As a result, if it is not the final address, the line address is input to the tag memory again (step S53). On the other hand, if the address is the last address, the standby mode is set (step S59).

When the write-back operation for the entire secondary cache is completed, all the status bits in the tag memory are changed to INVALID, the contents of the data memory are discarded, and in the standby mode, the refresh operation for the data memory is performed. Not done. The third
In the embodiment, when returning from the standby mode to the normal mode, the operation shown in FIG. 10 is not performed.

Next, a fourth embodiment of the present invention will be described. In the present embodiment, the ride-back operation is not performed, and is applied to a case where the transfer of data from the secondary cache to the main memory is inconvenient for some reason. In the fourth embodiment, the data memory and the tag memory in the secondary cache are both constituted by DRAM memory cells. The secondary cache adopts a write-back method, and its state transition is the same as that of the Pentium processor shown in FIG. FIG. 12 is a flowchart showing the operation of the secondary cache when the mode is switched from the normal mode to the standby mode in the microcomputer chip with embedded memory according to the fourth embodiment of the present invention.

In this embodiment, after switching from the normal mode to the standby mode (step S61),
The self-refresh mode is started (step S6)
2). Next, the line address is initialized to 0 (step S63). Next, the line address is input to the tag memory (step S64). Thereafter, the memory cell in the tag memory selected based on the line address is refreshed (step S65). Then, only the status bit is taken out of the data read to the sense amplifier circuit, and the status bit is determined by the determination circuit (step S66). As a result, if the status bit is modified (MODIFIED), the memory cell in the data memory selected based on the line address is refreshed (step S67), and the line address is incremented by +1 (step S69).
If the status bit is SHARED or EXCLUSIVE, the status bit is changed to INVALID (step S6).
8) The line address is incremented by +1 (step S69). On the other hand, if the status bit is INVALID, the direct line address is +
It is incremented by one (step S69).

Thereafter, it is determined whether or not the line address is the last address (step S70). As a result, if it is not the final address, the line address is input to the tag memory again (step S64). On the other hand, if it is the last address, it is determined whether or not the self-refresh operation signal has been released (step S71).
As a result, if the self-refresh operation signal has not been released, the line address is initialized again (step S63). On the other hand, if the self-refresh operation signal has been released, the self-refresh mode ends (step S72).

Next, a fifth embodiment of the present invention will be described. Also in this embodiment, the ride-back operation is not performed, and is applied to a case where the transfer of data from the secondary cache to the main memory is inconvenient for some reason. In the fifth embodiment, the data memory in the secondary cache is composed of SRAM memory cells, and the value of the status bit is stored even in the standby mode. Also, 2
The next cache employs a write-back method, and its state transition is the same as that of the Pentium processor shown in FIG. FIG. 13 is a flowchart showing the operation of the secondary cache when the mode is switched from the normal mode to the standby mode in the microcomputer chip with embedded memory according to the fifth embodiment of the present invention.

This embodiment is different from the fourth embodiment shown in FIG. 12 in that the operation of refreshing the memory cell in the tag memory selected based on the line address (step S65) is omitted. Done.

As described above, in the fourth and fifth embodiments,
Only when the output of the status bit in the tag memory selected by the line address is modified (MODIFIED), the refresh operation of the data memory selected by the line address is performed. In other cases,
The status bit is set to INVALID, and the refresh operation of the data memory selected by the line address is not performed. Thereby, coherency of the cache data is maintained.

Next, a sixth embodiment of the present invention will be described. In this embodiment, a DRAM is used as a cache memory such as a main memory, and is mounted on the same chip as the CPU. FIG. 14 is a block diagram showing a computer system using a microcomputer chip with embedded memory according to the sixth embodiment of the present invention. In this system, two memory-embedded microcomputer chips 17 and 18 and a main memory 19 having a DRAM and a DRAM control circuit for controlling the DRAM are connected to a system bus 21. In the microcomputer chips 17 and 18 with embedded memories, a DRAM is used as a cache A or a cache B, respectively, and addresses to which the caches A and B are mapped on the main memory 19 are determined in advance.

For this reason, the tag memories provided in the first to fifth embodiments become unnecessary except for the status bits. In the case of the first to fifth embodiments, a status bit exists for each memory cell selected by a line address.
If there is no tag data, the status bits can be set flexibly in multiples of the memory cell accessed by the input address. That is, the status bits can be set for each line address, and the status bits can be set for the entire chip as one unit.

FIG. 15 is a block diagram showing a DRAM cache used in the sixth embodiment of the present invention. The DRAM cache used in the sixth embodiment is connected to a control circuit for controlling the DRAM cache. The DRAM cache used in the sixth embodiment is provided with a memory cell array composed of k DRAMs.
The RAM has m word lines WL3 ₀ , WL3 ₁ ,.
, WL3 _m-2 and WL3 _m-1 and n bit lines (data lines) BL3 ₀ , BL3 ₁ ,.
L3 _n-2 and BL3 _n-1 are provided. In each memory cell array, m word lines WL3 ₀ to WL3 _m-1
It is connected to the row decoder circuit RD3 ₀ to RD3 _{k -1.} The bit line BL3 ₀ through BL3 _n-1 of the n are each sense amplifier circuit _{SA3 0, SA3 1, ···,} SA3
_n-2 and SA3 _n-1 and the data latch circuit DL3 _0, D
L3 _1, · · ·, are connected to DL3 _n-2 and DL3 _n-1.

[0079] Further, the DRAM cache, each sense amplifier circuit SA3 ₀ to SA3 Sense amplifier control circuit SAC3 controls the _n-1, each row decoder circuits RD3 ₀ to row decoder control circuit for controlling the RD3 _k-1 RDC
3, the row decoder circuit RD3 ₀ to RD3 _k-1 connected to the address latch circuit AL3, the sense amplifier circuit SA3
_{0 to} SA3 _n-1 and the row decoder circuit RD3 _{0 to} RD
Block decoder circuit BD3 connected to 3 _k-1 and a refresh address counter circuit R for incrementing the line address by +1 in a self-refresh mode
An AC3, a block decoder address latch circuit BAL3 connected to the block decoder circuit BD3, and a status register SR3 are provided.

In the case of the data memory of the first embodiment,
One memory cell array is selected by the bank selection address. In the case of this embodiment, however, the number of banks is one, and one memory cell array is selected by the upper address of the addresses input to the DRAM cache. Is done. After the upper address is latched by the block decoder address latch circuit BAL3, it is input to the block decoder circuit BD3, and a block selection decode signal is output. Block selection decode signal is input to the row decoder circuit RD3 ₀ to RD3 _k-1 and the sense amplifier control circuit SAC3, constituted by the memory cell array, a row decoder circuit and the n sense amplifier circuits being activated when accessing the sense One amplifier circuit group is selected.

The block selection decode signal is input to a status register SR3 in which status bits are stored.
In the case of the DRAM cache used in this embodiment, the status bits are shared (SH) in units of k memory cell arrays.
ARED), Modified (MODIFIED), EXCLUSIVE (EXCLUSIVE) and INVALID (INVALID) are set in two bits each to correspond to the four states,
There are 2k bits in total. This state bit takes the same state transition as the Pentium processor shown in FIG.

On the other hand, the lower address is latched by the address latch circuit AL3, and then the row decoder circuit RD3 ₀
To RD3 _k-1 to select one word line. At the time of the read operation, n pieces of data read from the memory cell, after being sense amplifier in the sense amplifier circuit SA3 ₀ to SA3 _n-1, is transferred to the data latch circuit DL3 ₀ through DL3 _n-1 You. On the other hand, during a write operation, respectively are written into the memory cells of n data transferred from the data latch circuit DL3 ₀ through DL3 _n-1 in the sense amplifier circuit is selected. Incidentally, the sense amplifier circuit SA3 ₀ to SA3 _n-1 and row decoder circuit RD3
_{0 to} RD3 _k-1 are sense amplifier control circuits SAC3, respectively.
Alternatively, it is controlled by the row decoder control circuit RDC3.

In this embodiment, the refresh operation is controlled in units of k memory cell arrays. At the time of refresh, the upper address is input to the status register, and the status bit is read. The presence or absence of a refresh operation of the DRAM cache is controlled according to the value of this status bit.

FIG. 16 is a flowchart showing a refresh operation in the DRAM cache provided in the sixth embodiment of the present invention.

When the refresh operation is started (step S81), the upper address is input to the status register SR3 (step S82). Next, the state bit of the memory cell array selected based on the upper address is determined (step S83). As a result, when the status bit is INVALID, the refresh operation ends without performing the memory cell refresh operation (step S85). On the other hand, if the status bit is EXCLUSIVE, shared (SHARED), or modified (MODIFIED), the memory cell in the memory cell array selected based on the upper address is refreshed (step S84). Then, the refresh operation ends (step S85).

FIG. 17 shows the DRA provided in the sixth embodiment.
5 is a flowchart illustrating a self refresh operation in the M cache.

When the self-refresh operation is started (step S91), the address is initialized to 0 (step S92). Next, the upper address is input to the status register SR3 (step S93). Next, the state bit of the memory cell array selected based on the upper address is determined (step S94). As a result, if the status bit is INVALID,
The address is incremented by +1 by the refresh address counter circuit RAC3 without performing the memory cell refresh operation (step S96). On the other hand, when the status bit is EXCLUSIVE, shared (SHARED), or modified (MODIFIED), the memory cell in the memory cell array selected based on the upper address is refreshed (step S95). +1 is incremented by the refresh address counter circuit RAC3 (step S96).

Thereafter, it is determined whether or not the address is the last address (step S97). As a result, if the address is not the final address, the upper address is input to the status register SR3 again (step S93). On the other hand, if it is the last address, it is determined whether or not the self-refresh operation signal has been released (step S98). As a result, if the self-refresh operation signal has not been released, the address is initialized again (step S9).
2). On the other hand, if the self-refresh operation signal has been released, the self-refresh mode ends (step S99).

FIG. 18 is a flow chart showing the operation of the DRAM cache when the mode is switched from the normal mode to the standby mode in the microcomputer chip with embedded memory according to the second embodiment.

In this embodiment, after the mode is switched from the normal mode to the standby mode (step S10).
1), the self-refresh operation shown in FIG. 17 is performed (steps S91 to S99).

Although the sixth embodiment is a modification of the first embodiment, the single CPU is similar to the first embodiment.
The system may be used, a direct map II system may be adopted as an index system, or a write-through system may be adopted as a write operation system.

Further, in each of the second to fifth embodiments, similarly to the sixth embodiment, it is possible to adopt a structure without a tag memory except for the status bits.

[0093]

As described in detail above, according to the present invention,
The refresh operation of the dynamic random access memory is controlled by the cache control circuit in association with the status bit, so that the refresh operation is not performed not only in the area where the memory access is not performed but also in the area where the memory access is performed. can do.
Therefore, it is possible to reduce the refresh current consumption regardless of the cache write operation method.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a microcomputer chip with embedded memory according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a computer system using a microcomputer chip with embedded memory according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a tag memory used in the first embodiment of the present invention.

FIG. 4 is a block diagram showing a data memory used in the first embodiment of the present invention.

FIG. 5 is a flowchart illustrating a refresh operation in a secondary cache provided in the first embodiment.

FIG. 6 is a flowchart showing a self-refresh operation in a secondary cache provided in the first embodiment.

FIG. 7 is a flowchart showing the operation of the secondary cache when the mode is switched from the normal mode to the standby mode in the memory-embedded microcomputer chip according to the first embodiment.

FIG. 8 is a schematic diagram showing a state transition of a write-through secondary cache;

FIG. 9 is a flowchart showing the operation of the secondary cache when the mode is switched from the normal mode to the standby mode in the microcomputer chip with embedded memory according to the second embodiment of the present invention.

FIG. 10 is a flowchart showing the operation of the secondary cache when the mode is switched from the standby mode to the normal mode in the memory-embedded microcomputer chip according to the second embodiment of the present invention.

FIG. 11 is a flowchart showing the operation of the secondary cache when the mode is switched from the normal mode to the standby mode in the microcomputer with embedded memory according to the third embodiment of the present invention.

FIG. 12 is a flowchart showing the operation of the secondary cache when the mode is switched from the normal mode to the standby mode in the microcomputer chip with embedded memory according to the fourth embodiment of the present invention.

FIG. 13 is a flowchart showing the operation of the secondary cache when the mode is switched from the normal mode to the standby mode in the microcomputer with embedded memory according to the fifth embodiment of the present invention.

FIG. 14 is a block diagram showing a computer system using a microcomputer chip with embedded memory according to a sixth embodiment of the present invention.

FIG. 15 shows a DRAM used in a sixth embodiment of the present invention.
It is a block diagram showing a cache.

FIG. 16 shows a DRAM provided in a sixth embodiment of the present invention.
5 is a flowchart illustrating a refresh operation in a cache.

FIG. 17 is a flowchart showing a self-refresh operation in a DRAM cache provided in a sixth embodiment.

FIG. 18 is a flowchart showing the operation of the DRAM cache when the mode is switched from the normal mode to the standby mode in the memory-embedded microcomputer chip according to the second embodiment.

FIG. 19 is a block diagram showing a conventional cache memory described in JP-A-6-314240.

FIG. 20 is a schematic diagram showing a structure of a secondary data cache of the Pentium processor.

FIG. 21 is a schematic diagram showing a state transition of a secondary data cache of the Pentium processor.

[Explanation of symbols]

1, 7, 8, 17, 18; microcomputer chip with embedded memory 2, CPU 3, secondary cache 4, secondary cache control circuit 5, secondary cache tag memory 6, secondary cache data memory 9, 19; main memory 10; peripheral devices 11 and 21; the system bus _{WL1 0, WL1 1, WL1 m} -2, WL1 m-1, WL2 0,
_{WL2 1, WL2 m-2,} WL2 m-1, WL3 0, WL3 1,
_{WL3 m-2, WL3 m-} 1; word lines _{BL1 0, BL1 1, BL1 l} -2, BL1 l-1, BL2 0,
_{BL2 1, BL2 n-2,} BL2 n-1, BL3 0, BL3 1,
_{BL3 n-2, BL3 n-} 1; bit line _{SA1 0, SA1 1, SA1 l} -2, SA1 l-1, SA2 0,
_{SA2 1, SA2 n-2,} SA2 n-1, SA3 0, SA3 1,
_{SA3 n-2, SA3 n-} 1; sense amplifier circuit _{DL1 0, DL1 1, DL1 l} -2, DL1 l-1, DL2 0,
_{DL2 1, DL2 n-2,} DL2 n-1, DL3 0, DL3 1,
_{DL3 n-2, DL3 n-} 1; data latch circuit _{RD1, RD2 0, RD2 1,} RD2 k-2, RD2 k-1, R
_{D3 0, RD3 1, RD3 k} -2, RD3 k-1; row decoder circuit AL1, AL2, BAL2, AL3, BAL3; address latch circuit RDC1, RDC2, RDC3; row decoder control circuit SAC1, SAC2, SAC3; sense amplifier Control circuit RAC1, RAC2, RAC3; refresh address counter circuit BD2; bank recorder circuit BD3; block decoder circuit SR3; status register

Claims (6)

[Claims] 1. A semiconductor, comprising: a cache having a dynamic random access memory; and a cache control circuit for controlling a refresh operation of the dynamic random access memory in association with a status bit of an address in the cache. Integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein said cache control circuit performs a refresh operation of said dynamic random access memory when said status bit indicates that said cache is valid. . 3. The refresh operation of the dynamic random access memory when the status bit indicates that data stored in an external main memory does not match the dynamic random access memory. 2. The semiconductor integrated circuit device according to claim 1, wherein: 4. The cache control circuit, when the status bit indicates that data stored in an external main memory and the dynamic random access memory match, invalidates the status bit of the cache. The semiconductor integrated circuit device according to claim 3, wherein the semiconductor integrated circuit device is changed to indicate the following. 5. The cache block arrangement method according to claim 1,
5. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device employs a two-way set associative method. 6. The semiconductor integrated circuit device according to claim 1, wherein the refresh operation is performed for each line address of the cache.