JPH02227897A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten a data transfer time between a cache memory and a main memory and to improve the throughput of a system by permitting a data register on a data line to function as the cache memory. CONSTITUTION:On all data lines DLo, the inverse of DLo to DLm, the inverse of DLm, transfer gates To0-Tm1 and a data register DRG to simultaneously hold all data to be read are provided. An address stored in an address register ARG and an address supplied from an external part are compared, and when the addresses do not coincide, the transfer gates To0-Tm1 are opened, all data are held in the data register DRG, and when the addresses coincide, the necessary data are outputted from the inside of the data register DRG to the external part while the transfer gates To0-Tm1 are closed. Consequently, the data register DRG functions as the cache memory. Thus, the data transfer time between the cache memory and main memory can be shortened, and the throughput of the system can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory technology and a technique particularly effective when applied to a buffer storage device, for example, a technique effective when applied to a cache memory.

[Prior Art] Conventionally, in a microcomputer that employs a buffer storage method, frequently used information in a main memory device such as a dynamic RAM is stored in a cache memory, and this information is stored in a cache controller. There are some devices that are controlled by a storage management device called . . . to improve throughput.

Cache memory is a microprocessor unit (
When the desired data is accessed by the address output from the MPU (hereinafter referred to as MPU) and is in the cache memory, that is, when the cache is hit, the MPU can immediately obtain the data, improving system throughput. .

The cache controller compares the address output from the MPU with an internal address (tag), and if it determines that the desired data is not in the cache memory, outputs a signal indicating a miss.

The MPU or cache controller then accesses the main memory to obtain data from the main memory.

At this time, data is transferred from the main memory to the cache memory in addition to the data required by the MPU, as well as one block (usually 256 to 4 bytes) of data including that data. . This is an MPU
This is because when accessing memory, there is a high rate of intensively accessing contiguous areas in the memory space, so by storing it in cache memory, the hit rate can be increased (Nikkei McGraw-Hill) issue,
"Nikkei Electronics J, November 16, 1987 issue, pages 170 and 171).

[Problems to be Solved by the Invention] However, since conventional cache memories are formed on a semiconductor chip separate from the main memory, data transfer of one word is limited by the cycle time of the main memory. Therefore, it takes a longer time to transfer block data, which reduces the throughput of the memory bus.
Since the CPU cannot access the cache memory, the throughput of the MPU bus also decreases. Furthermore, in order to increase the cache hit rate, the larger the unit of block transfer between the cache memory and the main memory is, the more the bus throughput decreases.

An object of the present invention is to easily configure a buffer storage system, reduce data transfer time between cache memory and main memory, and improve system throughput.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a data register capable of holding all the data read simultaneously with the transfer gate is provided on all data lines in a readable and writable semiconductor memory (dynamic RAM) constituting the main memory device, and an address register and this data register are provided on all data lines. An address comparator is provided to compare the address stored in the address register with the address supplied from the outside. If the addresses do not match, the transfer gate is opened and all data on the data line is held in the data register. When a match occurs, the desired data is output from the data register to the outside while the transfer gate is closed.

[Operation] According to the above means, the data register on the data line functions as a cache memory, so the main memory and the cache memory are built on the same semiconductor chip, and the data between the main memory and the cache memory is In addition to shortening the transfer cycle, the data transfer unit is not limited to the conventional word unit (32 bits) between the main memory and cache memory, but can transfer the amount equivalent to one block (total number of memory cells on the selected word line). Data can be transferred all at once, and the number of transfer cycles can be significantly reduced.

[Embodiment] FIG. 1 shows an embodiment of a semiconductor memory device according to the present invention.

In FIG. 1, reference numeral M-ARY indicates a memory array in which memory cells are arranged in a matrix. This memory array M-ARY is composed of dynamic memory cells consisting of an information charge storage capacitor and a selection MO3FET in order to satisfy the requirement of large capacity when used as a main memory.

Furthermore, every other memory cell in the same row in the memory array M-ARY is connected to the same word line WL, ~WLn, and each cell in an adjacent memory column is connected to a pair of complementary data lines D.
L,, DL, ~DLm, DLm are connected to each data g D L l l D L 1 (i=.28.
A preamplifier PAi is connected for each line (m), and data is read by amplifying the level difference between the data lines.

In this embodiment, the data lines DL L , DL i
A latch circuit LTi is connected between them via transfer MO3FETs Ti, Ti, respectively, and the latch circuit LTi is further connected to a selection switch MO5FETQ.
common data line CDL, C via lt+Q l,
Connected to DL. And the above common data line C
A data write circuit WR and a data output buffer DOB are connected to DL and CDL, respectively.

Note that FIG. 1 only shows a circuit that outputs 1-bit read data, but when outputting 16-bit data, for example, 16 memory mats with the above configuration are provided, and data is read from each memory mat. It may be configured to simultaneously read and output one bit at a time.

Reference symbols XDll-XDn indicate internal complementary address signals a0-ak formed by the address buffer ABF based on the address signal AD supplied from the outside, which are decoded to select one of the word lines WL, -WLn. word decoders, YD, ~YDm, driving one to the selection level;
is the above switch M OS F based on the address signal.
ETQi! , Qi, which forms a selection signal that turns on one set.

In this embodiment, internal address signals a0 to
A transfer gate circuit TG is provided for supplying or cutting off ak to the decoder.

Along with this, an address register ARG capable of latching the internal address signals a0 to ak, and an address comparison that compares the address held in this address register ARG with the internal address signals a, to ak supplied from the address buffer ABF. A device CMP is provided.

Address comparator CMP outputs a hit signal HIT when two address signals completely match.

This signal is supplied to the control circuit 1!6CNT, -
When M, the control signal φC is changed to low level, and when they do not match, the signal φT is changed to high level. This signal φC is supplied to address register ARG, causing the address register to latch the address signal being supplied at that time. Further, the control circuit CNT receives the above-mentioned hit signal HTT and external read/write control signal R/
A control signal φT is generated based on W. This signal φT is connected to the transfer gate circuit TO and the transfer MOS.
It is supplied to FET T, , ~Tm, to make them conductive or cut them off.

FIG. 2 shows an example of the configuration of the control circuit CNT.
Also, in FIG. 3, a latch circuit LT0 forming a data register DRG that holds data read out on the data line.
~LTm configuration examples are shown respectively.

The control circuit CNT includes inverters INV, AND
It consists of gates G, ,G, and OR gate G, and takes in the hit signal HIT from the address comparator CMP and the read/write control signal R/W in synchronization with the clock CLK, and generates a truth table as shown in Table 1. Control signal φC2φ according to
Form a T.

The latch circuit LTi is composed of, for example, two CMOS inverters having one output terminal connected to the other input terminal.

Next, the operation of the memory configured as described above will be explained using the timing chart of FIG.

First, during data reading when the read/write control signal R/W is at a high level, when an address signal AD is input from the outside, internal address signals 80 to ak are formed in the address buffer ABF, and the address comparator CM
P and column decoders YD, to YDm, and turns on any one set of column switches Qi, , Qi.

In the address comparator CMP, internal address signals a0 to ak
and the address in the address register ARG are compared. If the two addresses do not match, a low level hit signal HIT is supplied to the control circuit CNT. Then, the control circuit CNT outputs high-level control signals φC and φT based on the signal HIT and the read/write control signal R/W. Control signal φT is supplied to gate circuit GT to make it conductive, and internal address signals a0 to ak are supplied to word decoders XD, to XDn to change any one word line to a selection level.

Further, the high-level control signal φT is supplied to the transfer Mo5FETT, . . . -Tm1 on the data line, turning them all on. Therefore, the information of the memory cells connected to the selected word line is transmitted to the preamplifier PA, ~
Amplified by P A m and transferred MO3FE
Latch circuit L T o= via T T, , ~Tm,
At the same time, the data corresponding to the column switches Qi, Qis that are turned on at that time is supplied to the output buffer DOB, and the output terminal Dout is changed to a high level or a low level depending on the read data. . In addition, in parallel with reading the above data, 1,
By supplying control signal φC to address register ARG, internal address signals a6 to ak at that time are stored in address register ARC.

On the other hand, when address comparator CMP determines that the addresses match and a high level hit signal HIT is generated, control signals φC2φT output from control circuit 1IlcNT are both set to low level. Then, transfer gate circuit TO and transfer MO
Since the 8FETs To, ~Tm are made non-conductive, the data held in the latch circuits LT, ~LTm is transferred to the column switches Qi1. Qi, and is supplied to the output buffer DOB and output. Therefore, desired data is immediately output without waiting for the memory cell to be accessed.

During data writing when the read/write control signal R/W is set to low level, if the comparison result in the address comparator CMP is "match", the control signal φC is set to low level and φT is set to high level, so that externally supplied control signal φC is set to low level and φT is set to high level. The written write data is latched in the selected latch circuit LTi, and the transfer MO5FET T is turned on by the control signal φT. The same data as the latch data of the latch circuits LT and -LTm is written in a write-through manner to all memory cells connected to the word line in the 1 selected state via the ~Tm process. At this time, address register ARG does not take in the address signal.

On the other hand, when the comparison result in the address comparator CMP is ``mismatch'', both control signals φC1φT are set to high level.Therefore, the write data is latched in the latch circuit LTi corresponding to the column address, and all the latch circuits LT0 to The data of LTm is simultaneously written to the selected memory cells of the same row, and the internal address signal a
0 to 8k are stored in address register ARG.

FIG. 5 shows a second embodiment of the semiconductor memory device according to the present invention.

In the embodiment shown in FIG. 1, a memory cell is selected by waiting for the comparison result in address comparator CMP and supplying an address signal to word decoders DR, -DRn only when there is a mismatch. Although there is a slight delay in reading data in the event of a mishit, this has the advantage of reducing current consumption by reducing the number of times the decoder is opened.

On the other hand, in the embodiment of FIG. 4, the address comparator CMP
The memory array M-ARY is accessed in parallel with the comparison in . Although this increases the current consumption to some extent, data reading in the event of a mishit becomes faster.

As explained above, in the above embodiment, data registers capable of holding data read simultaneously with transfer gates are provided on all data lines in a readable and writable semiconductor memory (dynamic RAM), and an address register and An address comparator is provided to compare the address stored in this address register with the address supplied from the outside. If the addresses do not match, the transfer gate is opened and all data on the data line is held in the data register, and the address is When they match, the desired data is output from the data register to the outside while the transfer gate is closed, so that the data register on the data line functions as a cache memory. Therefore, main memory and cache memory are built into the same semiconductor chip, which shortens the data transfer cycle between main memory and cache memory, and the unit of data transfer is a word between main memory and cache memory. Data equivalent to one block (total number of memory cells on the selected word line) can be transferred at once without being limited to units (32 bits), and the number of transfer cycles can be significantly reduced. . As a result, the buffer storage system can be easily configured, and the data transfer time between the cache memory and the main memory can be shortened, thereby improving the throughput of the system.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in the above embodiment, the address register and the address comparator are formed on the same chip as the memory array, but they can also be provided as external circuits outside the chip.

Further, in the above embodiment, the memory array is composed of dynamic memory cells, but the memory array may be composed of static memory cells.

In the above explanation, the invention made by the present inventor was mainly applied to cache memory, which is the field of application that formed the background of the invention, but the present invention is not limited thereto; Other buffer storage devices can generally be used.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, when the semiconductor memory device according to the present invention is used,
The buffer storage system can be easily configured, and the data transfer time between the cache memory and the main memory can be shortened, and the throughput of the system can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a logical configuration diagram showing an example of the configuration of a control circuit, and FIG. 3 is a circuit diagram showing an example of the configuration of a latch circuit. , FIG. 4 is a time chart 5 showing the operation timing of the memory device of the embodiment. FIG. 5 is a block diagram showing a second embodiment of the semiconductor memory device according to the present invention. M-ARY ----Memory array, LT, ~L
Tm...Latch circuit, DRG...Data register, T. ~Tm,...Transfer MO8FET
, XD, ~XDn...word decoder. ARG...address register, CMP...address comparator. Figure Figure Figure Figure Figure

Claims (1)

[Claims] 1. A memory array in which memory cells are arranged in a matrix, a selection circuit for selecting an arbitrary memory cell in the memory array based on an external address, and the memory array a data holding means for latching data read from the memory array; and a switch means provided between the data holding means and the memory array, wherein a part of the data stored in the memory array passes through the switch means. A semiconductor memory device, characterized in that the semiconductor memory device is configured to be held in the data holding means via the data holding means. 2, comprising an address holding means capable of holding an address, and an address comparing means for comparing the address held in the address holding means and an address supplied from the outside;
The data in the memory array corresponding to the address in the address holding means is held in the data holding means, and when the two addresses match as a result of the comparison in the address comparing means, the data holding means 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured to read and write data. 3. A transfer gate is provided before the selection circuit,
If the two addresses do not match as a result of the comparison in the address comparison means, an external address is supplied to the selection circuit via the transfer gate;
3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is configured to perform access to a memory array.