JP2000106370A - Bipolar transistor having negative resistance - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a transistor exhibiting a large negative resistance under room temperature. SOLUTION: A transistor 100 has an emitter region 10, a base region 20 and a collector region 50. The collector region 50 has first and second collector layers 30, 40. The first collector layer 30 is heavily doped so that electrons in the collector region 50 migrate to the base region 20 through tunnel effect under room temperature. The first collector layer 30 is provided contiguously to the base region 20. The second collector layer 40 is provided contiguously to the first collector layer 30 and doped lighter than the first collector layer. According to the structure, the transistor 100 exhibits a large negative resistance under room temperature.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor, and more particularly to a bipolar transistor having improved high-frequency characteristics and capable of obtaining a high negative resistance at room temperature.

[0002]

2. Description of the Related Art In order to attain multifunctionality and high performance of semiconductor ICs, research on transistors utilizing a tunnel effect has been actively conducted. In the voltage-current characteristics of such a transistor, non-linear characteristics can be obtained due to the negative resistance derived from the tunnel effect. When the transistor has a negative resistance and a certain load is applied, a plurality of stable points can be obtained in the voltage-current characteristic curve. By utilizing these characteristics, in semiconductor ICs,
It is possible to reduce the number of elements such as a logic circuit or a dividing cycle.

Conventionally, as a configuration for obtaining a negative resistance, a structure in which a tunnel diode is added to a normal transistor has been adopted. Bell Labs' Capasso et al. Proposed a transistor structure in which a heterojunction bipolar transistor and a resonant tunneling diode were connected in series. In this transistor structure, since the resonant tunneling diode is coupled to the emitter region of the transistor, the overall element length from the emitter to the collector increases.

There is also a double heterojunction bipolar transistor in which the emitter and the collector use a material having a larger band gap than the base. This transistor structure operates normally at room temperature,
At low temperatures, specifically at temperatures around 77K,
It is known that negative resistance occurs.

[0005] Although not a bipolar transistor, a transistor structure utilizing a tunnel effect is
A transistor structure in which a high electron mobility transistor (HEMT) and a resonant tunneling diode are connected in series has also been proposed.

[0006]

The transistor has a parasitic resistance. Since this parasitic resistance adversely affects the high-frequency characteristics of the transistor, it is desirable that the parasitic resistance be as small as possible. In addition, when the element length is long, the electron transit time from the time when the electron leaves the emitter to the time when the electron reaches the collector becomes longer, so that the high-frequency characteristics deteriorate. Therefore, in order to obtain excellent high-frequency characteristics, it is necessary to reduce the element length and the parasitic resistance as much as possible.

Further, a transistor which exhibits a negative resistance only at a low temperature, when actually incorporated in a semiconductor IC,
Since it cannot exhibit negative resistance at room temperature, it has little practical value as a negative resistance element. Therefore, the development of a transistor having excellent high-frequency characteristics and capable of obtaining a large negative resistance at room temperature has been desired in the technical field.

The conventional transistor structure proposed by Capasso et al., That is, a transistor structure in which a heterojunction bipolar transistor and a resonant tunneling diode are connected in series, cannot be said to have excellent high-frequency characteristics from the above viewpoint. This is because the transistor structure has a structure in which a resonant tunneling diode is added in series to the emitter region, so that the element length is correspondingly increased, and furthermore, the parasitic resistance of the entire transistor structure is reduced by the parasitic resistance in the resonant tunneling diode. This is because the resistance increases due to the resistance. Therefore, this transistor structure can obtain a negative resistance, but has a disadvantage of deteriorating high-frequency characteristics instead.

Further, the conventional double heterojunction bipolar transistor structure can obtain negative resistance at a low temperature (77 K). However, since this transistor exhibits negative resistance only at a low temperature, it is impossible to actually incorporate it into a circuit in expectation of negative resistance characteristics.
When such a transistor is incorporated in a circuit, temperature control is difficult or almost impossible, and it can be said that practical use is difficult.

Therefore, the present invention can obtain a large negative resistance at room temperature, which can solve the above problems,
It is another object of the present invention to provide a bipolar transistor having excellent high-frequency characteristics. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous embodiments of the present invention.

[0011]

According to a first aspect of the present invention, there is provided a bipolar transistor having an emitter region, a base region adjacent to the emitter region, and a collector region adjacent to the base region. A bipolar transistor, wherein the collector region includes a first collector layer that is heavily doped so that electrons in the collector region move to the base region by a tunnel effect. . In this bipolar transistor, a tunnel effect can be generated by setting the doping concentration of the first collector layer high.

In one embodiment of the first mode, the first collector layer is highly doped so that the bipolar transistor exhibits a negative resistance at room temperature. By setting the doping concentration of the first collector layer high, the bipolar transistor
A large negative resistance due to the tunnel effect can be obtained.

In another aspect of the first aspect, the first aspect
The collector layer is provided adjacent to the base region.

[0014] In still another mode of the first mode, the first collector layer may have a band gap wider than a band gap of a layer of the base region adjacent to the first collector layer.

In still another aspect of the first aspect, the base region may include a layer made of GaAs, and the first collector layer may be made of InGaP.

In still another aspect of the first aspect, the first collector layer may be formed of the same semiconductor material as a layer of the base region adjacent to the first collector layer.

In still another aspect of the first aspect, the base region may have a layer made of GaAs, and the first collector layer may be made of GaAs.

In still another embodiment of the first embodiment, it is preferable that the doping concentration of the first collector layer is set to 1 × 10 ¹⁸ cm ⁻³ or more.

In still another embodiment of the first aspect, it is preferable that the doping concentration of the first collector layer is set to 5 × 10 ¹⁸ cm ⁻³ or more.

[0020] In still another embodiment of the first mode, it is preferable that the thickness of the first collector layer is formed to be 40 nm or more.

[0021] In still another embodiment of the first mode, the thickness of the first collector layer may be formed to be approximately 50 nm.

[0022] In still another aspect of the first aspect, the emitter region may include a layer having a band gap wider than a band gap of a layer of the base region adjacent to the emitter region.

In still another aspect of the first aspect, the layer of the emitter region may be made of InGaP, and the layer of the base region adjacent to the emitter region may be made of GaAs.

[0024] In still another aspect of the first aspect, the collector region includes a second collector layer adjacent to the first collector layer and having a lower doping concentration than the doping concentration of the first collector layer. May be.

[0025] In still another aspect of the first aspect, the second collector layer may be made of GaAs.

According to a second aspect of the present invention, there is provided a semiconductor IC including the bipolar transistor according to the present invention as a circuit element. A bipolar transistor incorporated in a semiconductor IC has an emitter region, a base region adjacent to the emitter region, and a collector region adjacent to the base region. It has a first collector layer that is heavily doped to move to the region.

[0027] In one embodiment of the second mode, the first collector layer is heavily doped so that the bipolar transistor exhibits a negative resistance at room temperature. The semiconductor IC according to the second embodiment can include a bipolar transistor that exhibits negative resistance at room temperature.

In another aspect of the second aspect, the first aspect
The collector layer is provided adjacent to the base region.

[0029] In still another mode of the second mode, the first collector layer may have a band gap wider than a band gap of a layer of the base region adjacent to the first collector layer.

[0030] In still another aspect of the second mode, the first collector layer may be formed of the same semiconductor material as a layer of the base region adjacent to the first collector layer.

The above summary of the present invention does not enumerate all the necessary features of the present invention, and sub-combinations of these features can also constitute the present invention.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described through embodiments of the present invention. However, the following embodiments do not limit the invention according to the claims, and are described in the embodiments. Not all combinations of features are essential to the solution of the invention.

FIG. 1 shows a basic structure of a transistor 100 according to a first embodiment of the present invention. The transistor 100 according to the first embodiment includes an emitter region 1
0, a base region 20 and a collector region 50.
The collector region 50 has a first collector layer 30 and a second collector layer 40. In this embodiment, the bipolar transistor 100 has n
It is configured as a pn type.

The emitter region 10 is made of InGaP,
An n-type impurity is doped at a doping concentration of 1 × 10 ¹⁸ cm ⁻³ . The base region 20 is made of GaAs, and is doped with a p-type impurity at a doping concentration of 5 × 10 ¹⁹ cm ⁻³ .
The first collector layer 30 is made of InGaP, and is doped with an n-type impurity at a doping concentration of 1 × 10 ¹⁸ cm ⁻³ . In the present invention, the first collector layer 30 is highly doped so that electrons in the collector region 50 move to the base region 20 by a tunnel effect at room temperature. Here, the room temperature means the temperature in the room, and usually 1 to
A temperature in the range of 35 ° C is applied. The first collector layer 30 is provided adjacent to the base region 20. The second collector layer 40 is made of GaAs, and is doped with an n-type impurity at a doping concentration of 3 × 10 ¹⁶ cm ⁻³ . Second collector layer 4
0 is adjacent to the first collector layer 30 and has a lower doping concentration than that of the first collector layer.

Emitter region 10 and first collector layer 3
The band gap of the material InGaP of 0 is wider than the band gap of the material GaAs of the base region 20. As shown in FIG. 1, this transistor 100 is grounded at the emitter. The pn junction between the base and the emitter is forward biased, and the pn junction between the base and the collector is reverse biased.

FIG. 2 is a band diagram of the transistor 100 according to the first embodiment. When an n-type semiconductor having a wide band gap and a p-type semiconductor having a narrow band gap are joined, a step occurs at the bottom of the conduction band due to a difference in electron affinity at the junction interface. First, considering the junction between the emitter and the base, in the present embodiment, a step ΔEc generated at the time of heterojunction between the emitter region 10 and the base region 20 is used as an electron launching table, so that the electron flow is reduced. Can be accelerated. The quick passage of electrons through the base region 20 can reduce the number of electrons that recombine with holes in the base region 20 and are lost. Further, regarding the holes in the base region 20, since the movement of the holes from the base region 20 to the emitter region 10 is hindered by the step ΔEc, the number of holes flowing into the emitter region 10 and disappearing can be reduced. . As described above, by hetero-junction between the emitter region 10 and the base region 20, the number of electrons and holes that disappear at the interface between the base and the emitter can be reduced. Therefore, a larger collector current can be obtained, and the current gain increases.

The current gain of the transistor 100 is
Varies with frequency. The current gain cutoff frequency ft, which is the limit frequency at which the gain of the transistor 100 is lost, is expressed as a function of the speed of electrons.
ft will improve. When a heterojunction is formed between the emitter region 10 and the base region 20, the speed of electrons is increased, so that ft is also improved.

Next, the junction between the base and the collector will be considered. The band gap of the material InGaP of the first collector layer 30 is wider than the band gap of the material GaAs of the base region 20. The doping concentration of the first collector layer 30 is higher than the doping concentration of the second collector layer 40.
By increasing the doping concentration of the base region 20 and the first collector layer 30, the thickness of the first collector layer 30 in the band diagram becomes very narrow. The doping concentration of the first collector layer 30 is desirably 1 × 10 ¹⁸ cm ⁻³ or more. When the voltage between the collector and the emitter is increased, the second collector layer 4 in the band diagram of FIG.
The level of 0 gradually moves downward. with this,
The thickness of the first collector layer 30 also decreases. As the thickness of the first collector layer 30 existing at the contact interface with the base region 20 decreases, electrons pass through the first collector layer 30 and move to the valence band of the base region 20. . This effect is called a tunnel effect.

FIG. 3 is a band diagram for explaining a tunnel effect in which electrons pass through the first collector layer 30.
In the drawing, the level indicated by the horizontal dotted line indicates the Fermi level of each layer.

FIG. 3A shows a state of a band when a voltage Vp is applied between a pn junction which is a junction between the base region 20 and the collector region 50. At this time, the electrons move from the base region 20 to the collector region 50 in the conduction band.

FIG. 3B shows a band state when a voltage Vv is applied between the junction between the base region 20 and the collector region 50. Referring to FIG. 3A, Vv is larger than Vp (Vv> Vp). When the voltage is set to Vv, the thickness of the first collector layer 30 becomes very narrow in the band diagram. As a result, the electrons pass through the first collector layer 30 and tunnel to the base region 20. Therefore, in the band state shown in FIG. 3B, the voltage-current characteristics lose linearity, and negative resistance occurs.

FIG. 3C shows the state of the band when the voltage applied between the junction between the base region 20 and the collector region 50 is further increased. In this example, a voltage Vpp (> Vv) is applied between the pn junctions. In the band state shown in FIG. 3C, when the electrons in the base region 20 move to the collector region 50, they collide with the atoms and strike out the electrons, and the struck out electrons collide with other atoms. A phenomenon occurs in which the electrons collide and knock out electrons, and a large amount of electrons flow into the collector region 50. This phenomenon is called electron avalanche breakdown. Since the amount of electrons flowing into the collector region 50 due to the avalanche breakdown is larger than the amount of electrons lost from the collector region 50 due to the tunnel effect, the amount of electrons supplied to the collector region 50 as a whole increases.

FIG. 4 shows voltage-current characteristics when the structure for producing the tunnel effect shown in FIG. 3 is made of a semiconductor. In FIG. 4, states a, b, and c correspond to FIGS. 3 (a), (b)
And (c) show the states shown. Between voltage 0 and Vp, the current monotonously increases, and the voltage-current characteristics have linearity. In state a, the current reaches the peak current Ip. Between the voltages Vp and Vv, the current decreases as the voltage increases, and negative resistance occurs.
This phenomenon is due to a tunnel effect in which electrons existing in the second collector layer 40 are injected back into the base region 20 and recombine with holes in the base region 20. Until the voltage reaches Vv, the collector current continues to decrease. When the voltage exceeds Vv, the amount of electrons injected into the second collector layer 40 due to the avalanche breakdown increases again, and the collector current increases again.

One load line 60 is shown in this voltage-current characteristic curve.
, A plurality of intersections (ie, stable points) occur. Utilizing the fact that there are a plurality of stable points, it is possible to reduce the number of elements such as a logic circuit or a divided cycle.

FIG. 5 shows a basic structure of a transistor 100 according to a second embodiment of the present invention. The transistor 100 according to the first embodiment includes an emitter region 1
0, a base region 20 and a collector region 50.
The collector region 50 has a first collector layer 30 and a second collector layer 40. In this embodiment, the bipolar transistor 100 has n
It is configured as a pn type.

The emitter region 10 is made of InGaP,
An n-type impurity is doped at a doping concentration of 1 × 10 ¹⁸ cm ⁻³ . The base region 20 is made of GaAs, and is doped with a p-type impurity at a doping concentration of 5 × 10 ¹⁹ cm ⁻³ .
The first collector layer 30 is made of GaAs, and is doped with an n-type impurity at a doping concentration of 1 × 10 ¹⁸ cm ⁻³ . In the present invention, the first collector layer 30 is doped at a high concentration such that electrons in the collector region 50 move to the base region 20 by a tunnel effect at room temperature. First
The collector layer 30 is provided adjacent to the base region 20. The second collector layer 40 is made of GaAs, and is doped with an n-type impurity at a doping concentration of 3 × 10 ¹⁶ cm ⁻³ . The second collector layer 40 is adjacent to the first collector layer 30 and has a lower doping concentration than the first collector layer. As shown in FIG. 1, this transistor 100 has an emitter grounded,
The pn junction between the emitters is forward biased, and the pn junction between the base and collector is reverse biased.

As compared with the transistor 100 according to the first embodiment shown in FIG. 1, in the second embodiment, the first collector layer 30 is formed of the same semiconductor material as the base region 20. However, the first collector layer 30 in the second embodiment is heavily doped with n-type impurities, as in the first embodiment.

The base region 20 and the first collector layer 30 are
In the transistor 100 formed of one material, FIG.
Effect and avalanche breakdown described in relation to
Occurs. As shown in FIG. 4, the voltage-current characteristics are negative.
In order to generate resistance, the first collector
The ping density may be set to a high density. Base area 2
0 and the first collector layer 30 form a homojunction,
Doping concentration is 1 × 10 to obtain negative resistance¹⁸cm^-3
It is desirable to set the above, and furthermore, 5 × 10 ¹⁸cm^-3
It is desirable to set above.

FIG. 6 shows one example of the transistor 100 which is prototyped by incorporating the structure of the first embodiment of the present invention. The transistor 100 has a substrate made of GaAs. In this transistor 100, the emitter region 10 includes an n-type GaAs layer (thickness 250 nm, doping concentration 5 × 10 ¹⁸ cm ⁻³ ) and an n-type InGaP layer (thickness 100 nm, doping concentration 1 × 10 ¹⁸ cm ⁻³ ). Including. Also, base region 2
0 is a p-type GaAs layer (thickness 50 nm, doping concentration 5 × 10 ¹⁹ cm)
^-3 ), and the collector region 50 has an n-type InGaP layer (thickness: 50 n).
m, doping concentration 1 × 10 ¹⁸ cm ^-3 ), n-type GaAs layer (thickness 250n
m, doping concentration 3 × 10 ¹⁶ cm ^-3 ) and n-type GaAs layer (thickness 500
nm, doping concentration of 1 × 10 ¹⁹ cm ⁻³ ). Referring to FIG. 1, first collector layer 30 is formed in collector region 50.
The second collector layer 40 corresponds to an n-type GaAs layer.
Corresponds to a layer. In another embodiment, the transistor may include layers other than those shown.

The doping concentration of the n-type InGaP layer in the collector region 50 is as high as 1 × 10 ¹⁸ cm ⁻³ . The band gap of the n-type InGaP layer included in the collector region 50 is wider than the band gap of the p-type GaAs layer of the base region 20. In a conventional mere heterojunction bipolar transistor having no negative resistance, the collector region 50 is formed of a highly doped n-type InGaP 1 × 10 ¹⁸ cm ^−3.
The p-type GaAs layer having no layer and serving as a base was directly adjacent to the n-type layer of the collector region 50 doped to about 3 × 10 ¹⁶ cm ⁻³ . However, in the present invention, the transistor 100 having a negative resistance at room temperature can be formed by forming a high-concentration n-type InGaP layer in the collector region 50. Therefore, this transistor 1
No. 00 is a configuration in which the element length is short with respect to the negative resistance, and the same effect as that obtained by adding a tunnel diode to a transistor can be obtained.

In the embodiment shown in FIG.
The first collector layer 30 adjacent to the base region 20 is made of InGaP
However, in another embodiment, the base region 20 may be formed of GaAs, which is the same semiconductor material. At this time, in order to generate a transistor having a negative resistance, it is necessary to set a high doping concentration of the first collector layer. Doping concentration of the first collector layer, 1 × is preferably set to 10 ^{1 8} cm ^-3 or more, preferably be further set to 5 × 10 ¹⁸ cm ^-3 or more.

The effect of the present invention is that the base region 20 and the first collector layer 30 are formed not only by the combination of GaAs and InGaP but also by, for example, GaAs and AlGaAs, InP and InGaAs, and Si and SiGe.
It can be obtained even when formed of a material obtained by combining the above. Further, as described above, even when the base region 20 and the first collector layer 30 are formed of the same material, the effects of the present invention can be obtained. That is, by suitably adjusting the doping concentration of the first collector layer 30 adjacent to the base region 20 to 1 × 10 ¹⁸ cm ⁻³ or more,
The excellent effects of the present invention can be obtained.

N-type first collector layer 3 in collector region 50
The doping concentration of 0 is preferably set high,
Specifically, it is desirable that it be 1 × 10 ¹⁸ cm ⁻³ or more. Further, the starting voltage Vp of the negative resistance changes according to the doping amount of the first collector layer 30. If the doping concentration of the first collector layer 30 is high, the starting voltage Vp of the negative resistance becomes low, and if the doping concentration is low, the starting voltage Vp becomes high. Further, the thickness of the first collector layer 30 for obtaining a desired starting voltage Vp in the voltage-current characteristics of the transistor 100 depends on the doping concentration. First collector layer 3
The thickness of 0 is preferably not less than 40 nm, and is 50 nm in the embodiment shown in FIG. In order to enable high-speed operation of the transistor 100, it is preferable that the base region be as thin as possible. The present transistor structure has a shorter element length than any of the conventional transistor elements having negative resistance, and enables high-frequency operation at room temperature at a frequency higher than 200 GHz. Collector area 5
When changing the thickness of the first collector layer 30 of 0, it is desirable to adjust the doping concentration.

Further, this transistor structure not only enables high-frequency operation, but also has a large current gain due to the reduced element length and parasitic resistance.
It is also possible to realize a dividing cycle and an amplifier with one transistor.

FIG. 7 shows experimental results of the voltage-current characteristics of the collector current Ic and the voltage Vce applied between the collector and the emitter of the transistor structure shown in FIG. 6 when the base current Ib is increased by 500 μA. This voltage-current characteristic was measured at room temperature (about 25 ° C.). Experiments have shown that the transistor structure of the present invention has a large negative resistance at room temperature.

FIG. 8 shows a semiconductor IC (integrated circuit) including the bipolar transistor 100 according to the present invention as a circuit element. This semiconductor IC has a chip on which the bipolar transistor 100 according to the present invention is formed. In FIG. 8, the chip is a pin grid array (P
GA) Although it is packaged, it may be packaged by other methods.

By incorporating the transistor 100 into a semiconductor IC, it is possible to achieve higher performance and more functions of the semiconductor IC. For example, the transistor structure
Since a plurality of stable points can be obtained with one load by the negative resistance characteristic, the number of circuit elements such as a logic circuit mounted on the semiconductor IC for realizing a certain function can be reduced.
Further, since the present transistor has a large current gain, it can be mounted on a semiconductor IC as a dividing cycle and an amplifier.

As apparent from the above description, according to the present invention, a transistor having a negative resistance at room temperature can be provided. As described above, the present invention has been described using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is apparent to those skilled in the art that various changes or improvements can be made to the above embodiment. It is apparent from the description of the appended claims that embodiments with such modifications or improvements are also included in the technical scope of the present invention.

[0059]

According to the present invention, a bipolar transistor having a large negative resistance at room temperature can be obtained.
Further, according to the present invention, since the element length is short, a bipolar transistor operable at a very high frequency can be obtained. Further, according to the present invention, a bipolar transistor having a very large current gain can be obtained.

[Brief description of the drawings]

FIG. 1 shows a basic structure of a transistor according to a first embodiment of the present invention.

FIG. 2 is a band diagram of a transistor in the first embodiment.

3 is a band diagram for explaining a tunnel effect in which electrons pass through a first collector layer 30. FIG.

FIG. 4 shows a voltage-current characteristic when the structure that causes the tunnel effect shown in FIG. 3 is made of a semiconductor.

FIG. 5 shows a basic structure of a transistor according to a second embodiment of the present invention.

FIG. 6 illustrates one embodiment of a transistor incorporating the structure of the present invention.

FIG. 7 shows a collector structure of the transistor structure shown in FIG.
The voltage Vce applied between the emitters and the collector current Ic
Shows the experimental results.

FIG. 8 shows a semiconductor IC including a bipolar transistor 100 as a circuit element.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Emitter, 20 ... Base, 30 ... 1st collector layer, 40 ... 2nd collector layer, 50 ...
Collector region, 60: load line, 70: semiconductor I
C, 100 ... transistor

Claims (20)

[Claims] 1. A bipolar transistor having an emitter region, a base region adjacent to the emitter region, and a collector region adjacent to the base region, wherein the collector region has an electron in the collector region formed by a tunnel effect. A bipolar transistor comprising a first collector layer that is heavily doped to move to a region. 2. The bipolar transistor according to claim 1, wherein the first collector layer is heavily doped so that the bipolar transistor exhibits a negative resistance at room temperature. 3. The bipolar transistor according to claim 1, wherein the first collector layer is provided adjacent to the base region. 4. The bipolar transistor according to claim 3, wherein the first collector layer has a band gap wider than a band gap of a layer of the base region adjacent to the first collector layer. 5. The bipolar transistor according to claim 4, wherein the base region has a layer made of GaAs, and the first collector layer is made of InGaP. 6. The bipolar transistor according to claim 3, wherein the first collector layer is formed of the same semiconductor material as a layer of the base region adjacent to the first collector layer. 7. The bipolar transistor according to claim 6, wherein said base region has a layer made of GaAs, and said first collector layer is made of GaAs. 8. The method according to claim 1, wherein the doping concentration of the first collector layer is 1 × 10 ¹⁸ cm ⁻³ or more.
8. The bipolar transistor according to any one of items 1 to 7, 9. The method according to claim 8, wherein a doping concentration of the first collector layer is 5 × 10 ¹⁸ cm ⁻³ or more.
4. The bipolar transistor according to claim 1. 10. The bipolar transistor according to claim 1, wherein the thickness of the first collector layer is 40 nm or more. 11. The first collector layer has a thickness of about 50.
11. The bipolar transistor according to claim 10, wherein the thickness is in nm. 12. The device according to claim 1, wherein the emitter region includes a layer having a band gap wider than a band gap of a layer of the base region adjacent to the emitter region. Bipolar transistor. 13. The method according to claim 13, wherein said layer of said emitter region is made of InGaP.
13. The bipolar transistor according to claim 12, wherein the layer of the base region adjacent to the emitter region is formed of GaAs. 14. The method of claim 5, wherein the collector region includes a second collector layer adjacent to the first collector layer and having a lower doping concentration than the first collector layer. A bipolar transistor as described. 15. The bipolar transistor according to claim 14, wherein said second collector layer is made of GaAs. 16. A semiconductor IC including a bipolar transistor as a circuit element, wherein the bipolar transistor has an emitter region, a base region adjacent to the emitter region, and a collector region adjacent to the base region. A semiconductor IC wherein the region has a first collector layer that is heavily doped so that electrons in the collector region move to the base region by tunneling. 17. The semiconductor IC according to claim 16, wherein the first collector layer is heavily doped so that the bipolar transistor exhibits a negative resistance at room temperature. 18. The device according to claim 1, wherein the first collector layer is provided adjacent to the base region.
18. The semiconductor IC according to 6 or 17. 19. The semiconductor IC according to claim 18, wherein the first collector layer has a band gap wider than a band gap of a layer of the base region adjacent to the first collector layer. 20. The semiconductor IC according to claim 18, wherein said first collector layer is formed of the same semiconductor material as a layer of said base region adjacent to said first collector layer.