JP2000101870A - Digital signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a sense of sharpness of an edge part after number of pixels of a video signal is converted. SOLUTION: An input video signal from an input terminal 101 is respectively given to an interpolation filter 102 and a control signal generating circuit 103. The control signal generating circuit 103 generates a control signal, which is given to a phase control circuit 104. The phase control circuit 104 controls an interpolation phase of the interpolation filter 102 based on the control signal. The interpolation filter 102 converts number of pixels of the received video signal and the converted video signal is outputted from an output terminal 105. In the case that the control signal is generated from a high frequency component of the received video signal and the interpolation filter interpolates pixels in this way, the control signal is used to control a phase of the interpolation pixels to enhance a sense of sharpness of an edge part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit for converting the number of pixels of a video signal.

[0002]

2. Description of the Related Art As means for converting the number of pixels of a video signal, interpolation is generally performed by an interpolation filter. FIG. 20 shows an example of this conversion. The video signal input from the input terminal 201 is input to the interpolation filter 202. The interpolation filter 202 interpolates the pixels to a phase corresponding to the number of pixels to be converted, and obtains a video signal whose number of pixels has been converted from the output terminal 203.

FIG. 21 shows an example of the interpolation phase. FIG.
This is an example of converting the number of pixels to / 3 times. In the figure, ○ indicates the original pixel, and ● indicates the interpolation pixel. The output of the interpolation filter 202 is a video signal whose pixel number has been converted, and has a waveform indicated by a solid line in FIG.

When the number of pixels is increased by 8/3 as shown in FIG. 21, the expressible band is increased by 8/3 as shown in FIG. However, in the pixel number conversion by the interpolation filter 202, ● is an interpolation pixel, and can be expressed only up to the maximum band of the video signal before the pixel number conversion.
This is only ／ of the band after the pixel number conversion, and the sharpness of the edge part is lost.

[0005]

The above-described conventional means for converting the number of pixels of a video signal has a problem in that there is no sharpness in an edge portion.

SUMMARY OF THE INVENTION It is an object of the present invention to improve the sharpness of an edge portion after converting the number of pixels of a video signal.

[0007]

In order to solve the above-mentioned problems, a digital signal processing circuit according to the present invention comprises a means for interpolating pixels into an input video signal and converting the number of pixels, and a high frequency band for the input video signal. Means for generating a control signal from the signal;
Control means for controlling the phase of the interpolation pixel by the control signal.

With such a configuration, a control signal is generated from a high-frequency component of an input video signal, and when a pixel is interpolated by an interpolation filter, the phase of the interpolated pixel is controlled by the control signal, whereby the edge portion Improve sharpness.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit configuration diagram for describing an embodiment of the present invention. In FIG. 1, a video signal input from an input terminal 101 is input to an interpolation filter 102 and a control signal generation circuit 103, respectively. The control signal generation circuit 103 generates a control signal and inputs the control signal to the phase control circuit 104. The phase control circuit 104 controls the interpolation phase of the interpolation filter 102 based on the control signal. The interpolation filter 102 converts the number of pixels of the input video signal, and derives the converted video signal from the output terminal 105.

Here, the relationship between the control signal and the interpolation phase control will be described with reference to FIG. When the sign of the control signal is positive, the interpolation phase is later than the original phase, and the amount of correction for how much later is determined by the level of the control signal. When the sign of the control signal is negative, the interpolation phase is earlier than the original phase, and the correction amount of how far ahead is determined by the level of the control signal.

By controlling the interpolation phase of the interpolation filter 102 with such a control signal, the interpolated signal becomes as shown by the dotted line in FIG. 2, and the sharpness of the edge can be improved.

[0012]

FIG. 3 is a block diagram for explaining a first embodiment of the control signal generation circuit 103 in the embodiment of the present invention shown in FIG. In the figure, a signal input from an input terminal 301 is a first-order differentiator 302,
Input to the differentiator 303 respectively. Outputs of the primary and secondary differentiators 302 and 303 are input to first and second interpolation filters 304 and 305, respectively, and the number of pixels is converted so as to have the same number of pixels as the interpolation filter 102.

The output of the second interpolation filter 305 is input to a code detector 306. The output of the code detector 306 is
The signal is input to the sign inverter 307. In the sign inverter 307, when the output of the sign detector 306 detects a negative value, the first
When the sign of the output of the interpolation filter 304 is inverted and a positive value is detected, the output of the first interpolation filter 304 is output as it is.

FIG. 4 shows a waveform diagram of the control signal generation circuit 103. A primary differential signal and a secondary differential signal are extracted from the input video signal. When the secondary differential pixel number conversion signal is positive, the primary differential pixel number conversion signal is output as it is as a control signal, and a negative differential pixel signal is output. In the portion, a signal obtained by inverting the first derivative pixel number conversion signal is output as a control signal. As a result, the control signal becomes as illustrated, and the interpolation phase of the interpolation filter 102 is controlled based on the control signal.

FIG. 5 is a block diagram for explaining a second embodiment of the control signal generation circuit of FIG. In this embodiment, parts having the same functions as those in FIG. In FIG. 3, the signal obtained by converting the number of pixels of the primary differential signal is used as it is as a control signal. Therefore, when the level of the input video signal is low, the control signal is low. As described above, since the correction amount of the phase is determined by the level of the control signal, if the control signal is small, the improvement effect is small. Therefore, this embodiment is intended to improve the edge even when the level of the input video signal is low.

That is, the output from the sign inverter 307 is input to the level detector 501. The level detector 501 detects the level of the sign-inverted output, and outputs a control signal corresponding to the level. The level controller 502 controls the level of the sign inversion output according to the level detection output.

In this level control, as shown in FIG. 6, when the level of the input video signal is small and the sign-inverted output is small, the sign-inverted output is reduced to a level at which the effect of improving the edge is obtained as shown by the dotted line in FIG. Raise the level. By using the output of the level controller 502 as a control signal, the edge portion can be improved even when the level of the input video signal is low.

FIG. 7 is a block diagram for explaining a third embodiment of the control signal generation circuit of FIG. This embodiment also improves the edge portion when the level of the input video signal is low.

That is, the output from the second interpolation filter 305 is input to the zero cross point detector 701. The zero cross point detector 701 detects a point at which the sign of the second derivative pixel number conversion signal changes. In the control data output unit 702, when a point at which the sign is switched is detected by the 0 cross point detector 701, as shown in FIG. 8, the control data output unit 702 outputs control signal data in an arbitrary range around the point. Regardless of the level of the input video signal, this control data outputs control data at a level at which, for example, the effect of improving the rising and falling edges of the input video signal is obtained. The control data synthesizer 703 adds these output control data.

Regarding the addition of the control data, as shown in FIG. 9, when the control data is output at the rising and falling pixels of the input video signal having a close relationship, a portion where the control data overlaps appears. If the control data in the overlapping portion is added by the control data synthesizer 703, it can be canceled. The portion where the control data overlaps is a portion where the phase can change in either direction, and there is a possibility that interference may occur in this portion by performing the phase control.

When the control signal is not canceled as shown in FIG. 10, the phase is controlled as shown by the dotted line in the figure.
The vertex becomes a concave waveform, and the brightness level changes on the screen and appears as an obstruction. For this reason, by adding and canceling control data, phase control is not performed and occurrence of interference is suppressed. This control data synthesizer 70
By using the output of control signal No. 3 as the control signal, the edge portion can be improved even when the level of the input video signal is low.

As shown in FIG. 11, when the phase control is performed, the vicinity of the zero crossing point of the second derivative pixel number conversion signal becomes zero.
Pixels whose phase is controlled before and after the cross point may be shifted, and jaggedness may be conspicuous by oblique lines or the like. In this embodiment, the shift of the zero cross point can be prevented by the output value of the control data. In order to prevent the pixels before and after the zero cross point from shifting, the phase may be controlled as shown in FIG. This phase control width is proportional to the absolute value of the pixel before and after the zero cross point. Therefore, the control data may be output so as to have the same ratio as the ratio of the absolute values of the pixels before and after the zero cross point.

FIG. 13 is a block diagram showing the embodiment of FIG.
FIG. 13 is a block diagram for explaining a fourth embodiment of the control signal generation circuit provided with a means for preventing a shift of a cross point. That is, the input video signal is supplied to the third interpolation filter 13.
01, and the number of pixels is converted so as to have the same number of pixels as the interpolation filter 102 of FIG. Interpolation filter 130
The output of 1 is input to a pixel level ratio detector 1302. When the detection signal of the 0 cross point is input from the 0 cross point detector 701, the pixel level ratio detector 1302 outputs the ratio of the level of the pixel before and after the detection signal. The pixel level ratio output is input to the control data output unit 702, and the control data output means outputs control data before and after the 0 cross point at a ratio equal to the pixel level ratio. In this way, the shift of the zero cross point can be prevented.

However, in this embodiment, means for converting the number of pixels of the input video signal is required, and the circuit scale becomes large. For this reason, the same control can be performed by using the already existing second derivative pixel number conversion signal. The level ratio of the input video signal before and after the zero cross point is almost the same as the level ratio of the second derivative pixel number conversion signal. Therefore, instead of the output of the pixel number conversion means of the input video signal, the pixel number conversion output of the second derivative is used as the pixel level ratio.

This is shown in the block diagram of FIG. 14 as a fifth embodiment of the control signal generation circuit. The difference between this embodiment and FIG. 13 is that the second derivative pixel number conversion output from the interpolation filter 305 is input to the pixel level ratio detector 1302, whereby the control data output unit 702 outputs control data. .

FIG. 15 is a block diagram for explaining a sixth embodiment of the control signal generation circuit. The secondary differentiator 303 used in the control signal generation circuit 103 is means for detecting a high frequency component. However, a high-frequency component having a small level may be noise, and if this noise component is detected by a second-order differentiator to generate a control signal,
It performs wrong phase control and appears as a disturbance. In addition, as described above, in the vicinity of the zero-cross point of the second derivative pixel number conversion signal, the phases of the pixels around the zero-cross point may be shifted due to the phase control. This embodiment is to prevent these.

The output of the second interpolation filter 305 is input to a level determiner 1501 to determine a level. The level determiner 1501 determines whether the output of the second interpolation filter is lower than a certain level. The determination signal from the level determiner is input to the level controller 1502. If it is determined that the output of the second interpolation filter is lower than a certain level, there is a possibility that the output is near noise or a zero crossing point. To control. This level controller 1
The output of 502 is a control signal. FIG. 16 shows a waveform diagram of the control signal.

By doing so, it is possible to prevent a phase control error due to noise and a phase shift around the zero cross point.

In this embodiment, the same effect can be obtained by performing the level judgment after the output of the second interpolation filter 305 of each of the embodiments described so far and performing the level control on the final output.

FIG. 17 is a block diagram for explaining a seventh embodiment of the control signal generation circuit. This embodiment is for preventing the diagonal line from being jagged. Therefore, a component extracted as a control signal through the vertical LPF 1701 that allows only the low frequency band of the vertical signal of the video signal to pass through the output of the sign inverter 307 is used. It differs from the embodiment of FIG. In addition,
The same functional parts as those in the embodiment of FIG.
The description is omitted.

As shown in FIG. 18, the signal level of the diagonal line changes for each line, and the shift of the control signal tends to occur depending on the line. If the control signal is shifted between the lines, the luminance difference after the phase control becomes large as shown in FIG. To prevent this, a vertical LPF is applied to the control signal to reduce the deviation of the control signal from the upper and lower lines.

The output from the sign inverter 307 is a vertical LPF
The difference between the lines of the sign-inverted output is reduced by inputting the signal to an input 1701 and extracting a vertical low-frequency component. By using this as a control signal, it is possible to suppress jaggedness in oblique lines.

In this embodiment, a similar effect can be obtained by applying a vertical LPF to the final output of each embodiment described above.

[0034]

As described above, in the digital signal processing circuit according to the present invention, the phase of the interpolated pixel is controlled by the control signal generated from the high-frequency signal of the input video signal, whereby the number of pixels converted is converted to the number of pixels. The sharpness of the edge portion can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention;

FIG. 2 is an explanatory diagram for explaining the operation of FIG. 1;

FIG. 3 is a block diagram for explaining a first embodiment of the control signal generation circuit of FIG. 1;

FIG. 4 is an explanatory diagram for describing the operation in FIG. 3;

FIG. 5 is a block diagram for explaining a second embodiment of the control signal generation circuit of FIG. 1;

FIG. 6 is an explanatory diagram for describing the operation in FIG. 5;

FIG. 7 is a block diagram for explaining a third embodiment of the control signal generation circuit of FIG. 1;

FIG. 8 is an explanatory diagram for explaining the operation of FIG. 7;

FIG. 9 is an explanatory diagram for describing the operation in FIG. 7;

FIG. 10 is an explanatory diagram for describing the operation in FIG. 7;

FIG. 11 is an explanatory diagram for explaining the operation of FIG. 7;

FIG. 12 is an explanatory diagram for explaining the operation in FIG. 7;

FIG. 13 is a block diagram for explaining a fourth embodiment of the control signal generation circuit of FIG. 1;

FIG. 14 is a block diagram for explaining a fifth embodiment of the control signal generation circuit of FIG. 1;

FIG. 15 is a block diagram for explaining a sixth embodiment of the control signal generation circuit of FIG. 1;

FIG. 16 is an explanatory diagram for describing the operation in FIG. 15;

FIG. 17 is a block diagram for explaining a seventh embodiment of the control signal generation circuit of FIG. 1;

FIG. 18 is an explanatory diagram for explaining FIG. 17;

FIG. 19 is an explanatory diagram for describing FIG. 17;

FIG. 20 is a block diagram for explaining conventional pixel number conversion of a video signal.

FIG. 21 is an explanatory diagram for describing an example of converting the number of pixels in FIG. 20;

FIG. 22 is an explanatory diagram for describing a problem of converting the number of pixels in FIG. 20;

[Explanation of symbols]

102: interpolation filter, 103: control signal generation circuit, 1
04 ... phase control circuit, 302 ... first-order differentiator, 303 ... 2
Second order differentiator, 304 ... first interpolation filter, 305 ... second
Interpolation filter, 306: sign detector, 307: sign inverter, 501: level detector, 502: level controller,
701: 0 cross point detector, 702: control data output device, 703: control data synthesizer, 1301: interpolation filter, 1302: pixel level ratio detector, 1501: level determiner, 1502: level controller

Claims (9)

[Claims] 1. A means for interpolating pixels into an input video signal to convert the number of pixels, a means for generating a control signal from a high-frequency signal of the input video signal, and a control for controlling a phase of an interpolated pixel by the control signal And a digital signal processing circuit. 2. The control signal generating means includes: means for extracting a primary differential signal of the input video signal; means for extracting a secondary differential signal; and a first for converting the number of pixels of the primary differential signal. Conversion means; second conversion means for converting the number of pixels of the secondary differential signal; and means for inverting the sign of the output of the first conversion means by the sign of the output of the second conversion means. The digital signal processing circuit according to claim 1, wherein: 3. A control signal generating means, comprising: means for extracting a primary differential signal of the input video signal; means for extracting a secondary differential signal; and a first for converting the number of pixels of the primary differential signal. Converting means; second converting means for converting the number of pixels of the secondary differential signal; means for inverting the sign of the output of the first converting means by the sign of the output of the second converting means; 2. The digital device according to claim 1, further comprising a level detecting means for detecting an output level of the means, and a level control means for controlling a level of an output of the inverting means in accordance with an output of the level detecting means. Signal processing circuit. 4. A control signal generation unit, a unit for extracting a second derivative signal of the input video signal, a unit for converting the number of pixels of the second derivative signal, and detecting a change of a sign of an output of the conversion unit. 2. The digital device according to claim 1, further comprising: means for outputting data having an arbitrary characteristic in an arbitrary range before and after the code switching, and synthesizing means for synthesizing the data output. Signal processing circuit. 5. A control signal generating unit, a unit for extracting a secondary differential signal of the input video signal, a first converting unit for converting the number of pixels of the secondary differential signal, and an output of the first converting unit. Means for detecting a change in the sign of the second video signal; second conversion means for converting the number of pixels of the input video signal; and means for detecting the ratio of the level of the output of the second conversion means before and after the change of the code. 2. The apparatus according to claim 1, further comprising: means for outputting data having a ratio equal to the ratio detection output in an arbitrary range before and after the code switching, and combining means for combining the data outputs. Digital signal processing circuit. 6. A control signal generating unit, a unit for extracting a secondary differential signal of the input video signal, a converting unit for converting the number of pixels of the secondary differential signal, and detecting a change of a sign of an output of the converting unit. Means for detecting the ratio of the level of the output of the conversion means before and after the switching of the code, and means for outputting data having the same ratio as the ratio detection output in an arbitrary range before and after the switching of the code. 2. The digital signal processing circuit according to claim 1, further comprising a synthesizing means for synthesizing the data output. 7. The digital signal processing circuit according to claim 2, wherein the control signal generating means reduces the level of the control signal when the output of the second derivative signal is small. 8. The control signal generating means according to claim 2, further comprising means for extracting a vertical low frequency component of the control signal, and using the vertical low frequency output as a control signal. 3. A digital signal processing circuit according to claim 1. 9. The control means shifts the phase of an interpolation pixel backward according to the magnitude of the control signal when the control signal has a positive value, and shifts the control signal when the control signal has a negative value. 2. The digital signal processing circuit according to claim 1, wherein the phase of the interpolated pixel is shifted forward according to the size of.