JP2000101644A - Means and method for distributing line load - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically distribute the load of communication between a base station device and a host device corresponding to this base station device to plural communication lines provided between these base station device and host device among these plural communication lines. SOLUTION: Inside a base station device 2, line terminating parts are provided for respectively terminating respective communication lines, a ring counter- shaped circuit is constituted by cyclically serially connecting an arbitration circuit, which outputs a signal expressing the reception right of the relevant line terminating part, to all the line terminating parts. The line terminating part having the logical '1' of the signal expressing the reception right in this ring counter-shaped circuit sends one packet from the base station device to a host device 11. When this one packet is completely sent out, the signal expressing the reception right in the ring counter-shaped circuit is shifted by one step so that the line load can be distributed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a line load distribution means and a line load distribution method. More specifically, in a system in which a plurality of lines are prepared for communication between a base station device for mobile communication and its higher-level device and communication is possible using any of the lines, A mobile station that is a transmission source of a transmission to a device (generally, a plurality of mobile stations exist for one base station) can perform transmission without being aware of which of a plurality of lines is used. The present invention relates to a line load distribution means and a line load distribution method in which traffic load is automatically distributed to a plurality of lines.

[0002]

2. Description of the Related Art As prior art of the present invention, Japanese Patent No.
No. 16431, “Packet communication system and device for load distribution” (JP-A-7-303114). In this prior art, when the congestion of the line is detected on the receiving side, the congestion state is notified to the transmission source, and the transmission source is controlled to use another line, or the transmission is temporarily stopped. Control. For this reason, the transmission source has a problem that the line is congested, and the packet data (assuming the ATM: asynchronous transmission mode) transmitted while the congestion state is notified from the receiving side is discarded. Also, as a method of distributing the load of the line, each time packet data is transmitted, the utilization rate of each line is calculated to determine which line to use, so packet data to be transmitted is generated. Since the above-described processing is performed by software or the like until the data is actually transmitted, there is a problem that processing time is required and the throughput of the transmission capability is reduced.

[0003]

As described above, in the line load distribution means according to the prior art, the packet data transmitted while the congestion state is notified from the receiving side is discarded or the throughput of the transmission capacity is reduced. There were problems such as lowering.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and a line load distribution means capable of automatically distributing the load on a line without being conscious of which line the transmission source uses. And a line load distribution method.

[0005]

According to the present invention, in a base station apparatus, a plurality of units of units 1 to N serving as a transmission source of a packet corresponding to the transmission of each mobile station and each of the plurality of lines are terminated. Each of the plurality of units and the plurality of line terminating units are connected in parallel to a common packet communication path, and among the plurality of line terminating units, the line terminating unit in which the line is not in a congested state is included. Is controlled by an arbitration circuit provided in each line termination unit so as to cyclically acquire the reception right. An arbitrary unit in each of the plurality of units transmits a packet to a packet communication path when there is a packet to be transmitted, without regard to which line the packet is transmitted, as long as the packet communication path is free. . Packets on the packet communication path are input to all the line terminating units, but only the line terminating unit that has acquired the reception right takes in the packet and writes it in the receiving buffer. When the writing is completed, the line termination unit transfers the reception right, and the next line termination unit acquires the reception right. The packets written in the reception buffer are sequentially read and transmitted on the line. The line terminating unit relinquishes the right to receive. The line load is automatically distributed by the above method.

That is, a plurality of communication lines are provided between a base station apparatus and a host apparatus for the base station apparatus.
In the case where the base station apparatus and the higher-level apparatus communicate via the plurality of communication lines, the line load distribution method of the present invention for distributing a load to the plurality of communication lines includes the following steps. Each line termination unit for terminating each line of the plurality of communication lines, a plurality of units performing communication between the base station apparatus and the higher-level device, and all the line termination units and all the units are mutually connected. A step of providing packet communication paths connected in parallel, a arbitration circuit for outputting a signal representing the reception right of the line termination unit in each line termination unit, and a ring counter-like circuit which is cascaded cyclically for all line termination units. In this ring counter-like circuit, a signal representing the reception right of one line termination is set to logic "1", and a signal representing the reception right of all other line terminations is set to logic "0". First Converting a packet from an arbitrary one of all units onto a packet communication path, and transmitting a packet on the packet communication path to a line termination unit whose reception right signal is logic "1". The step of outputting a write enable signal to be written to the receive buffer of the unit, and after completing the writing by the write enable signal, shifting the signal of logic "1" representing the receive right to the next stage of the ring counter circuit A shift step, a step of reading out the signals in the reception buffer of the line termination unit in the order of writing, and transmitting the signals to the line.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, reference numeral 12 denotes a base station device of a mobile communication system, and reference numeral 11 denotes a base station device 1.
2 shows a higher-level device for 2. Multiple mobile stations (not shown)
Communicates with a mobile station belonging to another base station apparatus (not shown) from the base station apparatus 12 via the higher apparatus 11 (for example, a public telephone exchange).
A plurality of communication paths 14 (a plurality of lines) are provided between the communication apparatus 1 and the communication apparatus 1, so that communication with the host device 11 can be performed using any one of the plurality of communication paths 14. It is equipped with.

In the base station apparatus 12, each line terminating section (in the embodiment shown in FIG. 1, the line terminating section 1 (reference number 15), the line terminating section 2 (reference number 16), and the line terminating section 3 (in the embodiment shown in FIG. 1). Reference numeral 17) and a line terminating unit 4 (reference numeral 18) are provided, and a unit (un) for converting the communication content of the mobile station belonging to the base station apparatus 12 into a packet form and transmitting it to the communication path 14 (un
it) is N units (reference numerals 101, 102, 103,...)
.10N). All the line terminating units and all the units are connected to the packet communication path 13 in parallel.

Each of the line termination units 1 to 4 (reference numerals 15 to 18) has the same configuration. FIG. 2 is a block diagram showing the configuration of an arbitrary line termination unit 21. Reference numeral 22 denotes a line transmission / reception unit, reference numeral 24 denotes a packet transmission / reception unit, and reference numeral 23 denotes a CP which controls the line transmission / reception unit 22 and the packet transmission / reception unit 24.
U. The symbol RX between the line transmitting / receiving unit 22 and the packet transmitting / receiving unit 24 indicates a receiving unit including a receiving buffer, and the symbol TX indicates a transmitting unit including a transmitting buffer. Reference numeral 25 indicates a matching circuit,
Reference numeral 26 denotes an arbitration circuit, and reference numeral 13 denotes the same reference numeral 13 as in FIG.
This is a packet communication path indicated by. Communication between the units 101 to 10N of the base station apparatus and the higher-level apparatus 11 is performed in an ATM (Asynchronous Transfer Mode) of packet transmission, and the format of the packet is a fixed-length header (header) section 31 as shown in FIG. It is composed of a variable length information section 32, and a destination (destination) address is entered in the header section 31.

As a communication protocol between the line terminating unit 21 and the higher-level device, for example, X.264 of ITU-T recommendation is used. 25
LAP B (Link Access Protocol Balanced) is used. The header unit 31 uses any data in the base station device 12 as a destination address in the data from the higher-level device 11.
Are contained in the host device 11 in the ITU-T
X. of Recommendation. The data is edited into the format of the 25 LAP B protocol and transmitted to the line termination unit 21 for any one of the lines in the communication path 14.

[0011] In addition, the host device 11
Is transmitted on the packet communication path 13 without regard to which line of the communication path 14 to transmit. The packet on the packet communication path 13 is input to all the line terminating units 21, but is written only into the receiving buffer of the packet transmitting / receiving unit 24 of the line terminating unit 21 having the receiving right (described later). In other words, as for the logic of the output signal 2e from the arbitration circuit 26, only the output signal 2e from the adjustment circuit having the reception right is logic "1", and it is written that the logic of the signal 2e is "1". Permission signal 2d
Is one condition for output. When writing this,
The matching of the destination address is performed by the matching circuit 25, and the write enable signal 2d to be written to the reception buffer is logical only when the destination address is to be transmitted via the host device 11 and the logic of the signal 2e is "1". It becomes "1".

The packets written in the reception buffer (usually composed of a first-in-first-out (FIFO) memory) of the packet transmission / reception unit 24 are read out in the order of writing and passed through the TX of the line transmission / reception unit 22 to the higher order. The packet is transmitted to the device 11, but when the TX of the line transmitting / receiving unit 22 is congested or the RX of the packet transmitting / receiving unit 24 is congested, the reception buffer of the packet transmitting / receiving unit 24 overflows (ov
erflow). Then write another packet,
At the point where the reception buffer overflows, the RX (including the reception buffer) of the packet transmitting / receiving unit 24
sy) A signal (code 2c) is issued, and the arbitration circuit 26 relinquishes the reception right. Further, when the write permission signal 2d is generated and the writing is completed, the arbitration circuit 26 transfers the reception right to the circuit termination unit 21 in the next stage.

FIG. 7 is a block diagram showing a connection in the form of a ring counter formed by a cyclic cascade of arbitration circuits 26 in each of the line terminating units 15 to 18. Reference numerals 261, 262, 263, Reference numeral 264 denotes the internal configuration of the arbitration circuit 26 in each of the line termination units 1, 2, 3, and 4. The internal configuration of the arbitration circuits 263 and 264 is the same as the internal configuration of the arbitration circuit 262. is there. In FIG. 7, signals 2a, 2b, 2c, 2d, and 2e represent the same signals as those of the same reference numerals in FIG.
Indicates an initialization signal. That is, it is assumed that an initialization signal 2x (a positive direction pulse signal in the illustrated embodiment) is generated when the power of the apparatus is turned on. The only difference between the internal configurations of the arbitration circuit 261 and the arbitration circuit 262 is the difference in the connection point of the initialization signal 2x.

In FIG. 7, reference numeral 70 denotes a flip-flop, wherein a set signal input terminal is represented by a symbol S, a reset signal input terminal is represented by a symbol R, an output terminal is represented by a symbol Q, and a signal output terminal having a logic opposite to that of the terminal Q is represented by a symbol U. Reference numeral 71 denotes an inverter for inverting the logic of the signal, reference numerals 72, 73, 74 and 75 denote AND gates, reference numerals 76, 77 and 78 denote OR gates, and reference numerals 79 and 80 denote delay elements, respectively.
When the busy signal 2c is logic "0" (when not in a congestion state), the output of the inverter 71 is logic "1".
The input signal 2a is connected to the set signal input terminal S of the flip-flop 70 via the AND gate 72, and the output of the terminal U of the flip-flop 70 is input to the arbitration circuit of the next stage via the AND gate 74 and the OR gate 78. And form a kind of ring counter.

The arbitration circuit 26 of the line termination unit 21 whose busy signal 2c is logic "1" is eliminated from the above-described ring-counter circuit configuration. That is, the input signal 2a is blocked by the AND gate 72 and is not input to the flip-flop 70, but becomes the output signal 2b via the AND gate 73 and the OR gate 78.
Since the signal at the terminal U of 0 is blocked by the AND gate 74, the arbitration circuit 26 is bypassed from the ring counter-like circuit. At the time of initialization, the signal 2x is input to the set signal input terminal S of the flip-flop 70 of the arbitration circuit 261 to set the flip-flop 70. In the other arbitration circuits 262, 263 and 264, the signal 2x is The flip-flop is reset by inputting it to a reset signal input terminal R of the flip-flop 70. In the arbitration circuit 26 in which the flip-flop 70 is set and the logic of the busy signal 2c is "0", the output logic of the AND gate 75 (the logic of the signal 2e) becomes "1", indicating that there is a reception right.

The logic of the signal 2e is "1" in the arbitration circuit 261, and "0" in the other arbitration circuits 262, 263 and 264.
When a packet signal is sent out on the packet communication path 13 in the state of the above, the write enable signal 2d is output only to the arbitration circuit 261 and the reception buffer of the packet transmission / reception unit 24 of the line connection unit 1 (reference numeral 15). Packet communication path 13
The above packet signal is written. After an appropriate time delay is given to the signal 2d by the delay element 79, the signal 2d is input from the OR gate 77 to reset the flip-flop 70. When the flip-flop 70 is reset, the terminal U
Rises, and is input to the arbitration circuit 262 of the next stage through the AND gate 74 and the OR gate 78, and is input from the AND gate 72 to the set signal input terminal S of the flip-flop 70 to set the flip-flop 70. In this way, the signal 2e representing the reception right is shifted by one stage in the ring counter-like connection. In the arbitration circuit that has newly obtained the right to receive, the signal at the terminal U of the flip-flop 70 falls from logic “1” to logic “0”,
This is input to the set signal input terminal S of the next-stage flip-flop 70, so that the flip-flop 70 is kept in the original state.

Next, a case where the logic of the signal 2c changes from "0" to "1" in the arbitration circuit operating with the reception right (referred to as the arbitration circuit 261 in FIG. 7) will be described. While the logic of the signal 2c is "0", the logic of the terminal B of the flip-flop 70 having the reception right (the logic is "0")
Is output through the AND gate 74 and the OR gate 78, but the logic (logic “1”) of the terminal B of the flip-flop 70 of the arbitration circuit (arbitration circuit 264) in the immediately preceding stage where the logic of the signal 2c becomes “1” Is output through the AND gate 73 and the OR gate 78, so that the flip-flop 7 of the next-stage arbitration circuit (arbitration circuit 262) is output.
0 is set and the receiving right is assigned.

Consider a case where the logic of the signal 2c is changed from "1" to "0". The logic of the signal 2c is changed from "0" to "1" immediately before the receiving buffer of the packet transmitting / receiving unit 24 overflows. Assuming that this state is the buffer usage rate A% and the signal 2c changes from logic "0" to logic "1" when the buffer usage rate becomes A% or more,
Changing the logic of the signal 2c from "1" to "0" takes into account a sufficiently large hysteresis,
When the buffer usage rate drops to B% which is sufficiently smaller than A%, the logic of the signal 2c is changed from "1" to "0" for the first time.
Changes to

Also, while the logic of the input signal 2a is "0", it is necessary to avoid changing the logic of the signal 2c from "1" to "0". Otherwise, the logic of the output signal 2b changes, and the flip-flop 70 in the next stage malfunctions. As described above, with reference to FIG. 7, it has been described that only one of the plurality of line termination units 21 is cyclically given the reception right. In the above description, the case where the hardware shown in FIG. 7 is used has been described for the sake of convenience, but it is easy to configure software that performs the same operation as the hardware shown in FIG.

Hereinafter, the operation of the circuit of FIG. 1 will be specifically described. FIG. 4 is an operation time chart showing a time distribution of the packets on the packet communication path 13, wherein each unit is connected to the communication path 1.
The packet is sent out onto the packet communication path 13 while checking that no signal collision occurs on the packet communication path 13 without giving any consideration to the state 4. In the example shown in FIG. 4, the packet A is transmitted from the unit 2 at the time T1, the packet B is transmitted from the unit 1 at the time T2,
At time T3, packet C is transmitted from unit 3; at time T4, packet D is transmitted from unit 1;
, A packet E is transmitted from the unit 3 and a packet F is transmitted from the unit 3 at time T6. FIG. 5 is a schematic diagram showing a packet on the packet communication path 13. However, it does not mean that a plurality of packets exist on the packet communication path 13 at the same time, but that they appear in the temporal order shown in the figure.

FIG. 6 is a schematic diagram showing which packet is transmitted from which line terminating unit. Since the line terminating unit 21 having the receiving right first is the line terminating unit 1 (reference numeral 15), the packet A On the other hand, the line permitting unit 1
d is generated and written to the line termination unit 1, the flip-flop 70 of the line termination unit 1 is reset by the delayed signal 2d, and the flip-flop of the line termination unit 2 of the next stage is reset when the signal logic at the terminal U rises. Is set, the line termination unit 2 of the next stage obtains the reception right, the packet B is written into the reception buffer of the line termination unit 2, and thus the packet C is transmitted to the line termination unit 3 and the packet D is transmitted to the line termination unit 3. Line termination unit 4
Are written respectively. Next, the reception right circulates, and the packet E is written to the line termination unit 1. Next, since the line termination unit 2 outputs the busy signal 2c and is removed from the ring counter connection (assuming so), Packet F
Is written to the line termination unit 3.

FIG. 8 is a schematic diagram showing an example of shifting the reception right in a ring counter-like circuit composed of the arbitration circuits 1-4 (reference numerals 261-264) shown in FIG.
The reception right is determined by the logic of the signal 2e. When the logic is "1", the reception right exists, and when the logic is "0", the reception right is absent. At the time T1 when the packet A is received, the arbitration circuit 261 has the reception right. When the reception is completed, the reception right is transferred to the arbitration circuit 262. At the time T2, the packet B is received. The right shifts to the arbitration circuit 263, and the packet C is received at the time T3. When the reception is completed, the reception right is changed to the arbitration circuit 264.
The packet D is received at time T4.

When the reception of the packet D is completed, the reception right circulates and moves to the arbitration circuit 261, and at time T5, the packet E
Is received. By this time T5, the arbitration circuit 262 outputs the busy signal 2c and is excluded from the ring counter connection, and the output from the arbitration circuit 261 is input to the arbitration circuit 263. The right shifts to the arbitration circuit 263, and the packet F is received at time T6.

Although the present invention has been described with reference to a preferred embodiment, it is needless to say that the present invention is not limited by the described embodiment. For example, the X.X. Although it has been described that the 25 LAP B protocol is used, another protocol may be used. Further, in the embodiment shown in FIG. 1, the total number of line termination units is four, but the total number of line termination units 21 is not limited to four. Although the packet has a variable length as shown in FIG. 3, it is more convenient to use a fixed-length packet based on the definition of the ATM cell when, for example, determining a logical change point of the signal 2c.

[0025]

As described above, according to the present invention, when a packet is transmitted from each unit to the packet communication path 13, the load on the communication line can be reduced without regard to which communication line is used. There is an effect that it can be automatically distributed to each communication line.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a line termination unit in FIG.

FIG. 3 is a format diagram showing a format of a packet transmitted according to the present invention.

FIG. 4 is an operation time chart showing a time relationship of packets output from each unit shown in FIG. 1 onto a packet communication path.

FIG. 5 is a schematic diagram showing an appearance order of each packet shown in FIG. 4 on a packet communication path.

FIG. 6 is a schematic diagram showing the packet shown in FIG. 5 and a line through which the packet is transmitted.

FIG. 7 is a block diagram showing a cyclic cascade of the arbitration circuit shown in FIG. 2;

8 is a schematic diagram showing an example of shifting of a signal representing a reception right in the ring counter-like circuit constituted by the cyclic cascade shown in FIG. 7;

[Explanation of symbols]

 2a Input signal to arbitration circuit 2b Output signal from arbitration circuit 2c Busy signal 2d Write permission signal 2e Reception right signal 2x Initialization signal 11 Host device 12 Base station device 13 Packet communication path 14 Communication path 15-18 Line termination section 1 -21 Line termination unit (arbitrary) 22 Line transmission / reception unit 23 CPU 24 Packet transmission / reception unit 25 Verification circuit 26 Arbitration circuit (arbitrary) 101-10N unit 261 Arbitration circuit in line termination unit 1 262 Arbitration circuit in line termination unit 2 Arbitration circuit 263 Arbitration circuit in line termination unit 3 264 Arbitration circuit in line termination unit 4

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[Procedure amendment]

[Submission date] July 26, 1999 (1999.7.2)
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

Claims (6)

[Claims] A plurality of communication lines are provided between a base station device and a higher-level device for the base station device, and communication is performed between the base station device and the higher-level device via the plurality of communication lines. In this case, in the line load distribution means for distributing the load to the plurality of communication lines, each line termination unit provided in the base station device for terminating each line of the plurality of communication lines, A plurality of units provided in the base station apparatus for performing communication between the base station apparatus and the higher-level apparatus, all line termination units and all units in the base station apparatus are connected in parallel with each other. A ring counter comprising a packet communication path, an arbitration circuit for outputting a signal indicating the reception right of the line termination unit in each line termination unit, and cascading all the line termination units.
At the time of initialization, a signal representing the reception right of one line termination in the ring counter circuit is logic "1", and a signal representing the reception right of all other line terminations is Initialization means for setting the logic to "0"; a write enable signal for a packet transmitted on the packet communication path by an arbitrary unit among all the units is a line termination whose signal indicating the reception right is a logic "1" A line selection means provided only to the unit, and after a packet on the packet communication path is written in the reception buffer of the line termination unit selected by the line selection means, a signal of logic "1" representing the reception right is transmitted. Receiving right shift means for shifting to the next stage of the ring counter circuit, means for reading out the signals in the receiving buffer of the line termination unit in the order of writing and sending out the signals to the line A line load balancing means comprising: 2. The line load distributing unit according to claim 1, wherein when a buffer usage rate, which is a ratio of a data storage amount to a total capacity of a reception buffer of said line terminal unit, becomes A% or more, said line terminal unit. The logic of the busy signal is changed from “0” to “1”, and the buffer usage rate becomes B%
When the following condition is satisfied (B <A and A and B are determined by design), the logic of the busy signal of the line termination unit is changed from “1” to “0”, and the ring counter-like circuit A line load distributing means comprising only a line terminating unit whose logic is "0". 3. The line load distribution means according to claim 2, wherein said ring counter circuit outputs an output signal of a logic opposite to a signal representing a reception right of said line termination unit in each line termination unit to a line termination of a next stage. In a line terminating unit which is cascaded cyclically as an input signal of the unit, and the logic of the busy signal is "1", the input signal is directly connected as an output signal to the next stage. Line load distribution means. 4. The line load distributing means according to claim 1, wherein said line selecting means includes a collating circuit, and said collating circuit inspects a destination address contained in a header of a packet on said packet communication path, and checks said destination address. Is a logical "1" only when the signal is normal.
The line load distributing means, wherein the write permission signal is given to the line termination unit. 5. A plurality of communication lines are provided between a base station device and a higher-level device for the base station device, and communication is performed between the base station device and the higher-level device via the plurality of communication lines. In the above case, in the line load distribution method for distributing a load to the plurality of communication lines, each line termination unit for terminating each line of the plurality of communication lines in the base station device; Providing a plurality of units for performing communication between a station device and the higher-level device, and providing a packet communication path in which all the line terminating units and all the units are connected in parallel with each other; Configuring a ring counter-like circuit by cascading an arbitration circuit for outputting a signal indicating the right of reception of all the circuits for all the line terminating units; one line in the ring counter-like circuit An initialization step of setting the signal representing the reception right of the termination unit to logic "1" and the signals representing the reception rights of all other line termination units to logic "0"; an arbitrary unit among all the units Sending a packet onto the packet communication path from the line, a write permission signal for writing a packet on the packet communication path to a reception buffer of the line termination section for a line termination section whose signal indicating the reception right is logic "1" Is output; after the writing by the write enable signal is completed, a reception right shifting step of shifting a signal of logic “1” representing the reception right to the next stage of the ring counter-like circuit; Reading the signals in the receiving buffer in the order of writing and sending out the signals to the line. 6. The line load balancing method according to claim 5, wherein when a buffer utilization rate, which is a ratio of a data storage amount to a total capacity of a reception buffer of said line termination unit, becomes A% or more, said line termination unit. Is changed from "0" to "1", and when the buffer usage rate becomes B% or less (B <A and A and B are determined by design)
Change the logic of the busy signal of the line termination unit from “1” to “0”
Wherein the ring counter-like circuit comprises a step of configuring the ring counter-like circuit excluding a line terminating unit whose logic of a busy signal is "1".