JP2000101115A - Manufacture of photovoltaic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent dopants contained in a P-type layer or an N-type layer from being diffused into an I-type layer so as to improve a photovoltaic device in an open voltage, by a method wherein an electrode opposed to a substrate where a sub-layer is formed and another electrode opposed to an adjacent substrate where a sub-layer is formed are made different from each other in polarity, when an electric discharge is performed so as to form one of a multilayered buffer semiconductor layer. SOLUTION: Buffer semiconductor layers 105a, 105b, 107a, and 107b are each formed on an interface between an N-type layer and an I-type layer and an interface between an I-type layer and a P-type layer, and these layers are formed through a method where material gas is made to react by two applied electric powers. That is, provided that the layers 105a and 107a and the layers 105b and 107b denote first buffer semiconductor layers and second buffer semiconductor layers respectively, a first and a second cathode electrode installed in a film forming space in a forming chamber are set different from each other in potential polarity or either of a first and a second cathode electrode is set at 0 volt in potential polarity, when a glow discharge takes place so as to form the first buffer semiconductor layers 105a and 105b and the second buffer semiconductor layers 105b and 107b in this sequence respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a photovoltaic element such as a solar cell or an optical sensor.
The present invention relates to a method for manufacturing a photovoltaic device in which a buffer semiconductor layer is formed at an interface of a semiconductor junction.

[0002]

2. Description of the Related Art As a photovoltaic element, a solar cell utilizing the photovoltaic effect of a semiconductor utilizes natural energy such as sunlight, and research and development for practical use in various fields have been active. There are many types of solar cells due to differences in semiconductor materials. For example, in the manufacture of solar cells using a non-single-crystal semiconductor film, plasma CVD (C
chemical Vapor Deposition)
The law is widely used.

[0003] The semiconductor layer of a solar cell has a semiconductor junction such as a so-called pn junction or pin junction. When a thin film of a-Si or the like is used as these semiconductor layers, silane (SiH ₄ ) as a raw material gas, phosphine (PH ₃ ),
A semiconductor film formed by mixing elements serving as dopants such as diborane (B ₂ H ₆ ) and applying activation energy by plasma to decompose has a predetermined conductivity type, and these semiconductor films are formed on a substrate. If the layers are sequentially stacked, a desired semiconductor junction can be easily obtained. Therefore, in the manufacture of a non-single-crystal solar cell, an independent formation chamber for forming each semiconductor layer is provided, and each semiconductor layer is manufactured in each formation chamber.

For example, US Pat. No. 4,400,009 discloses a roll-to-roll system.
1) A continuous plasma CVD apparatus employing the method is disclosed. In this apparatus, a plurality of glow discharge regions, that is, formation chambers for depositing semiconductor layers are provided in rows.
An extremely long flexible substrate having a predetermined width is passed through each of the forming chambers. On this substrate, a semiconductor layer of a predetermined conductivity type is deposited in each glow discharge region of each chamber as it is transported through each forming chamber, and the semiconductor layer is continuously transported in the longitudinal direction thereof, thereby forming a semiconductor. A device having a junction is manufactured continuously. In this apparatus, a gas gate is provided to prevent a dopant gas involved in a film forming reaction of each semiconductor layer from diffusing and mixing into another glow discharge region. That is, each glow discharge region, so that the opening is separated from each other by a very narrow slit-shaped separation passageway, thereby further separating passages example Ar, by flowing a gas such as H ₂ scavenged.

[0005]

However, the conventional method for manufacturing a photovoltaic device (solar cell) has the following problems.

(1) Since the gas gate is provided, the deposition space for the p-type layer and the n-type layer can be substantially separated from the deposition space for the i-type layer, thereby preventing the dopant from being mixed in the gas state. Although possible, for example, when or after forming the i-type layer on the n-type layer, phosphorus (P) as a dopant of the n-type layer thermally diffuses into the i-type layer. For this reason, the ni junction is weakened, and the open-circuit voltage and the fill factor of the solar cell are deteriorated. As a result, there is a problem in the initial characteristics that the photoelectric conversion efficiency is reduced.

(2) Even if the photoelectric conversion efficiency in the initial stage of manufacture is high to some extent, if it is actually used under various weather and installation conditions, the i-type dopant of the p-type layer and the n-type layer There has been a problem of reliability in that thermal diffusion to the mold layer gradually progresses, which promotes deterioration of the solar cell.

The solar cell is required to have a sufficiently high photoelectric conversion efficiency, stable characteristics, and easy mass production. We want to improve the conductivity, mechanical properties, fatigue characteristics of repeated use, and environmental resistance, and at the same time increase the area, uniform the film thickness and film quality, and at the same time, mass-produce reproducibly by high-speed film formation. .

[0009] A power generation system using a solar cell includes:
In many cases, unit modules in which solar cell elements are standardized are connected in series or in parallel, and unitized to obtain predetermined voltages and currents.

In the case of unitization, since the characteristics of the unit are determined by the unit module having the smallest current and voltage characteristics in the whole connected unit modules, not only the characteristics of each unit module are improved, but also the It is important to reduce the variation in the characteristics in the above. In addition, disconnection or short circuit must not occur in each unit module because the yield is deteriorated. For this reason, at the stage of manufacturing the unit module, it is necessary to ensure uniformity of the characteristics of the semiconductor layer itself, which is the element body of the solar cell, and it is required to reduce defects in the semiconductor layer. From the viewpoint of facilitating module design and simplifying the module assembling process, the provision of a semiconductor deposited film having excellent uniformity of characteristics over a large area enhances mass productivity of solar cells, There is a need to achieve significant reductions in production costs.

Accordingly, the present invention has been made in view of such a conventional problem, and in a semiconductor junction such as a pin junction, a dopant of a p-type layer or an n-type layer is diffused into another layer such as an i-type layer. To provide a method for manufacturing a photovoltaic element, which can prevent the occurrence of the photovoltaic element, can improve the output characteristics of the manufactured photovoltaic element, particularly the open-circuit voltage and the fill factor, and can reduce the deterioration of those characteristics. With the goal.

[0012]

The present invention employs a process of introducing a material gas into a discharge space of a reaction vessel, decomposing the material gas by plasma discharge, and forming a non-single-crystal semiconductor layer on a substrate. And at least one pi on the substrate
In a method of manufacturing a photovoltaic device having an n-junction and having a buffer semiconductor layer composed of a plurality of sublayers between an n-type layer and an i-type layer and / or between an i-type layer and a p-type layer At the time of a discharge that forms at least one of the buffer semiconductor layers having the multilayer structure, the polarity of an electrode facing the substrate for forming one sublayer, and the sublayer adjacent to the one sublayer. A method for manufacturing a photovoltaic element, wherein the polarity of an electrode facing the substrate for forming a substrate is made different, or the potential of one of the electrodes is set to 0 V.

Hereinafter, in the present specification, these sub-layers are referred to as a first buffer semiconductor layer, a second buffer semiconductor layer, and the like. The buffer semiconductor layer between the n-type layer and the i-type layer is called an n / i buffer semiconductor layer, and the buffer semiconductor layer between the i-type layer and the p-type layer is called a p / i buffer semiconductor layer. That is, when a buffer semiconductor layer composed of a plurality of sublayers is provided between an n-type layer and an i-type layer, each sublayer has a first n / i
The buffer semiconductor layer is called a second n / i buffer semiconductor layer.

Here, the electrode facing the substrate is generally called a cathode electrode, but when the polarity is +, it becomes an anode electrode. The electrode to be paired with the electrode may be a substrate on which a film is formed, or may be provided separately from the substrate.

Further, in a preferred aspect of the method of manufacturing a photovoltaic device according to the present invention, at least a part of the buffer semiconductor layer is formed by a-Si: H or a-SiGe: H or a
-SiC: H.

In a preferred embodiment of the method for manufacturing a photovoltaic device according to the present invention, the photovoltaic device is a solar cell.

In a preferred aspect of the method of manufacturing a photovoltaic element according to the present invention, the substrate is moved through a plurality of film forming spaces each having a discharging means.

In a preferred aspect of the method for manufacturing a photovoltaic element according to the present invention, the substrate is formed in a belt shape.

When a discharge occurs to form the buffer semiconductor layer, the polarity of the electrode facing the substrate for forming the adjacent sub-layer is made different from each other, or one of the potentials is set to 0 V, so that p A buffer semiconductor layer adapted to the band gap of the n-type layer or the n-type layer can be formed, and the dopant of the p-type layer or the n-type layer can be effectively prevented from thermally diffusing into the i-type layer during film formation. Buffer semiconductor layer
It is possible to provide the solar cell at the i interface and / or the ni interface, thereby improving the output characteristics of the solar cell, particularly the open-circuit voltage and the fill factor, and as a result, providing a solar cell with improved output characteristics.

Further, since an effective buffer semiconductor layer is provided at the pi interface and / or the ni interface, diffusion of the dopant in an actual use state can be prevented, and deterioration of the solar cell can be reduced. An improved solar cell can be provided.

In particular, in a stacked photovoltaic element,
An extremely good pn junction can be realized, and a higher-quality photovoltaic element can be uniformly formed with good reproducibility.

Further, at least a part of the buffer semiconductor layer is made of a-Si: H or a-SiGe: H or a
By using -SiC: H, a photovoltaic element having excellent mass productivity and stable characteristics can be obtained.

By using a photovoltaic element as a solar cell, a solar cell in which diffusion of a dopant in a semiconductor junction is suppressed can be manufactured.

Further, a plurality of discharge means are arranged in order to form a plurality of film-forming spaces, and the substrate is continuously moved in the film-forming space, whereby a semiconductor layer can be formed continuously. At this time, the semiconductor layers can be stacked in conjunction with each other, so that the film thickness and film quality can be made uniform.

Further, by forming the substrate in a band shape, the semiconductor layer can be continuously formed on the substrate by continuously moving the band-shaped substrate in the film formation space. Photovoltaic elements can be manufactured in large quantities.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the method for manufacturing a photovoltaic device according to the present invention will be described below with reference to the accompanying drawings. Here, a solar cell will be described as an example of a photovoltaic element. FIG. 1 is a schematic sectional view showing an example of a solar cell manufactured according to the present invention.

The solar cell 101 is of an amorphous type, and has a backside reflective layer 103 on a substrate 102.
, N-type semiconductor layer 104, first n / i buffer semiconductor layer 105 a, second n / i buffer semiconductor layer 105 b, i
Semiconductor layer 106 and first p / i buffer semiconductor layer 107
a, a second p / i buffer semiconductor layer 107 b, a p-type semiconductor layer 108, and a transparent electrode 109, which are sequentially stacked. On the transparent electrode 109, a current collecting electrode 110 and an extraction electrode 111 Is provided to receive light from the transparent electrode 109 side. The extraction electrode 111 is also provided on the substrate 102.

(Substrate) The substrate 102 is preferably made of a conductive member, and is required to have a small strength and a small deformation and a high strength at the temperature at which the semiconductor layer is formed. For example, metal thin plates and composites thereof such as stainless steel, aluminum and alloys thereof, iron and alloys thereof, copper and alloys thereof, and metal thin films of different materials or SiO ₂ , Si ₃ N ₂ , Al _{2 on} their surfaces O
_3. An insulating thin film such as AlN ₃ is made of a material which has been subjected to a surface coating treatment by a sputtering method, a vapor deposition method, a plating method or the like. Further, the surface of a heat-resistant resin sheet such as polyimide, polyamide, polyethylene terephthalate, epoxy, or a composite of these with glass fiber, carbon fiber, boron fiber, metal fiber, or the like, is formed of a simple metal or alloy, and a transparent conductive oxide. The substrate 102 may be made of (TCO) or the like that has been subjected to a conductive treatment by a method such as plating, vapor deposition, sputtering, coating, or the like.

The thickness of the substrate 102 is preferably as thin as possible because cost and storage space can be reduced.
What is necessary is just to be in the range which can exhibit the intensity | strength which maintains the shape when conveyed in a manufacturing apparatus. This thickness is set to, for example, 0.01 to 5 mm, preferably 0.02 to 2 mm.
mm, optimally 0.05 to 1 mm. Note that when a thin plate made of metal or the like is used as the substrate 102, it is easy to obtain a predetermined strength even when the thickness is relatively thin.

The width of the substrate 102 is not particularly limited, and may be set according to the size of a manufacturing apparatus (semiconductor layer forming chamber) for forming a semiconductor layer. The length of the substrate 102 is also not particularly limited, and may be a length that can be wound into a roll, or may be a longer one that is made longer by welding or the like. Further, the surface of the substrate 102 may have a so-called smooth surface or a minute uneven surface. In the case of forming a fine uneven surface, the shape is spherical, conical, pyramidal, or the like, and its maximum height (R
It is preferable that (max) be, for example, 50 to 500 nm, since light reflection on the surface becomes irregular reflection and the optical path length of the reflected light increases.

(Back reflection layer) Transparent electrode 1 on the light incident side
09 and, conversely, the bottom reflective layer 103 on the bottom side are provided to face each other with the semiconductor layer interposed therebetween.

The back reflection layer 103 is made of Ag, Au, Pt,
It is formed of a metal such as Ni, Cr, Al, Ti, Zn, Mo, W or an alloy thereof by vacuum evaporation, electron beam evaporation, sputtering, or the like. Since the metal thin film thus formed becomes a resistance component with respect to the output of the solar cell 101, its sheet resistance is 50%.
Ω or less, and more preferably 10 Ω or less.

(Transparent electrode) The transparent electrode 109 is made of Sn
O ₂ , In ₂ O ₃ , ZnO, CdO, Cd ₂ SnO ₄ , IT
Using a metal oxide such as O (indium tin oxide: In ₂ O ₃ SnO ₂ ) or a metal thin film in which a metal such as Au, Al, Cu or the like is formed in a very thin and translucent shape, etc. It is preferable that the film is formed so that the transmittance is 70% or more. This is for efficiently absorbing light from the sun, white fluorescent lamps, and the like into the semiconductor layer, and it is more preferable that the light transmittance is 80% or more.

Although the transparent electrode 109 is laminated on the p-type semiconductor layer 108 in this embodiment, it may be laminated on the n-type semiconductor layer if the laminated structure is different. For forming the transparent electrode 109, a resistance heating evaporation method, a sputtering method, a spray method, or the like is suitably used, and a forming method is appropriately selected.

(Current Collecting Electrode) The current collecting electrode 110 is provided on the transparent electrode 109, and is composed of Ag, Cr, Ni, Al, and A.
It is formed to reduce the sheet resistance value of the transparent electrode 109 by using a simple substance of a metal such as u, Ti, Pt, Cu, Mo, W, an alloy thereof, or carbon as a material. In the stacked structure shown in FIG. 1, since the transparent electrode 109 is formed after each semiconductor layer is formed, the substrate temperature when the transparent electrode 109 is formed cannot be too high. As a result, the sheet resistance of the transparent electrode 109 becomes relatively high. Therefore, it is particularly preferable to form the current collecting electrode 110 to reduce the resistance. The material of the current collecting electrode 110 is appropriately selected in consideration of the advantages of the above-described metal or carbon, that is, low resistance, low diffusion to the semiconductor layer, robustness, and easy formation of the electrode by printing or the like. Good.

The current collecting electrode 110 preferably has a shape uniformly spread on the light receiving surface in order to secure a sufficient amount of incident light on the lower semiconductor layer, and its area is larger than the entire light receiving area. It is preferably at most 15%, more preferably at most 10%. The sheet resistance is preferably 50Ω or less, more preferably 10Ω.

(Transparent Conductive Layer) A transparent conductive layer (buffer resistor layer) made of ZnO or the like may be formed between the back reflection layer 103 and the n-type semiconductor layer 104.
By forming this, short circuit prevention and buffering of the electrode metal can be achieved. In other words, by this transparent conductive layer,
The metal element constituting the back reflection layer 103 is the n-type semiconductor layer 1
04 can be prevented, and by providing the transparent conductive layer with an appropriate resistance value, the back reflection layer 103 provided between the semiconductor layers and the upper transparent electrode 109 can be prevented from being diffused. A short circuit caused by a defect such as a pinhole can be prevented, and incident light that causes multiple interference by a thin film can be confined in the solar cell 101. The transparent conductive layer is made of a material based on magnesium fluoride, indium, tin, cadmium, zinc, antimony, silicon, chromium, oxides, nitrides and carbides of aluminum, copper, and aluminum, or a mixture thereof. Particularly, magnesium fluoride and zinc oxide are easy to form and have an appropriate resistance value and light transmittance, so that they can be preferably applied to a transparent conductive layer.

(Semiconductor Layer) The i-type semiconductor layer 106 is made of a-
Si: H, a-Si: F, a-Si: H: F, a-Si
C: H, a-SiC: F, a-SiC: H: F, a-S
iGe: H, a-SiGe: F, a-SiGe: H:
F, μc-Si: H, μc-SiGe: H, μc-Si
Semiconductors of so-called group IV elements or group IV alloys such as C: H, polycrystalline Si: H, polycrystalline Si: F, polycrystalline Si: H: F (a- is amorphous, μc- is microcrystal) Is formed as a material. The amount of hydrogen atoms contained in the i-type semiconductor layer 106 is preferably 20 atom% or less,
More preferably, it is set to 0 atomic% or less.

The n-type semiconductor layer 104 and the p-type semiconductor layer 10
Reference numeral 8 is formed by doping a valence electron controlling agent into the semiconductor material forming the i-type semiconductor layer 106 described above. In this case, it is preferable to include a crystal layer in the semiconductor material forming the n-type layer or the p-type layer because the light utilization rate and the carrier density can be increased. The concentration of hydrogen contained in the n-type layer or the p-type layer is preferably 5 atomic% or less, more preferably 1 atomic% or less.

The buffer semiconductor layers 105a, 105b, 107
a, 107b are a-Si: H, a-Si: F, a-S
i: H: F, a-SiC: H, a-SiC: F, a-S
iC: H: F, a-SiGe: H, a-SiGe: F,
a-SiGe: H: F, μc-Si: H, μc-SiG
e: H, μc-SiC: H and the like are formed. These buffer semiconductor layers are formed at the interface between the n-type layer and the i-type layer and at the interface between the i-type layer and the p-type layer. These layers are formed by reacting source gases with two different applied powers. Can be.

That is, the first buffer semiconductor layers 105a, 107a and the second buffer semiconductor layers 105b,
107b, the first buffer semiconductor layers 105a, 1
07a and the second buffer semiconductor layers 105b and 107b are sequentially formed, and when a glow discharge is generated, the potential polarities of the first and second cathode electrodes provided in the film forming space in the formation chamber are made different, or , One of the potential polarities of the second cathode electrode is set to 0V. As a specific method for changing the potential polarity of the plurality of cathode electrodes, a DC voltage is superposed on a voltage applied from an AC power supply. Further, the potential polarity of the cathode electrode can be appropriately controlled by making the surface area of the cathode electrode in the film formation space larger or smaller than the surface area of the anode electrode.

In order to form each of the above semiconductor layers, a microwave plasma CVD method and an RF plasma CVD method are used.
, VHF plasma CVD, ion plating, sputtering and reactive sputtering, optical CVD, thermal CVD, MOCVD, MBE, HR-CVD and other semiconductor deposition film formation methods are applied as appropriate. I do. In addition, the source gas for forming each semiconductor layer includes a simple substance, a hydride, a halide, an organometallic compound, or the like of each of the above-described material elements, which can be introduced in a gaseous state into a film formation space in each formation chamber. used. Of course, only one kind of these source gases may be used, but a plurality of kinds may be mixed and used.
e, Ne, Ar, Kr, Xe, Rn or other rare gas and a diluent gas such as H ₂ , HF or HCl may be mixed and used.

(Manufacturing Apparatus) FIG. 5 is a schematic sectional view showing an example of a manufacturing apparatus for continuously manufacturing a solar cell as a photovoltaic element.

In this manufacturing apparatus, a delivery chamber 502 and a take-up chamber 503 of a strip-shaped substrate 501 are arranged to face each other.
An n-type semiconductor layer forming chamber 504, an n / i buffer semiconductor layer forming chamber 505, an i-type semiconductor layer forming chamber 506,
A p / i buffer semiconductor layer formation chamber 507 and a p-type semiconductor layer formation chamber 508 are arranged in this order from the delivery chamber 502 side, and each of these chambers has a gas gate 5 having a gate gas introduction pipe 519.
The substrates 501 are connected to each other by 18, and the semiconductor layers are continuously formed as the substrate 501 wound up in a roll shape is sent out from the sending chamber 502 and passes through each forming chamber. , After being sequentially laminated, the winding chamber 50
3 and wound up in a roll again.

The substrate 501 is wound around a delivery bobbin 509 in the delivery chamber 502, and is wound around a winding bobbin 510 in the winding chamber 503. However, the substrate 501 can be conveyed in reverse. The delivery chamber 502 and the take-up chamber 503 are provided with conveyance rollers 511 and 512, and thereby adjust the tension of the substrate 501 and position the substrate 501.

An exhaust pipe 513 is connected to each chamber, and is connected to an exhaust pump (not shown). Exhaust pipe 5
13 is provided with a throttle valve 514,
The conductance can be adjusted. Also,
Reference numeral 517 denotes an applicator, to which a microwave transmitting member is attached at its tip, and which is connected to a microwave power supply (not shown) through a waveguide (not shown). 5
Reference numeral 22 denotes an electrode, which is connected to the RF power supply 515.

Each infrared heater 5 provided in each forming chamber
Reference numeral 21 denotes an arrangement of a large number of infrared lamps, and a lamp house 523 is provided on the back side of the infrared lamps, so that the radiant heat can be efficiently concentrated on the substrate 501. The temperature of substrate 501 is monitored by thermocouple 520.

In the delivery chamber 502 and the take-up chamber 503, a transport mechanism for winding and feeding the interleaving paper along the surface of the substrate 501 is provided.
01 may be configured to protect the surface. As a material of the interleaving paper, polyimide-based, Teflon-based and glass wool, which are heat-resistant resins, are preferable.

In each forming chamber, a bias voltage may be applied to control the potential of plasma generated in the film forming space in the chamber. As the bias voltage, it is preferable to apply a DC, a pulsating current, and an AC voltage alone or by appropriately superimposing them. By controlling the potential of the plasma, the stability and reproducibility of the plasma can be improved. In addition, the film characteristics of the film formation layer can be improved, and defects can be reduced.

The formation chamber 505 and the formation chamber 507 are both reaction chambers for forming a buffer semiconductor layer, and have the same configuration. Therefore, the formation chamber 505 will be described. Description is omitted. FIG. 2 shows a schematic schematic sectional view of the formation chamber 505.

That is, as shown in FIG. 2 as a formation chamber 202, the buffer semiconductor layer formation chamber 505 is provided with two box-shaped first and second film-forming containers 203a and 203b each having an open upper surface. And the first and second film forming vessels 203
The substrate 201 is transported in the space above a and 203b, and accordingly, a buffer semiconductor layer is formed on the opposing surface (lower surface) of the substrate 201. The formation chamber 202 and the first and second film forming containers 203a and 203b inside are both made of metal members and are electrically connected to each other.

The substrate 201 is introduced from the gas gate 218 on the carry-in side (left side in FIG. 2) of the formation chamber 202, passes through the upper spaces of the first and second film forming vessels 203a and 203b, and is carried out of the formation chamber 202. (Right side of FIG. 2) gas gate 218
And is led to the next forming chamber or the like.

Each of the first and second film-forming containers 203a and 203b has a first and second cathode electrode
21a and 221b are provided, and the first and second cathode electrodes 221a and 221b are connected to the first and second RF power sources 220a and 220a.
20b. First and second gas introduction pipes 204a and 204b for introducing a raw material gas are provided in the first and second film forming vessels 203a and 203b, respectively. The upstream side of these gas supply pipes is connected to a gas supply facility, and a source gas is discharged toward the substrate 201 from a large number of gas discharge ports provided on the downstream side.

Then, the first and second film-forming containers 203a, 203
Above the substrate 03b, on the opposite side (upper side) of the substrate 201, an infrared heater 208 for preheating and first and second infrared heaters 205 and 206 for temperature management are provided on the substrate 201.
, And thermocouples 217, 214, 215 are attached to each of them in a state of contact with the substrate 201. Further, a thermocouple 207 is provided between the infrared heater 205 and the infrared heater 206 so as to be in contact with the substrate 201. The infrared heater 208 is controlled by a temperature control device 212, and the first and second infrared heaters 205 and 206 are controlled by first and second temperature control devices 209 and 210, respectively.
When heating the substrate 201 from the back side, the infrared heater 20
8, preheating is performed to obtain a predetermined film formation temperature, and the first and second infrared heaters 205 and 206 make the temperature during film formation constant.

Next, the formation chamber 506 of the i-type semiconductor layer will be described with reference to FIG. As shown in FIG. 3, three first, second, and third film-forming spaces 302 each having a box shape with an open upper surface are provided inside the i-type semiconductor layer forming chamber 506 so as to be connected to each other. The space above the first, second, and third film formation spaces 302 is
Is transported, and accordingly, an i-type semiconductor layer is formed on the opposing surface (lower surface) of the substrate 301. This forming chamber and the outer walls 30 of the first, second, and third film forming spaces inside are formed.
2 is made of a metal member.

The substrate 301 is introduced from a gas gate (not shown) on the carry-in side (left side in FIG. 3) of the formation chamber, passes through the upper space of the first, second, and third film formation spaces 302 and passes through the space of the formation chamber. The gas is discharged through a gas gate (not shown) on the carry-out side (the right side in FIG. 3) and is guided to the next forming chamber or the like.

On the side walls of the first, second and third film forming spaces 302, first, second and third applicators 303 are provided on the substrate 301.
Are provided along the transport direction. Each applicator 3
Numeral 03 is for introducing microwave energy into the film forming space, and the distal ends of the waveguides connected to a microwave power source (not shown) are connected to each other. In addition, the mounting portions of the applicator 303 in the film formation space are each made of a microwave permeable member 304.

At the bottom of the first, second, and third film forming spaces 302, first, second, and third gas introduction pipes 3 for introducing a source gas are provided.
Numeral 06 is piped, and the upstream side is connected to a gas supply facility, so that a source gas is discharged toward the substrate 301 from a large number of gas discharge ports.

An exhaust punching board 305 is attached to the first, second, and third film forming spaces 302 on the side opposite to each applicator 303 so that microwave energy is confined in the film forming spaces. These are connected to an exhaust slot valve connected to an exhaust pipe (not shown).

Since the formation chamber 504 for the n-type semiconductor layer and the formation chamber 508 for the p-type semiconductor layer have the same structure,
The formation chamber 504 will be described, and the description of the formation chamber 508 will be omitted. FIG. 4 shows a schematic schematic cross-sectional view of the formation chamber 504.

As shown in FIG. 4, the formation chamber 402 (50
4) is a case in which a box-shaped film forming container 403 having an open upper surface is provided inside, and the upper space of the film forming container 403 is
1 is conveyed while being supported by the substrate support roller 411, and accordingly, a semiconductor layer is formed on the opposing surface (lower surface) of the substrate 401. This forming chamber 40
2 and the inner film forming container 403 are both made of a metal member and are electrically connected to each other.

The substrate 401 is introduced from the gas gate 412 on the loading side (the left side in FIG. 4) of the formation chamber 402, passes through the space above the film forming container 403, and is unloaded from the formation chamber 402 (the right side in FIG. 4). Exhausted through the gas gate 412 of
It is led to the next forming room and the like. 413 is a gate gas introduction pipe.

In the film forming container 403, a cathode electrode 415 is provided at a lower portion on the inner side.
F power supply 414. In the film forming container 403,
A gas introduction pipe 404 for introducing a source gas is provided. The gas introduction pipe 404 has an upstream side connected to a gas supply facility, and is configured to discharge a source gas toward the substrate 401 from a plurality of gas discharge ports provided downstream.

Then, the substrate 40 is placed above the film forming container 403.
1, an infrared heater 406 for pre-heating and an infrared heater 405 for temperature management are provided in order from the loading side of the substrate 401, and thermocouples 407, 408 are respectively provided on those portions. Are provided in contact with the substrate 401. The infrared heater 406 is controlled by the temperature control device 410, and the infrared heater 405 is controlled by the temperature control device 409.
When heating the substrate 401 from the back side, the infrared heater 40
Preliminary heating is performed by 6 to obtain a predetermined film formation temperature, and the temperature during film formation is made constant by the infrared heater 405.

[0065]

(Embodiment 1) An embodiment of a method for manufacturing a photovoltaic device according to the present invention will be described below. Here, a method for continuously manufacturing solar cells using the apparatus shown in FIG.
The procedure will be described.

(1) The substrate 501 is placed in the delivery chamber 502.
The delivery bobbin 509 in which is wound and stored is set,
The substrate 501 is guided by the respective gas gates 518, sequentially passed through the respective forming chambers 504, 505, 506, 507, and 508, and wound around the winding bobbin 510 of the winding chamber 503, and the tension is adjusted to the extent that there is no slack. .

The substrate 501 is made of SUS having a thickness of 0.2 mm.
430BA, 300mm wide and 300m long
After sufficient degreasing and washing are performed in advance,
The back reflection layer 1 is formed by depositing a thin film of 100 nm and a ZnO thin film to a thickness of 1 μm by sputtering.
03 and a transparent conductive layer.

(2) Each of the chambers 502 to 508 was evacuated by a vacuum pump to reduce the pressure to 1 × 10 ⁻⁶ Torr or less.

(3) Heating treatment before film formation A gate gas (H ₂ ) is supplied to each gas gate 518 from a gate gas introduction pipe 519 at 500 cc / min, and 500 cc of He is supplied from each gas introduction pipe to each film formation container.
/ Min. At this time, the pressure in each of the chambers 502 to 508 was set to 1.0 Torr. To adjust the pressure, the opening of each throttle valve 514 is adjusted, and the exhaust pipe 5 of each chamber is adjusted.
This was performed by evacuating each chamber through a vacuum pump through 13.

Thereafter, in each of the forming chambers 504 to 508, the infrared heater for preheating was operated to heat the substrate 501 and the inner member to 400 ° C., and this state was maintained for at least 3 hours.

(4) Each of the chambers 502 to 508 was evacuated by a vacuum pump to reduce the pressure to 1 × 10 ⁻⁶ Torr or less.

(5) Gate gas introduction during film formation Gate gas (H ₂ ) was introduced into each gas gate 518 from a gate gas introduction pipe 519 at 500 cc / min.

(6) Preparation for forming n-type semiconductor layer 104 In the forming chamber 402 (corresponding to 504 in FIG. 5) shown in FIG. Was heated, and the set value of the heating temperature was 250 ° C. And the temperature control device 40
9 was started to heat the substrate 401 by the infrared heater 405, and the set value of the heating temperature was 270 ° C.

A raw material gas was introduced into the film forming container 403. That is, the raw material gas was introduced from the gas supply equipment into the gas introduction pipe 404 and led to the space inside the film forming container 403. here,
100 cc / min of SiH ₄ gas, PH ₃ / H ₂ (P
H ₃ : 1%) gas at 500 cc / min, H ₂ gas at 70
0 cc / min was introduced. At this time, the pressure of the film forming container 403 was set to 1.0 Torr. The pressure is adjusted by the formation chamber 4
02 by adjusting the opening degree of the throttle valve 514 and evacuating with a vacuum pump through the exhaust pipe 513.

When the RF power supply 414 is activated, the output value is set to 10
0 W, and the film forming container 4 was set through the cathode electrode 415.
A discharge was generated in the cell.

(7) n / i buffer semiconductor layers 105a, 105
05b Preparation for film formation In the formation chamber 202 (corresponding to 505 in FIG. 5) shown in FIG. 2, the temperature control device 212 for preheating is started, and the substrate 201 is heated by the infrared heater 208. 260 ° C. Then, the first temperature control device 209 was started, and the substrate 201 was heated by the first infrared heater 205, and the set value of the heating temperature was 260 ° C.
The substrate 201 was heated by the second infrared heater 206 by activating the second temperature control device 210, and the set value of the heating temperature was 300 ° C.

A source gas was introduced into the first film forming container 203a. That is, the raw material gas was introduced from the gas supply equipment into the first gas introduction pipe 204a, and was led to the space inside the first film forming container 203a. Here, the SiH ₄ gas is supplied at 50 cc / min,
H ₂ gas was introduced at 1000 cc / min. At this time, the pressure of the first deposition container 203a was set to 1.1 Torr. The pressure was adjusted by adjusting the opening of a throttle valve provided in the container and evacuating with a vacuum pump through an exhaust pipe.

The output value was set to 50 W by activating the first RF power supply 220a. At this time, the first cathode electrode 221
A DC power supply (not shown) was connected to a, and the DC power supply was started to superimpose a DC voltage of +100 V on the first cathode electrode 221a to generate a discharge in the first film forming container 203a.

A source gas was introduced into the second film forming container 203b. That is, the raw material gas was flowed from the gas supply equipment into the second gas introduction pipe 204b, and was led to the space inside the second film forming container 203b. Here, SiH ₄ gas is supplied at 100 cc / mi.
n, and H ₂ gas were introduced 300 cc / min. On this occasion,
The pressure of the second film forming container 203b was set to 1.1 Torr.
The pressure was adjusted by adjusting the opening of a throttle valve provided in the container and evacuating with a vacuum pump through an exhaust pipe.

The output value was set to 100 W by activating the second RF power supply 220b, and a discharge was generated in the second film-forming container 203b through the second cathode electrode 221b. The bias voltage at this time was -2 volts.

(8) Preparation for forming i-type semiconductor layer 106 The substrate 501 is heated by the infrared heater by activating the temperature control device for preheating, and the set value of the heating temperature is 350 ° C.
And Then, the temperature control device is started, and the substrate 501 is heated by the infrared heater.
0 ° C.

The first, second and third film forming spaces 30 shown in FIG.
Raw material gas was introduced into 2. That is, the raw material gas was flowed from the gas supply equipment into the first, second, and third gas introduction pipes 306, and was led to each film forming space. Here, the SiH ₄ gas is 80 c
c / min, 90 cc / min of GeH ₄ gas and 200 cc / min of H ₂ gas were introduced. At this time, the pressure in each film formation space was set to 0.02 Torr. The pressure was adjusted by adjusting the opening of the throttle valve in the forming chamber and exhausting the gas through a vacuum pipe with a vacuum pump.

The first, second, and third microwave power supplies are activated to set each output value to 200 W, thereby introducing microwave (μw) power to each applicator 303, and transmitting the microwave transparent member 304. A discharge was generated in each film forming space through the process.

(9) p / i buffer semiconductor layers 107a, 107
In the formation chamber 202 (corresponding to 507 in FIG. 5) shown in FIG. 2, the temperature controller 212 for preheating is started to heat the substrate 201 by the infrared heater 208, and the set value of the heating temperature is The temperature was 360 ° C. Then, the first temperature control device 209 was started to heat the substrate 201 by the first infrared heater 205, and the set value of the heating temperature was 380 ° C.
The substrate 201 was heated by the second infrared heater 206 by activating the second temperature control device 210, and the set value of the heating temperature was 200 ° C.

A source gas was introduced into the first film forming container 203a. That is, the raw material gas was introduced from the gas supply equipment into the first gas introduction pipe 204a, and was led to the space inside the first film forming container 203a. Here, SiH ₄ gas is supplied at 150 cc / mi.
n, and H ₂ gas was introduced 1500cc / min. At this time, the pressure of the first deposition container 203a was set to 1.1 Torr. The pressure was adjusted by adjusting the opening of a throttle valve provided in the container and evacuating with a vacuum pump through an exhaust pipe.

The output value was set to 200 W by activating the first RF power supply 220a, and a discharge was generated in the first film forming container 203a through the first cathode electrode 221a. The bias voltage at this time was -54V.

The source gas was introduced into the second film forming container 203b. That is, the raw material gas was flowed from the gas supply equipment into the second gas introduction pipe 204b, and was led to the space inside the second film forming container 203b. Here, SiH ₄ gas is supplied at 40 cc / min,
H ₂ gas is introduced 1500cc / min. At this time, the pressure of the second film forming container 203b was set to 1.1 Torr. The pressure was adjusted by adjusting the opening of a throttle valve provided in the container and evacuating with a vacuum pump through an exhaust pipe.

The output value was set to 1800 W by activating the second RF power supply 220 b. At this time, the second cathode electrode 2
A DC power supply (not shown) was connected to 21b, the DC power supply was activated, and a DC voltage of +200 V was superimposed on the second cathode electrode 221b to generate a discharge in the second film forming container 203b.

(10) Preparation for forming p-type semiconductor layer 108 In the formation chamber 402 (corresponding to 508 in FIG. 5) shown in FIG. Was heated, and the set value of the heating temperature was 270 ° C. And the temperature control device 40
9 was started to heat the substrate 401 by the infrared heater 405, and the set value of the heating temperature was 270 ° C.

A source gas was introduced into the film forming container 403. That is, the raw material gas was introduced from the gas supply equipment into the gas introduction pipe 404 and led to the space inside the film forming container 403. here,
10 cc / min of SiH ₄ gas, BF ₃ / H ₂ (BF ₃ :
(1% dilution) gas at 500 cc / min, H ₂ gas at 60
00 cc / min was introduced. At this time, the pressure of the film forming container 403 was set to 1.0 Torr. The pressure was adjusted by adjusting the opening of the throttle valve 514 in the formation chamber 402 and exhausting the gas through the exhaust pipe 413 with a vacuum pump.

The RF power supply 414 is activated to set the output value to 15
The discharge was set to 00 W and generated in the film formation container 403 through the cathode electrode 415.

(11) The substrate 501 is placed in the delivery chamber 50
It was transported from the second side to the winding chamber 503 side. The transport speed is set to 2000 mm / min, whereby the n-type semiconductor layer 104 and the n / i buffer semiconductor layer 105 are formed on the substrate 501.
a, 105b, the i-type semiconductor layer 106, the p / i buffer semiconductor layers 107a, 107b, and the p-type semiconductor layer 108 were formed.

(12) After one roll of the substrate 501 was transported, all plasma, all gas supply, and power supply to all infrared heaters were stopped. Next, N ₂ gas for residual gas leak was introduced into the chamber to return to atmospheric pressure, and the substrate 501 wound on the winding bobbin 510 was taken out.

(13) Transparent electrode 109 and current collecting electrode 1
Formation of 10 On the p-type semiconductor layer 108 of the substrate 501 taken out, an IT
O (In ₂ O ₃ + SnO ₂ ) is 100 nm by vacuum evaporation.
To form a transparent electrode 109, and further, Al is vacuum-deposited on a predetermined portion of the transparent electrode 109 by 2 μm.
The collector electrode 110 was formed by vapor deposition to a thickness of m. Subsequently, it was cut into a size of 36 cm × 22 cm.

The solar cell having the laminated structure shown in FIG. 1 was manufactured by the above procedure. This is referred to as Sample 1, and the manufacturing conditions are shown in Table 1.

[0096]

[Table 1]

Comparative Example 1 A solar cell was manufactured under the same conditions as in Example 1 except that the polarity of the bias voltage of the cathode electrode was not changed when forming the buffer semiconductor layer.

Specifically, in step (7), the DC voltage is not superimposed on the first cathode electrode 221a, the bias value is set to -10 V, and in step (9), the DC voltage is superimposed on the second cathode electrode 221b. No bias value was set to -10
0 V was applied. The solar cell manufactured in this manner was compared with Comparative Sample 1
I will call it.

(Evaluation) First, for each of the sample 1 obtained in the example 1 and the comparative sample 1 obtained in the comparative example 1, the photoelectric conversion efficiency η = ｛maximum generated power per unit area (mW / c)
m ² ) / incident light intensity per unit area (mW / cm ² )｝
Was evaluated.

Each of Sample 1 and Comparative Sample 1 was manufactured by five sheets. These samples were prepared using AM-1.5 (100 m
W / cm ² ), placed under simulated sunlight, applying a DC voltage to the extraction electrode 111 to measure current-voltage characteristics,
Further, the open voltage was measured, and the fill factor and the photoelectric conversion efficiency η were determined.

As a result, the sample 1 was different from the comparative sample 1 in that:
The open circuit value was 1.12 times on average, the fill factor value was 1.1 times on average, and the photoelectric conversion efficiency η was 1.29 times on average.

Further, each of the sample 1 and the comparative sample 1 was vacuum-sealed with a protective film made of polyvinylidene fluoride (VDF), and was placed outdoors, and a fixed resistance of 50Ω was connected to both electrodes. It was placed under so-called actual use conditions. After one year under the actual use condition, the photoelectric conversion efficiency η is obtained again, and the deterioration rate caused by light irradiation, that is, the value of the photoelectric conversion efficiency η impaired by the deterioration is divided by the initial photoelectric conversion efficiency η. Was examined. As a result, sample 1
Is 23% lower than that of Comparative Sample 1.
And was kept low.

From the above, it was found that the solar cell manufactured according to the present invention has a remarkable improvement in photoelectric conversion efficiency η and can maintain its initial performance for a long period of time.

Example 2 A solar cell was manufactured in the same manner as in Example 1 except that the manufacturing conditions were as shown in Table 2.

The difference from the first embodiment is that the procedure (7)
In the above, when forming the n / i buffer semiconductor layer 105a, a DC voltage is superimposed on the first cathode electrode 221a by 0 V, the bias value is set to 0 V, and the first p / i buffer semiconductor layer 107a is -SiGe: H. The solar cell manufactured in this manner is referred to as Sample 2.

[0106]

[Table 2]

Comparative Example 2 A solar cell was manufactured under the same conditions as in Example 2 except that the polarity of the bias voltage of the cathode electrode was not changed when the buffer semiconductor layer was formed.

Specifically, in step (7), n / i
When forming the buffer semiconductor layer 105a, the DC voltage is not superimposed on the first cathode electrode 221a, and the bias value is set to -1.
0V, and in step (9), the second cathode electrode 22
The bias value was set to -100 V without superimposing a DC voltage on 1b. The solar cell manufactured in this manner is referred to as Comparative Sample 2.

(Evaluation) The same evaluation as in Example 1 and Comparative Example 1 was performed on each of Sample 2 obtained in Example 2 and Comparative Sample 2 obtained in Comparative Example 2. As a result, Comparative Sample 2
In comparison with the sample 2, the open-circuit voltage value was 1.18 times on average, the fill factor value was 1.1 times on average, and the photoelectric conversion efficiency η was 1.3 times on average. Further, the deterioration rate of Sample 2 was suppressed to 50% lower than that of Comparative Sample 2.

As described above, in the solar cell manufactured according to the present invention, the first p / i buffer semiconductor layer has a-SiGe:
Even in the case of H, the photoelectric conversion efficiency η is dramatically improved,
It was also found that the initial performance could be maintained for a long time.

(Example 3) As shown in Table 3, when forming the n / i buffer semiconductor layer 105a, in step (7), the DC voltage was not superimposed on the first cathode electrode 221a, and the bias value was not changed. A solar cell was manufactured under the same conditions as in Example 1 except that the voltage was changed to −10 V. The solar cell manufactured in this manner is referred to as Sample 3.

[0112]

[Table 3]

Comparative Example 3 A solar cell was manufactured under the same conditions as in Example 3 except that the polarity of the bias voltage of the cathode electrode was not changed when the buffer semiconductor layer was formed. Specifically, in step (9), the DC voltage is not superimposed on the second cathode electrode 221b, and the bias value is set to -1.
00V. The solar cell manufactured in this manner is referred to as Comparative Sample 3.

(Evaluation) The same evaluation as in Example 1 and Comparative Example 1 was performed for each of Sample 3 obtained in Example 3 and Comparative Sample 3 obtained in Comparative Example 3. As a result, Comparative Sample 3
Sample 3 has an open-circuit voltage value of 1.08 times on average, a fill factor value of 1.15 times on average, and a photoelectric conversion efficiency η
Was 1.2 times better on average. The deterioration rate of the sample 3 is
The deterioration rate was 36% lower than that of Comparative Sample 3.

As described above, in the solar cell manufactured according to the present invention, when forming the buffer semiconductor layer, the polarity of the bias voltage is made to be different from that of the semiconductor layer joined by lamination in the p / i buffer semiconductor layer. Even if applied only to
It was found that the photoelectric conversion efficiency η was dramatically improved and its initial performance could be maintained for a long period of time.

(Embodiment 4) In Embodiment 4, Embodiment 1
3 was set so that only one set of pin junctions was formed on the surface of the back reflection layer 103, but three sets of pin junctions were stacked. A stack of three sets of pin junctions is called a triple solar cell.

Table 4 shows the manufacturing conditions in Example 4. The stacking order of each semiconductor layer is from the upper column of Table 4 to the lower column.
In the fourth embodiment, the i-type semiconductor layer includes the first and second pi
In the n-junction, it is a-SiGe: H, and the third pi
In the n-junction, it is a-Si: H. In addition, the buffer semiconductor layer was not formed at the third pin junction on the light incident side, and the discharge generating means for forming the i-type semiconductor layer was RF discharge.

In forming the buffer semiconductor layer, the first p
For the in-junction, a DC voltage of +100 V is superimposed on the first cathode electrode when the first n / i buffer semiconductor layer is formed,
When forming the second p / i buffer semiconductor layer, a DC voltage of +200 V was superimposed on the second cathode electrode. Regarding the second pin junction, a DC voltage is superimposed on the first cathode electrode by 0 V when the first n / i buffer semiconductor layer is formed, and the bias value is set to 0 V.
When a second p / i buffer semiconductor layer was formed, a DC voltage of +200 V was superimposed on the second cathode electrode.

[0119]

[Table 4]

The manufacturing apparatus for manufacturing this triple type solar cell has a configuration in which a plurality of forming chambers for forming respective layers are newly added based on the manufacturing apparatus shown in FIG. That is, an n-type semiconductor layer, an n / i buffer semiconductor layer, an i-type semiconductor layer, a p / i buffer semiconductor layer, a p-type semiconductor layer, and an n-type semiconductor layer are provided between the p-type semiconductor layer formation chamber 508 and the winding chamber 503. Each of the chambers for forming the semiconductor layer, the i-type semiconductor layer, and the p-type semiconductor layer is connected to each other by a gas gate 518 and added.

Subsequently, the manufactured triple solar cell was
It was processed into unit modules using a continuous modularization device. The size of the unit module was 36 cm × 22 cm.

(Evaluation) An energy density of 100 mW / AM1.5 was applied to the unit module of this triple solar cell.
The photoelectric conversion efficiency η was determined by irradiating cm ² of pseudo sunlight. As a result, the photoelectric conversion efficiency η was 11.5% or more. In addition, the variation in characteristics between the unit modules is also 3
Within%.

Further, two of the processed unit modules are selected.
Individual pieces were taken out and subjected to a continuous bending test of 200 times. As a result, various characteristics did not deteriorate even after the test, and phenomena such as peeling of the deposited film were not observed. Further, the energy density is 100 mW / cm ^{2 at} AM1.5.
For 500 hours continuously. Even after this, the deterioration rate of the photoelectric conversion efficiency η was within 8.5% of the initial value.

Further, by connecting a large number of unit modules of the triple type solar cell, a power supply system with an output of 5 kW could be constructed.

(Example 5) As a material for forming the first p / i buffer semiconductor layer, a-SiG was used instead of a-Si: H.
e: A solar cell module was manufactured under the same conditions as in Example 4 except that H was used.

(Evaluation) The same characteristics as in Example 4 were evaluated for the processed solar cell module.
A photoelectric conversion efficiency of 2.2% or more was obtained, and the variation in characteristics between the respective solar cell modules was within 5%.
Further, even after the continuous bending test of 200 times, no deterioration of the characteristics was observed, and no peeling of the deposited film occurred. Furthermore, even after the continuous 500 hours of simulated sunlight irradiation,
The fluctuation of the photoelectric conversion efficiency was within 7.1% of the initial value. By using this solar cell module, a power supply system with an output of 5 kW could be configured.

(Example 6) As a material for forming the first p / i buffer semiconductor layer, a-Si: H was used instead of a-Si: H.
A solar cell module was manufactured under the same conditions as in Example 4 except that C: H was used.

(Evaluation) For the processed solar cell module, the same characteristics as in Example 4 were evaluated.
A photoelectric conversion efficiency of 7.4% or more was obtained, and the variation in characteristics between the respective solar cell modules was within 5%.
Further, even after the continuous bending test of 200 times, no deterioration of the characteristics was observed, and no peeling of the deposited film occurred. Furthermore, even after the continuous 500 hours of simulated sunlight irradiation,
The fluctuation of the photoelectric conversion efficiency was within 6.7% of the initial value. By using this solar cell module, a power supply system with an output of 5 kW could be configured.

[0129]

As described above, the method of manufacturing a photovoltaic device according to the present invention is characterized in that, when a discharge occurs for forming a buffer semiconductor layer, the polarity of an electrode facing a substrate for forming an adjacent sublayer is reduced. Are different from each other, or one of the potentials is set to 0 V, so that a p-type layer or a buffer semiconductor layer suitable for the band gap of the n-type layer can be formed. A buffer semiconductor layer that can effectively prevent thermal diffusion into the i-type layer during film formation can be provided at the pi interface and / or the ni interface, and the output characteristics, particularly the open-circuit voltage and fill factor, of the solar cell can be reduced. Thus, a solar cell with improved output characteristics can be provided.

Further, since an effective buffer semiconductor layer is provided at the pi interface and / or the ni interface, the diffusion of the dopant in the actual use state can be prevented, and the deterioration of the solar cell can be reduced. An improved solar cell can be provided.

In particular, in a stacked photovoltaic element,
An extremely good pn junction can be realized, and a higher-quality photovoltaic element can be uniformly formed with good reproducibility.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view schematically illustrating an example of a solar cell as a photovoltaic element manufactured according to the present invention.

FIG. 2 is a schematic cross-sectional view showing, in an enlarged manner, a formation chamber of a buffer semiconductor layer in FIG.

3 is a schematic schematic perspective view showing, in an enlarged manner, a chamber for forming an i-type semiconductor layer in FIG. 5;

FIG. 4 is a schematic cross-sectional view showing, in an enlarged manner, a chamber for forming an n-type semiconductor layer in FIG.

FIG. 5 is a schematic cross-sectional view schematically showing one example of a manufacturing apparatus used in the method for manufacturing a photovoltaic element according to the present invention.

[Explanation of symbols]

 Reference Signs List 101 solar cell (photovoltaic element) 102 substrate 103 back reflection layer 104 n-type semiconductor layer 105a, 107a first buffer semiconductor layer 105b, 107b second buffer semiconductor layer 106 i-type semiconductor layer 108 p-type semiconductor layer 109 transparent electrode 110 Current collecting electrode 111 Extraction electrode 201 Substrate 202 Formation chamber 203 Deposition container 204 Gas introduction tube 205, 206, 208 Infrared heater 207, 214, 215, 217 Thermocouple 209, 210, 212 Temperature controller 218 Gas gate 220 RF power supply 221 Cathode Electrode 301 Substrate 302 Film formation space 303 Applicator 304 Microwave permeable member 305 Exhaust punching board 306 Gas introduction tube 401 Substrate 402 Formation chamber 403 Film formation container 404 Gas introduction tube 405, 406 Infrared heater 40 7, 408 Thermocouple 409, 410 Temperature control device 411 Substrate support roller 412 Gas gate 413 Gate gas introduction tube 414 High frequency power supply 415 Electrode 501 Substrate 502 Delivery room 503 Winding room 504 to 508 Forming room 509 Delivery bobbin 510 Winding bobbin 511 , 512 transport roller 513 exhaust pipe 514 throttle valve 515 RF power supply 517 applicator 518 gas gate 519 gate gas introduction pipe 520 thermocouple 521 infrared heater 522 electrode 523 lamp house

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Naoto Okada 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Koichiro Moriyama 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon (72) Inventor Hiroshi Shimoda 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor O ▲ saki ▼ Hiroyuki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon stock Inside the company (72) Inventor Masahiro Kanai 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc.

Claims (7)

[Claims] A step of introducing a material gas into a discharge space of a reaction vessel, decomposing the material gas by plasma discharge, and forming a non-single-crystal semiconductor layer on the substrate; It has one pin junction, n-type layer and i
In a method of manufacturing a photovoltaic device having a buffer semiconductor layer composed of a plurality of sublayers between a mold layer and / or between an i-type layer and a p-type layer, at least one of the buffer semiconductor layers having the multilayer structure The polarity of the electrode facing the substrate for forming one sublayer and the electrode facing the substrate for forming a sublayer adjacent to the one sublayer when a discharge occurs to form one of the sublayers And making the potential of one of the electrodes 0 V. 2. A method for manufacturing a photovoltaic element, comprising: 2. The method according to claim 1, wherein at least a part of the buffer semiconductor layer is a
The method for manufacturing a photovoltaic device according to claim 1, wherein the photovoltaic device is formed of -Si: H. 3. The method according to claim 1, wherein at least a part of the buffer semiconductor layer is a
The method for manufacturing a photovoltaic device according to claim 1, wherein the photovoltaic device is formed of -SiGe: H. 4. At least a part of the buffer semiconductor layer is a
The method for manufacturing a photovoltaic device according to claim 1, wherein the photovoltaic device is formed of -SiC: H. 5. The method for manufacturing a photovoltaic device according to claim 1, wherein the photovoltaic device is a solar cell. 6. The light according to claim 1, wherein, in the step of forming the non-single-crystal semiconductor layer, the substrate is moved through a plurality of deposition spaces each having a discharge unit. A method for manufacturing an electromotive element. 7. The method according to claim 1, wherein the substrate is a band-shaped substrate.