JP2000099712A - Method and device for parallel processing of multi- channel data and recording medium recording the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to execute a high speed processing for multi-channel data. SOLUTION: In a data broadcast transmitting part 100, a data receiver 101 individually receives multi-channel data first and a broadcast transmitter 102 transmits the received data to plural processors 200 in a broadcast manner. Then, in the processors 200, a writer 203 writes the broadcast channel data in memory areas allocated to individual channel data in a writing memory of one of memories 201, 202. Then, the other memory out of these memories 201, 202 is a reading memory for a processing part 205. Then, the writing memory and the reading memory are switched by a switch 204 at prescribed timing. As the example of switching timing is the timing when the writing of a series of channel data is finished. Then, the processing part 205 reads optional data from the reading memory and executes its processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing for high-speed processing of multi-channel data such as image data in panoramic imaging and multi-point imaging using a plurality of cameras, and audio data in audio stereo and stereophonic sound. The present invention relates to a processing method and apparatus.

[0002]

2. Description of the Related Art As typical multi-channel data parallel processing devices, there are a shared memory type parallel processing device and a distributed shared memory type parallel processing device.

FIG. 11 shows an example of a shared memory type parallel processing device when multi-channel data is image data.
In a shared memory type parallel processing device, processing is performed by accumulating data in one memory shared by a plurality of processors. First, image data from a plurality of cameras is collected and stored in a shared memory. Each processor reads necessary image data from the shared memory and performs processing. In the shared memory type parallel processing device, a plurality of processors can use the processing result only by writing the processing result to the shared memory once, and the processor can be used efficiently.

On the other hand, FIG. 12 shows an example of a distributed shared memory type parallel processing device when multi-channel data is image data. In a distributed shared memory type parallel processing device, data is distributed and stored in a plurality of processor memories, and each processor performs processing as if they were virtually one shared memory. Since a plurality of small memories are used in a distributed manner, the cost is low, and the reliability against a memory failure or the like is high. When an image to be processed exists in the memory of another processor, each processor performs communication between the processors and reads necessary image data. There is no need for inter-processor communication if all are in its own memory.

[0005]

In the above-described conventional shared memory type parallel processing device, the processor enables the use of a plurality of processors by writing the processing result to the shared memory only once, but the plurality of processors are simultaneously operated. The same processing result cannot be read. Since the memory access is performed sequentially for each processor, if the reading of a plurality of processors occurs at the same time, a delay occurs until the reading of the other processor is completed, and the efficiency of the parallel processing decreases.
In addition, while the processor is writing the processing result to the shared memory, other processors cannot read the processing result, causing a delay, and reducing the parallel processing speed. In addition, these delays differ depending on the accessed processor and are not constant, so that the processing scheduling of each processor becomes complicated. When real-time processing such as moving image processing is required, it is difficult to secure real-time processing.

On the other hand, in the case of the above-described conventional distributed shared memory type parallel processing device, since each processor performs processing by virtually implementing one shared memory, a plurality of processors are provided in the same manner as in the above described shared memory type parallel processing device. When the processors simultaneously access the memory, a delay occurs, and the efficiency of parallel processing decreases. In addition, while using a small number of small memories in a distributed manner to reduce costs and improve reliability against memory failures, the processor needs to write processing results to a plurality of memories. Also requires access to a plurality of memories, which reduces the efficiency of parallel processing. In addition, if simultaneous access to the memory of multiple processors occurs, delays occur in the distributed memories, so the processing scheduling of each processor becomes more complicated than the shared memory parallel processing method, and real-time performance is ensured. Is difficult.

An object of the present invention is to provide a parallel processing method and apparatus for processing multi-channel data at high speed, which solves the problems of the conventional method.

[0008]

The present invention solves the above-mentioned problems by means listed below.

One means is to individually receive multi-channel data and to broadcast the received individual channel data to a plurality of processors, and to independently write in each of the processors. , One of which is for writing channel data and the other is for memory of processor access.
Writing the broadcasted channel data to a memory area allocated to the individual channel data in the channel data writing memory;
A method of switching between the channel data writing memory and the processor access memory, and a step of reading and processing arbitrary data from the processor access memory. .

Alternatively, the multi-channel data is individually received, and the received individual channel data is transmitted to a plurality of processors in a broadcast manner, or the plurality of processors individually transmit the processor data to another processor. Broadcasting; and within each of said processors:
Two channels of memory that can be independently written and read are provided, one for writing channel data and processor data and the other as memory for processor access, and the individual channel data or memory in the channel data and processor data writing memory. Writing the broadcasted channel data or processor data to a memory area allocated to each processor data; switching between the channel data and processor data writing memory and the processor access memory; Reading arbitrary data from the processor access memory and processing the data; writing arbitrary data to a memory area of the processor access memory allocated to the processor; And a step of transmitting data to processor data as a broadcasting manner to other processors is parallel processing method of multi-channel data, characterized in that it comprises.

[0011] Alternatively, receiving means for individually receiving multi-channel data, transmitting means for individually transmitting the received channel data to a plurality of processors, and independent writing and writing in each of the processors. Two types of memories that can be read, one for writing channel data and the other for processor access, and a memory area assigned to each channel data in the channel data writing memory. Writing means for writing the broadcasted channel data; switching means for switching between the memory for writing the channel data and the memory for accessing the processor; and reading and processing arbitrary data from the memory for accessing the processor. And processing means. A parallel processing apparatus Yan'nerudeta.

Alternatively, the two memories have a memory area assigned to each processor, and the processing means has a function of writing processor data to the memory area assigned to the processor. Transmission means for broadcasting the processor data written by the processing means to another processor, and transmitting the processor data broadcast from the other processor to the channel data writing means. A multi-channel data parallel processing device, comprising: receiving means for writing in a memory area allocated to the other processor in the memory of (1).

Alternatively, there is provided a multi-channel data parallel processing apparatus characterized in that one or both of the two multi-channel data parallel processing apparatuses are connected.

Further, there is provided a multi-channel data parallel processing method characterized in that a program for causing a computer to execute the steps in the multi-channel data parallel processing method is recorded on a computer-readable recording medium. It is a recording medium on which recording is performed.

By the above means, the present invention enables parallel processing for processing multi-channel data at high speed.

That is, means / stages for individually receiving multi-channel data and transmitting the received data to a plurality of processors, and a memory area allocated to each channel data in each processor. The means / steps for writing data to the memory enable data sharing, ie, memory sharing, by copying individual channel data to multiple processor memories. For example, the reading of the image data A by the processor A and the reading of the image data A by the processor B can be performed simultaneously without interfering with each other, and there is no delay due to simultaneous access by the processors. Further, since the image data is multiplexed and stored in the memories of the processors A and B,
High reliability against memory failure and the like.

On the other hand, the means / stage for switching between the write memory and the read memory allows simultaneous writing of broadcast channel data and reading of the processor, thereby enabling efficient parallel processing. For example, when 30 frames of image data are broadcast from the camera to the processor memory per second, the image data is written to the write memory, and then the write memory and the processor access memory are synchronized with the image data frame. By switching the mode, the processor can read arbitrary data including the image data from the processor access memory while writing the next broadcast image data to the writing memory. And reading of the processor at the same time.

The means / step for writing data to the memory area allocated to each processor by the processor and the means / step for broadcasting the written data to another processor are efficient. Enables interprocessor communication. For example, the processor A can broadcast the processing result to the processor B by writing the processing result to the inter-processor broadcast memory, and the processor B can broadcast the processing result to the processor A by writing the processing result to the inter-processor broadcast memory. it can.

Further, by connecting a plurality of parallel processing devices for multi-channel data, a high-speed parallel processing network capable of performing complicated processing can be constructed. For example, when two multi-channel data parallel processing devices are connected in series, the depth measurement of the object can be performed by the preceding parallel processing device, and the object recognition processing can be performed by the subsequent parallel processing device.

As described above, according to the present invention, when a plurality of processors simultaneously access the memory, the delay can be minimized only in the memory write time and the read time.
Real-time processing is easy, and efficient parallel processing is possible. Further, efficient inter-processor communication can be performed, and parallel processing for processing multi-channel data at high speed is enabled. Also, since multiple parallel processing devices for multi-channel data can be connected as modules,
The scale of the system can be easily changed according to the application.

As for the multi-channel broadcast communication method, either a software method using a network protocol or the like or a hardware method using a crossbar switch or the like is possible.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

<Embodiment 1> FIG. 1 is a block diagram of a first embodiment illustrating a basic parallel processing system of the present invention.

The multi-channel data parallel processing device of this embodiment comprises a plurality of data broadcasting units 100 and a plurality of processors 200. Each data broadcast transmission unit 100
Comprises a data receiver 101 for individually receiving multi-channel data, and a broadcast transmitter 102 for broadcasting the received channel data to a plurality of processors 200. Each processor 200 has two memory systems 20 each having a memory area allocated to each channel data and switchable between writing and reading.
1, 202 and the broadcasted channel data
01, 202, a writer 203 for writing to a memory area allocated in the write memory, a switch 204 for alternately switching between the write memory and the read memory, and arbitrary data from the switched read memory. A processing unit 205 for reading and processing.

FIG. 2 is a flowchart showing a parallel processing method having the above configuration.

First, in the data broadcast transmitting section 100,
The multi-channel data is individually received, and the received data is broadcast to a plurality of processors 200. Next, in the processor 200, the broadcaster writes the broadcasted channel data to the memory area allocated to each channel data in the write memory. Next, the switch 204 switches the write memory and the read memory at a predetermined timing. As an example of the switching timing, it is assumed that writing of a series of broadcast channel data has been completed and reading has not been performed. Next, the processing unit 205 reads arbitrary data from the reading memory and processes it.

In the data broadcast transmitting section 100,
A broadcast transmitter 102 that receives multi-channel data individually and broadcasts the received data to a plurality of processors.
In the processor 200, the data writer 203 that writes data to the memory area allocated to each channel data enables the data to be shared by copying the channel data to the memory in the plurality of processors 200. I have. That is, the memory of each processor can function as a shared memory of the entire parallel processing device.

For example, in the case of the configuration shown in FIG. 3, the reading of the image data A by the processor A and the reading of the image data A by the processor B can be performed at the same time without interfering with each other. No delay occurs. Further, since the image data is multiplexed and stored in the memories of the processors A and B, the reliability against the memory failure or the like is high.

On the other hand, the switching unit 204 is configured such that one of the two independent memories is used as a memory for writing channel data, and the other is used as a memory for reading the processing unit 205, and a memory for reading and a memory for reading are used as a series of channel data. Since the switching is alternately performed every time the data is written, the writing of the broadcast channel data and the reading of the processor can be performed at the same time, and efficient parallel processing becomes possible. For example, as shown in FIG.
When the image data of a frame is broadcast to the memories of the processors A and B, the writing memory and the reading memory are switched by the frame synchronization timer in synchronization with the image data, so that the writing of the broadcast image data can be performed. The reading of the processor can be performed simultaneously.

As described above, according to the present invention, when a plurality of processors simultaneously access the memory, the delay can be minimized only in the memory write time and the read time.
Real-time processing is easy, and efficient parallel processing is possible.

<Embodiment 2> FIG. 5 is a block diagram of a second embodiment illustrating a parallel processing system of the present invention.

In FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description will be simplified. In the present embodiment, the processors 210 include the memories 211 and 212.
Is a memory used for switching between writing of channel data or broadcast data from another processor and for accessing the processor. In addition to the memory area allocated to each channel data, It has individually allocated memory areas. The broadcast transceiver 213 is provided for each processor 2.
Of the memory for processor access among the memories 211 and 212 allocated to the processor 10
When the processing unit 205 writes data to the memory area allocated to 0, the processing unit 205 broadcasts the written data to another processor. This is means for writing to a memory area allocated to the processor in the writing memory.

FIG. 6 is a flowchart showing a parallel processing method having the above configuration.

First, in the data broadcasting section 100,
The multi-channel data is individually received, and the received data is broadcast to a plurality of processors 210. Alternatively, the data of the processing result in a certain processor is broadcast to another processor. Next, in the processor 210, the writer 203 writes the broadcasted channel data to the memory area allocated to each channel data in the write memory. Alternatively, broadcast data from another processor is written by the broadcast transceiver 213 to a memory area allocated to the processor in the write memory. Next, the memory for writing and the memory for processor access are switched at a predetermined timing. As the switching timing, the writing of a series of broadcast channel data or a series of broadcast data from another processor is completed, and
5 and the broadcast transmission / reception by the broadcast transceiver 213 is not performed. Next, the processing unit 205 reads and processes arbitrary data from the processing unit access memory. Next, the processing unit 205 writes arbitrary data such as a processing result in a memory area of the processor access memory allocated to the processor 210. Next, the broadcast transceiver 213 broadcasts the data written in the memory area allocated to the processor 210 by the processing unit 205 to another processor.

As described above, in this embodiment, in addition to the operation of the first embodiment, efficient inter-processor communication can be performed, and parallel processing for processing multi-channel data at high speed is possible. become. That is, the processing unit 205 of the processor writes the broadcast data from the processor into the memory area allocated to each processor, and transmits the data written by the processing unit 205 to another processor. The notification transceiver 213 enables efficient inter-processor communication.

<Embodiment 3> FIG. 7 is a block diagram of a third embodiment for explaining a parallel processing system of the present invention.

In this embodiment, a high-speed parallel processing network can be constructed by connecting one or both of the multi-channel data parallel processing devices shown in the first and second embodiments. It is characterized by the following.

As a connection method, it is possible to connect in series as shown in FIG. 7A and in a network as shown in FIG. 5B.

As described above, complex processing can be performed by connecting a plurality of parallel processing devices for multi-channel data. Further, since a plurality of parallel processing devices for multi-channel data can be connected as a module, the scale of the system can be easily changed according to the application.

<Embodiment 4> FIG. 8 is a block diagram of a fourth embodiment of the present invention relating to a parallel processing apparatus when multi-channel data is image data.

The three cameras 300A, 300B, 300
This is an example of a parallel processing device that extracts an image of an arbitrary area requested by two terminals from a panoramic image captured in C.

In FIG. 8, the image transmission units 120A, 120A
Reference numeral 121 in 0B and 120C denotes an image receiver for receiving an image, and 122 denotes a broadcast transmitter for broadcasting the received image data. Processors 220A, 2 constituting each terminal
Reference numerals 221 and 222 in the memory 20B are memories for storing image data, and 223 is a memory 22 for storing broadcast channel data.
A writer 224 for writing to a memory area allocated in the write memory of the write memories 122 and 222
A switch 226 for alternately switching between 21 and 222 for writing and reading is a frame synchronization timer 226 that generates a signal synchronized with frame switching of an image. 225
Is a processing unit that extracts and processes an image of an arbitrary area requested by the terminal, and 227 is an input / output interface with the display device 228 of each terminal.

Since the panoramic image data is transmitted by the broadcast transmitter 122 to the processors 220A and 220B and stored in the memory switched to the writing side of each processor, the processors 220A and 220B
The access to the image data from the processing unit 225 can be performed simultaneously without interfering with each other. Since simultaneous access is possible even when the number of processors increases, a large number of users can access a large image such as a panoramic image at the same time with this configuration.

The switch 224 uses one of the memories as a memory for writing channel data and the other memory as a memory for reading the processing unit 225, and alternates each time frame data is written by a timer signal from the frame synchronization timer 226. , The frame data is written to the memory by the broadcast transmitter 122 and the processing unit 22
5 can be read at the same time, and high-speed processing with little delay can be performed.

As described above, this embodiment has an advantage that real-time processing is easy and a plurality of images can be efficiently processed in parallel.

Although the embodiment in which the multi-channel data is image data has been described above, the present invention is applicable to multi-channel data such as voice / sound data and general data.

<Embodiment 5> FIG. 9 shows a fifth embodiment of the present invention relating to a parallel processing apparatus when multi-channel data is image data. Two cameras 300
A, is an example of a parallel processing device that measures the depth of an object captured from a stereo image captured in 300B.

In FIG. 9, in the right-eye image transmitting section 130A and the left-eye image transmitting section 130B, 131 is an image receiver for receiving an image, and 132 is a broadcast transmitter for broadcasting the received image data. Further, the processors 230A, 230
In B, 231 and 232 are memories for storing broadcast image data and broadcast data between processors.
Reference numerals 2311 and 2321 denote memories for storing right-eye image data, 2312 and 2322 denote memories for storing left-eye image data, 2313 and 2323 denote memories for broadcasting between processors, and memories for storing processor A data.
Reference numerals 2314 and 2324 denote memories for broadcasting between processors, which are memories for storing processor B data.
Reference numeral 233 denotes a writer for writing the broadcasted right-eye and left-eye image data to a memory area allocated in the write memory of the memories 231 and 232;
A switch 4 alternately switches between the memories 231 and 232 for writing image data and accessing the processing unit. Reference numeral 235 denotes a processing unit for calculating the depth of the object. Reference numeral 236 denotes a processing unit 235.
The data written in the memory area allocated to the processor of the terminal is transmitted to another processor by broadcasting, and the data allocated to the processor is received by receiving the broadcast data from the other processor. A broadcast transceiver that writes to the area.

The right-eye image data and the left-eye image data are transmitted to the processors 230A and 230B by the broadcast transmitter 132 and stored in the memories of the processors 230A and 230B.
Access to the image data of B can be performed simultaneously without interfering with each other. Also, the processor 230A
And 230B are the broadcast memory 231 between the processors.
Since processing results can be exchanged through 3,2314, 2323, and 2324, efficient parallel processing is possible.

The switch 234 uses one of the memories 231 and 232 as a memory for writing image data and the other as a memory for access (reading and writing) of the processing unit 235, and alternately switches each time image data is written. The writing to the memory and the reading of the processing unit 235 by the broadcast transmitter 132 can be performed at the same time, and high-speed processing with little delay becomes possible. That is, the processor 230A writes the processing result into the processor A data memory for broadcasting between the processors, thereby executing
30B, and the processor 230B can broadcast the processing result to the processor 230A by writing the processing result to the processor B data memory for broadcast communication between the processors.

As described above, this embodiment has an advantage that real-time processing is easy and a plurality of images can be efficiently processed in parallel.

Although the embodiment in which the multi-channel data is image data has been described above, the present invention is also applicable to multi-channel data such as voice / sound data and general data.

<Embodiment 6> FIG. 10 shows a sixth embodiment of the present invention relating to a parallel processing apparatus when multi-channel data is image data. An example of a parallel processing device that measures the depth of an object captured from stereo images captured by two cameras, performs three-dimensional matching based on the depth information, recognizes the object, and extracts a target object. is there.

In FIG. 10, reference numerals 400 and 410 denote parallel processing units for multi-channel data of the present invention having two channels for both input and output, and the parallel processing unit 400 operates from the right-eye image and the left-eye image to the depth according to the fifth embodiment. The parallel processing device 410 that obtains information performs an object recognition process from depth information with the same configuration.

In the parallel processing device 400, the right-eye image data and the left-eye image data are broadcasted to the processors A and B inside the parallel processing device 400 by the broadcast transmitter.
The same processing as in the embodiment is performed. Processor A,
The output of B is transmitted to the corresponding depth information transmission unit of the parallel processing device 410. In the parallel processing device 410,
Each of the depth information transmitting units broadcasts the depth information of the processors A and B to the processors C and D in the parallel processing device 410, and performs three-dimensional matching based on the depth information to recognize the object. In each of the processors C and D, a target object is extracted.

As in the present embodiment, since the recognition processing is further added to the configuration of the fifth embodiment, even if the processing becomes complicated, multi-channel data parallel processing devices are connected in multiple stages. This allows efficient parallel processing.

Further, since a plurality of parallel processing devices for multi-channel data can be connected as modules, the scale of the system can be easily changed according to the complexity of the processing.

Although the embodiment in which the multi-channel data is image data has been described above, the present invention is applicable to multi-channel data such as voice / sound data and general data.

As shown in FIG. 7B, a parallel processing device for multi-channel data can be connected in a network form, and a complicated parallel processing circuit network such as a neural network can be constructed.

<Embodiment 7> FIGS. 1, 5, 8, and 9
Needless to say, some or all of the functions of the respective units described using the above-described methods can be implemented using a computer, or the steps of the processing illustrated in FIGS. 2 and 6 can be executed by a computer. Therefore, a program for realizing the function of each part by the computer or a program for executing the processing stage by the computer is stored in a computer-readable recording medium such as an FD (floppy disk) or an MO. , ROM, memory card, CD, DVD,
It can be recorded on a removable disk or the like, provided, and distributed.

[0061]

As described above, according to the present invention, first,
The multi-channel data is individually received, the received data is transmitted to a plurality of processors in a broadcast manner, and then, in the processor, the data is written in a memory area allocated to each of the channel data, and the external data By switching between the write memory and the internal access memory alternately every time data is written, and reading and processing arbitrary data from the internal access memory, multi-channel data can be processed in parallel at high speed. It is suitable when necessary. Further, since the delay can be minimized only in the memory write time and the read time, the processing scheduling of each processor is easy.

Further, the processor writes data in a memory area allocated to each processor, and transmits the written data to other processors in a broadcast manner, so that the delay is minimized and the efficiency is reduced. It also has the advantage of enabling efficient interprocessor communication, and enables complex parallel processing.

Further, by connecting a plurality of parallel processing devices for multi-channel data, there is an advantage that a high-speed parallel processing network can be constructed, the connection form can be changed according to the processing, and the expandability is excellent. I have.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment illustrating a basic parallel processing system according to the present invention.

FIG. 2 is a flowchart illustrating a parallel processing method according to the first embodiment.

FIG. 3 is a diagram showing an example for explaining the operation of the first embodiment.

FIG. 4 is a diagram showing another example for explaining the operation of the first embodiment.

FIG. 5 is a configuration diagram of a second embodiment illustrating a parallel processing system to which an inter-processor communication function according to the present invention is added.

FIG. 6 is a flowchart illustrating a parallel processing method according to the second embodiment.

FIGS. 7A and 7B are configuration diagrams of a third embodiment illustrating a parallel processing system in which a plurality of parallel processing devices of the present invention are connected.

FIG. 8 is a configuration diagram illustrating a fourth embodiment of the present invention.

FIG. 9 is a configuration diagram illustrating a fifth embodiment of the present invention.

FIG. 10 is a configuration diagram illustrating a sixth embodiment of the present invention.

FIG. 11 is an explanatory diagram of a conventional technique relating to a shared memory type parallel processing method.

FIG. 12 is an explanatory diagram of a conventional technique relating to a distributed shared memory type parallel processing method.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 data broadcast transmitter 101 data receiver 102 broadcast transmitter 120A, 120B, 120C image transmitter 121 image receiver 122 broadcast transmitter 130A right-eye image transmitter 130B left-eye image transmitter 131 ... Image receiver 132 ... Broadcast transmitter 200 ... Processor 201,202 ... Memory 203 ... Writer 204 ... Switcher 205 ... Processor 210 ... Processor 211,212 ... Memory 213 ... Broadcast transmitter / receiver 220A, 220B ... Processor 221, 222 ... Memory 223 ... Writer 224 ... Switcher 225 ... Processor 226 ... Frame synchronization timer 227 ... I / O interface 228 ... Display device 230A, 230B ... Processor 231,232 ... Memory 2311, 1212, 2321, 232 ... Image Data memory 313,2314,2323,2324 ... Broadcast memory 233 ... write 234 ... switch 235 ... processing unit 236 ... broadcast transceiver 300A, 300B, 300C ... camera 400, 410 ... parallel processing device

Continuing on the front page (72) Inventor Kenji Nakazawa 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Co., Ltd. F-term (reference) in Nippon Telegraph and Telephone Corporation 5B045 AA01 BB04 DD01 DD02 GG11 5B057 CH02 CH04 CH11 CH14

Claims (6)

[Claims] 1. Receiving multi-channel data individually,
Transmitting the received individual channel data to a plurality of processors in a broadcast manner; and, within each of the processors, comprising two systems of memories capable of independently writing and reading, one of which is used for writing channel data. Writing the broadcasted channel data into a memory area allocated to the individual channel data in the channel data writing memory, using the other as a processor access memory; A method of switching between a memory and the processor access memory; and a step of reading and processing arbitrary data from the processor access memory. 2. Receiving multi-channel data individually,
Broadcasting said received individual channel data to a plurality of processors, or said plurality of processors broadcasting processor data individually to other processors; A memory for writing channel data and processor data, and a memory for accessing the processor, one for writing channel data and processor data. Or writing the broadcasted channel data or processor data to a memory area allocated to each processor data, and switching between the channel data and processor data writing memory and the processor access memory Reading arbitrary data from the processor access memory and processing the data; writing arbitrary data to a memory area of the processor access memory allocated to the processor; and writing the written data to the processor. Transmitting the data as broadcast data to another processor. 3. A receiving means for individually receiving multi-channel data, a transmitting means for individually transmitting the received channel data to a plurality of processors, and independently writing and writing in each of the processors. Two memory systems that can be read, one memory for writing channel data and the other for processor access, and a memory area allocated to each channel data in the memory for writing channel data. Writing means for writing the broadcasted channel data; switching means for switching between the channel data writing memory and the processor access memory; and reading and processing arbitrary data from the processor access memory And a processing means. Parallel data processing unit. 4. The two-system memory has a memory area assigned to each of the processors, and the processing means has a function of writing processor data to the memory area assigned to the processor. Transmission means for broadcasting the processor data written by the processing means to another processor, and transmitting the processor data broadcast from the other processor to the channel data. 4. A multi-channel data parallel processing apparatus according to claim 3, further comprising a receiving means for writing in a memory area allocated to said other processor in said memory. 5. A parallel processing device for multi-channel data, wherein one or both of a parallel processing device for multi-channel data according to claim 3 and a parallel processing device for multi-channel data according to claim 4 are connected. . 6. A program for causing a computer to execute the steps in the method for parallel processing of multi-channel data according to claim 1 or 2 on a recording medium readable by the computer. Recording medium recording the parallel processing method.