JP2000099189A - Clock controller and clock skew adjusting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock controller and a clock skew adjusting method which is capable of performing precise clock control for every block. SOLUTION: This device is provided with a low level latch 120 inputting a clock 103 to an enable terminal E after the passage of a delay buffer for delaying an input clock, OR gate 110 for outputting the OR signal of a first clock control signal 101 generated inside the block and a second clock control signal 102 generated outside the block to the D input of the low level latch 120, logic inverter gate 130 for logically inverting the output of the low level latch 120, and AND gate 140 for making the AND output of the clock 103 and the output from the logic inverter gate 130 a block operating clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control device for controlling a clock of a processor operating at a high speed, and a clock skew adjusting method for adjusting a clock skew between blocks.

[0002]

2. Description of the Related Art In recent years, design technology, process technology, CAD tool technology, etc., surrounding LSIs have made remarkable progress.
The processing performance required for the LSI will only increase, but will not decrease. Accordingly, the operating speed of the processor has been dramatically increased. In addition, the world is aiming for low energy consumption, and the power consumption of a processor is no exception.

In the case of a CMOS circuit, the power consumption of a processor is proportional to (frequency) × (capacitance) × (voltage) × (voltage) (for example, “Technical White Paper for Low-Power LSI” (Nikkei B)
(See P57 issued by Company P)), at the level of the processor architecture, efforts are made to reduce the (frequency) term. Although it is one idea to lower the frequency as a whole, the required amount of processing is large at present, and it can be said that it is not acceptable to operate the processor as a whole at low speed. Therefore, it can be said that fine clock control such as distributing the clock only when it is really necessary in the processor and operating only the really necessary block is essential for reducing the power consumption.

In this case, it is desirable that the clock can be controlled (stopped) more. Furthermore, in order to basically inactivate more clock lines, it is desirable to be able to stop at the base of the clock generator in the processor.
An outline of a conventional control method is shown. FIG. 11 shows a clock generator in the processor and a block group to which the clock is to be distributed. FIG. 12 is a timing chart showing how the clock is controlled.

In FIG. 11, reference numeral 1 denotes the entire processor;
Is a clock generating unit, 3, 4, and 5 are blocks that operate upon receiving a clock, 6 is a clock source, 10 is a clock source, 20 is an operating clock, a clock (non-gated) input to a flip-flop, and 30 is " A clock control signal for stopping the clock when it is 1 "; a delay adjusting buffer 40 for reducing clock skew between blocks;
50 is a flip-flop in each block, and 51 is a flip-flop that outputs the clock control signal 30.

The original clock 10 and the operation clock 20 are delayed by a time A. This is because the clock skew is adjusted. Since the clock distribution is not homogeneous and the arrival time differs for each block,
The clock phase does not match between the blocks (clock skew occurs). Therefore, in order to reduce the delay difference between blocks (to make it 0), the delay adjustment buffer 40
Change the size and number of, and adjust the delay. At this time, it will match the slowest block.

It is assumed that the condition for stopping the clock in a certain cycle (cycle A in FIG. 12) is satisfied. Then, the control signal 30 becomes "1" after some delay time from the rising edge of the operation clock, and the control signal 30 tries to stop the original clock 10 (clock stop in cycle B). The margin for that is time B. It takes time B for the control signal 30 to reach the AND gate 2a of the clock generator 2.
Otherwise, a short pulse is generated in the clock, and the operation of the processor cannot be guaranteed. In order to perform the clock control correctly, it is preferable that the time B is as large as possible. For that purpose, various attempts have been made to reduce the time A as much as possible.

By controlling the clock at the output stage of the clock generator 2 as described above, the clock operation in the chip can be almost stopped if necessary, which has a great effect on reducing power consumption. However, with the recent sophistication of processors, the conventional technology has often been unable to cope with the problems.

[0009] With the advancement of functions, the number of blocks as shown in FIG. 11 has increased. Therefore, the efficiency has been deteriorated in the intensive control (clock control is performed only by the clock generation unit). That is, while there is almost no timing at which a plurality of blocks all stop at the same time,
At most timings, some blocks no longer need to operate.

[0010] Further, as the speed is increased, the cycles A and B become shorter, and it becomes difficult to control the clock in the clock generator (FIG. 13). That is, if the process rule does not change, the time A does not change, but the time B surely decreases, and it becomes difficult to stop the clock in the cycle B. As described above, the conventional configuration has a problem that the clock cannot be controlled to reduce the power consumption when the functions and speed of the processor have been improved.
In other words, the clock control of a processor operating at high speed has strict timing when trying to control the clock source, making it impossible to perform fine control, and is not suitable for reducing power consumption.

In view of the above, it is an object of the present invention to provide a clock control device capable of performing fine clock control for each block and a clock skew adjustment method for efficiently using the clock control device. And

[0012]

According to a first aspect of the present invention, there is provided a clock control device, comprising: a delay element for delaying an input clock input to a block; and a low-level latch for inputting a clock after passing through the delay element to an enable terminal. An OR element for outputting a logical sum signal of a first clock control signal generated inside the block and a second clock control signal generated outside the block to a D input of the low level latch, and an output of the low level latch And a logical AND element that outputs the logical product of the clock after passing through the delay element and the logical inverting element output as a block operation clock.

According to the clock control device of the first aspect, with respect to the clock control of the processor operating at high speed, it is possible to prepare a clock control cell which can handle global control and local control in a unified manner. The timing design becomes easy by incorporating it into the design flow. As a result, efficient clock control can be realized, which greatly contributes to low power consumption of the processor.

According to a second aspect of the present invention, there is provided a clock control device according to the first aspect, wherein the low level latch, the OR element, the AND element, and the logical inversion element are configured in one clock control cell. is there. According to the clock control device of the second aspect, the same effect as that of the first aspect is obtained. 4. The clock control device according to claim 3, wherein a delay element for delaying an input clock input to the block, and a clock after passing through the delay element is input to an enable terminal and a first clock control signal generated in the block. And a second low-level latch that inputs the clock after passing through the delay element to the enable terminal and inputs the second clock control signal generated outside the block to the D input. A latch, a first logical inversion element for logically inverting the output of the first low-level latch, a second logical inversion element for logically inverting the output of the second low-level latch, and a clock after passing through the delay element , And an AND element that outputs the logical product of the output of the first logical inversion element and the output of the second logical inversion element as a block operation clock.

According to the clock control device of the third aspect, the same effect as that of the first aspect is obtained. According to a fourth aspect of the present invention, in the clock control apparatus according to the third aspect, the first low-level latch, the second low-level latch, an AND element,
The first logic inversion element and the second logic inversion element are configured in one clock control cell. According to the clock control device of the fourth aspect, the same effect as that of the first aspect is obtained.

According to a fifth aspect of the present invention, there is provided a clock skew adjusting method for adjusting a clock skew between blocks, wherein a clock tree adjusting delay element is provided in each block when creating netlist data in each block. A full-chip layout is performed so that the clock control cell is placed immediately after the input and the delay element, and the clock skew value between each block is calculated with this layout. The clock skew value is reduced by replacing cells with cells having the same outer shape but different delay values.

According to the clock skew adjustment method of the present invention, the skew adjustment can be easily realized as a layout by treating the clock control cell as a skew adjustment cell.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a clock control device according to the present invention will be described below with reference to FIGS. First, a clock control cell that can be used for clock control in units of blocks will be described. 1 and 2 are used. 100 and 200 are clock control cells of different forms from each other. 101, 102, 201, and 202 are clock control signals that become "1" when the clock is to be stopped, and 103 and 203 are clock control cells 100 and 200.
, A clock after passing through the delay buffer, 110 is an OR gate, 105 is an output signal of the OR gate 110, and 120, 220, 221 are input D = output Q when the clock 103 or 203 is "0". , Low-level latches, 130, 230, and 231 are logical inversion gates, 140 and 240 are logical product gates, and 104 and 204 are stop-controlled clocks. As shown, the output signal 105 of the OR gate 110 is input to the input D of the low-level latch 120, the clock 103 is input to the enable terminal E, and the clock control signals 201 and 202 are input to the input D of the low-level latches 220 and 221. And the clock 203 is input to the enable terminal E.

As shown by the clock control cell 200, a cell in which a plurality of low-level latches corresponding to control signals from the outside of the cell are prepared can be considered. In this embodiment, two low-level latches are provided. Only those shown. Even if the number of control signals becomes three or more, the following description similarly applies. The timing of these cells is adjusted as follows. That is, in the 100 clock control cells, the output of the logical inversion gate 130 (denoted as 140.A) input to the AND gate 140 and the clock 103
(Denoted as 140.B) is the AND gate 140
Is to prevent glitches from being output. In other words, AND gate (130) 140. The signal change of A is always clock (103) 140. B is to be generated in the row section of B. Specifically, 140. In the case where A rises at the fastest speed, as shown in FIG. B. In order to avoid falling of B, In the case where A rises at the latest, as shown in FIG. The timing is adjusted so that the rising of B does not occur.

In the 200 clock control cells, the relationship between inputs A and B of AND gate 240 is 140. A and 140. B
, And similarly, the relationship between inputs A and C of AND gate 240 is 140. A and 140. The timing is made so as to be the same as the relationship of B. The operation of the clock control cell is as follows.

FIG. 5 shows the configuration of the clock input port in block units. 310 is a clock from the clock generator,
Reference numeral 340 denotes a delay element for receiving the clock 310, for example, a delay buffer, which also has a role of adjusting skew between blocks. A control signal 330 is generated outside the block and becomes “1” when the clock is stopped, 100 is a clock control cell, and 311 is a clock (1) after passing through the delay buffer 340.
Reference numeral 320 denotes a clock signal supplied to the flip-flop in the block after the output clock of the clock control cell 100 passes through the clock tree, and reference numeral 331 denotes a mask signal for masking the clock 311 in the clock control cell 100. The clocks have a delay and have a phase relationship of the clocks 310, 311 and 320 as shown in FIG. Further, since the change timing of the control signal 330 is triggered by the rising edge of the clock 320 serving as the operation clock, the change timing is near the next rising edge of the clock 310 if the clock is a high-speed clock. When the original clock (clock generation unit) is to be masked by this, the timing is extremely severe (arrows in the figure), but the clock 3 which is the clock that passed through the intra-block delay buffer 340 is used.
Considering that the mask 11 is masked, there is a margin in time. FIG. 10 shows the case where the control signal 330 changes in the low section of the clock 311. Assuming that the control signal 330 is active for one cycle, a clock is supplied inside the block, as indicated by the broken line.

Similarly, the control signal 330 is the clock 311
7, the clock mask signal 331 changes waiting for the low period of the clock 311 to change as shown in FIG. 7, and the clock also stops for one cycle. Here, of the clock 311 and the control signal 330, the clock 311 passes through a buffer for delay adjustment (a powerful buffer for distributing a lot of data in a block, which results in a large delay). The change of the clock mask signal 331 is surely in time for the rising change of the clock 311.

Here, for simplicity, the clock control cell 1
Although input of only the EN1 terminal of 00 is considered, if a clock control signal in the block is input to EN2, clock control can be similarly realized by the block alone. Since the timing is assured in the clock control cell 100, it is not necessary to consider the timing of the clock 311 whose phases are not aligned, and the timing design is very easy. That is, the clock control of the entire processor and the clock control of the block alone can be realized at the same time, and as a result of extremely fine clock control as compared with the related art, lower power consumption can be expected.

Conventionally, the clock delay (delay between the clock 310 and the clock 311) in the block is minimized.
Attempts have been made to achieve clock control during high-speed operation by reducing this, but clock delay is inevitable as long as the current synchronous design method is used. In the present invention, the clock control can be stably performed even at the time of high-speed operation by actively using the indispensable clock delay for control.

Further, the clock control cell 100 may be replaced with a clock control cell 200 whose operation is exactly the same. That is, the clock control cell 200 uses the clock control cell 200 when there is a clock control signal that is so critical that the transit time of the OR gate 110 in the clock control cell 100 is also omitted.

Even if the clock control cells 100 and 200 are not used, the same effect can be expected if gates having the same configuration are arranged. However, if the location of each gate cannot be precisely controlled during layout, timing cannot be guaranteed, so it can be used for clock control at low and medium speed operations, but it can be used for control at high speed operations. Can not do it.

Next, a clock skew adjustment method using the above-described clock control cell will be described.
The clock control cell 100 described above as a clock control cell
Use Even when the clock control cell 200 is used, the processing flow is exactly the same. First, with respect to the delay buffer and the clock control cell, a plurality of cells having the same outer shape of the layout data but different in only the delay value related to the clock are prepared. It is used to replace the layout data and adjust only the delay value.

Step 1: When generating netlist data from which layout data is generated, a circuit for receiving a clock in a block is configured as shown in FIG. Appropriate delays for the respective delay buffers and clock control cells at this time are employed. 8 and 9, reference numerals 401 and 501 denote clocks, 410 and 51, respectively.
0 and 511 are clock control cells (= clock control cell 1
00), 420, 520, and 521 are delay elements for adjusting skew between blocks, for example, delay buffers 430, 530,
Reference numeral 531 denotes a delay element for adjusting skew in a block, for example, a delay buffer. Flip-flops 540 and 541 are connected to the same clock tree (generated from the same clock control cell) in the block.
Are flip-flops connected to a clock tree different from 540 and 541. 500 is a block, 502
Is a control signal.

That is, in FIGS. 8 and 9, the delay buffer 42 for adjusting the clock tree in the block 500 is used.
0, 520 and 521 are arranged immediately after the block input, and clock control cells 410, 510 and 511 are arranged immediately after the delay buffers 420, 520 and 521. Step 2: At the time of creating layout data in block units, in order to suppress the time difference (in-block skew) from the output stage of the clock control cell 410 to each terminal gate (mainly a flip-flop) within the design allowable range, The size of the delay buffer 430 is determined in consideration of the load connected to the output stage of the clock control cell 410.
These processes can be generally performed by a tool. The same applies to FIG. 9, and since the clock trees are different, generally different delay values are assigned to the delay buffer 530 and the delay buffer 531.

Step 3: A full chip layout is executed. After that, a clock delay from the clock generation unit to a terminal gate (mainly a flip-flop) in each block is measured. Since the skew after the clock control cell in the block has been adjusted, the replacement of the clock skew adjustment delay buffer 420 between blocks and the clock control cell 410 is directly performed on the layout data.
The delay from the clock generator is made equal to the delay to the largest block. As described above, the clock skew in the chip can be adjusted.

Conventionally, when controlling a clock in a block, it is treated as a gated clock.
It is a design flow that is very difficult to handle with tools, and it was virtually impossible to manually adjust skew. However, according to the flow of the present invention, the layout can be easily realized by treating the clock control cell as a skew adjustment cell.

FIG. 10 schematically shows a block configuration in the final chip. Reference numeral 600 denotes a processor showing the entire chip. 610, 620, 640 are blocks to which a clock is supplied, 630 is a clock generator, 601
Is the clock output from the clock generator 630, 60
2 is a clock control signal output from the block 610;
611 is a control signal generation circuit for globally stopping blocks in the chip, 621 is a clock control cell for performing block-only control without performing global clock control, and 622 is a clock control cell for controlling intra-block clocks. A generating circuit 623 is a clock control signal in the block.
631 is a clock source.

In this embodiment, the clock control signal 602
Is output from the block 610 different from the clock generator 630, but may be output from the clock generator 630. Further, in the present embodiment, only one of the local clock control circuits 622 is provided, but it may be provided in each block or may be provided in plural. In this example, a clock that does not pass through the clock control cell is directly input to the control signal generation circuit 611, but in such a case, a special delay adjustment is required.

Further, as shown in this example, even in the same block, if the control units are different, a clock control cell may be prepared for each of those units.

[0035]

According to the clock control device of the present invention, a clock control cell capable of uniformly handling global control and local control with respect to clock control of a processor operating at high speed can be prepared. By incorporating them into the design flow, timing design becomes easier. As a result, efficient clock control can be realized, which greatly contributes to low power consumption of the processor.

According to the clock control device of the second aspect, the same effect as that of the first aspect is obtained. According to the clock control device of the third aspect, the same effect as that of the first aspect is obtained.
According to the clock control device of the fourth aspect, the same effect as that of the first aspect is obtained. According to the clock skew adjustment method according to the fifth aspect, the skew adjustment can be easily realized as a layout by treating the clock control cell as a skew adjustment cell.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a clock control cell according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the clock control cell of the present invention.

FIG. 3 is a waveform diagram showing timing when one input of an AND gate in the clock control cell of the present invention rises at the fastest speed.

FIG. 4 is a waveform diagram showing timing when one input of an AND gate in a clock control cell rises at the latest.

FIG. 5 is an explanatory diagram showing an arrangement configuration of clock control cells in a block according to the embodiment;

FIG. 6 is a waveform diagram illustrating how clock control is performed by a clock control cell in the embodiment, with the phase relationship between clocks being clarified, when a control signal changes in a low section of the clock. .

FIG. 7 is a diagram illustrating a state in which clock control is performed by a clock control cell according to the embodiment, clarifying a phase relationship between clocks, and is an explanatory diagram when a control signal changes in a high section of the clock; .

FIG. 8 is an explanatory diagram showing a basic configuration for clock skew adjustment in the embodiment.

FIG. 9 is an explanatory diagram showing a relationship between an arrangement of clock control cells in a block and a clock tree in the embodiment.

FIG. 10 is a circuit configuration diagram showing the overall configuration of a chip when the clock control device according to the embodiment of the present invention is used.

FIG. 11 is an explanatory diagram showing a state of clock distribution in a chip in a conventional example.

FIG. 12 is a waveform diagram showing timing of clock control during low-speed operation in a conventional processor.

FIG. 13 is a waveform diagram showing timing of clock control during high-speed operation in a conventional processor.

[Explanation of symbols]

100, 200 Clock control cell 101, 102, 201, 202 Clock control signal 103, 203 Clock after passing through delay buffer 110 OR gate 120, 220, 221 Low level latch 130, 230, 231 Logical inversion gate 140, 240 Logical product Gate 310 Clock (input clock) 340 Delay buffer 600 Processor 601 Clock generator output clock 602 Global clock control signal 623 Local clock control signal 621 Clock control cell 631 Clock source 610, 620, 640 Block receiving clock supply 630 Clock Generator 611 Global clock control signal generation circuit 622 Local clock control signal generation circuit

Claims (5)

[Claims] 1. A delay element for delaying an input clock input to a block, a low-level latch inputting a clock after passing through the delay element to an enable terminal, and a first clock control signal generated in the block A logical sum element for outputting a logical sum signal of the second clock control signal generated outside the block to a D input of the low level latch, a logical inversion element for logically inverting the output of the low level latch, A clock control device comprising: an AND element that outputs a logical product of the clock after passing through the delay element and the output of the logical inversion element as a block operation clock. 2. The clock control device according to claim 1, wherein the low-level latch, the OR element, the AND element, and the logical inversion element are configured in one clock control cell. 3. A delay element for delaying an input clock input to a block, and a clock after passing through the delay element is input to an enable terminal, and a first clock control signal generated in the block is input to a D input. A first low-level latch to be input, and a second low-level latch to input the clock after passing through the delay element to an enable terminal and to input a second clock control signal generated outside the block to a D input A first logical inverting element for logically inverting the output of the first low-level latch, a second logical inverting element for logically inverting the output of the second low-level latch, and after passing through the delay element And an AND element for outputting the AND of the output of the first logical inversion element and the output of the second logical inversion element as a block operation clock. Control device. 4. A clock control cell comprising a first low-level latch, a second low-level latch, an AND element, a first logical inversion element, and a second logical inversion element. The clock control device according to claim 3, wherein 5. A method for adjusting a clock skew between blocks, wherein, when creating netlist data in each of the blocks, a delay element for adjusting a clock tree is arranged in the block immediately after input of the block, and A layout on a full chip is performed so that the clock control cell is arranged immediately after the delay element, and a clock skew value between the blocks is obtained by this layout, and the delay element and the clock control cell in each block are determined. A clock skew adjustment method, wherein the clock skew value is reduced by replacing cells with the same outer shape but different delay values.