JP2000091906A - Exclusive or circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the XOR circuit fast by providing an OR circuit constituted by connecting bases of respective transistors to a 1st node point and a 2nd node point, respectively, connecting their emitters to a 3rd node in common, and connecting a current source to the 3rd node point. SOLUTION: Currents are so defined that Iab=Icd, Iab>=Iy, and OUT('1')> VBB1>OUT('0'). When '0' (even) is obtained as an XOR output, the currents Iab and Icd are made to flow to one of resistances R10 and R20 mutually. Since VBB1>OUT('0'), a current (Iab+Icd+Iy) flows to a resistance R3. Then '0' is obtained as the XOR output through an OR circuit W1. When '1' an odd number is obtained as the XOR output, both the currents Iab and Icd flow concentrically to one of the resistances R10 and R20 and do not flow to the other. Then '1' is obtained as the XOR output through the OR circuit W1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exclusive OR circuit suitable for high-speed driving.

[0002]

2. Description of the Related Art Generally, an exclusive OR circuit (hereinafter referred to as an XOR circuit) having a large number of input terminals is an XOR circuit having a small number of input terminals.
It is considered to be faster because the XOR logic result can be obtained with a smaller number of circuit stages than the R circuit. As an example of a conventional XOR circuit, a 4-input (A, B, C, D) XO shown in FIG.
R circuits are known. In the figure, Z1 is a load, W1 is an OR circuit, and X1 is 2 for inputs A and B (including / A, / B).
An input XOR circuit, X2 is connected to inputs C and D (including / C, /
D) for a two-input XOR circuit. X1 transistors Q3 and Q5 and X2 transistors Q4 and Q5
6 is connected to the resistor R1 in the load Z1, and X1
And the collectors of the transistors Q3 and Q5 of X2 are connected to the resistor R2 in the load Z1. Here, Iab is the drive current of X1, and Icd is X2
N1 is an output node to which the resistor R1 is connected,
N2 is an output node to which the resistor R2 is connected. The output OUT is obtained via an OR circuit W1 in which the output nodes of N1 and N2 are connected to the bases of the transistors Q7 and Q8, and their emitters are connected to a current source.

FIG. 13 shows the truth values of the conventional four-input XOR circuit. The operation will be described with reference to FIGS. Item numbers 1 to 16 show all combinations of four inputs (A, B, C, D). In the case where ｀ 0 ′ (even number) is obtained in the XOR output, drive currents Iab and Icd flow through either of resistors R1 and R2. For this reason,
Both output nodes N1 and N2 have a low potential (hereinafter, ｀
L ′), and outputs “0” to the output via the OR circuit W1.
(Even number) is obtained. On the other hand, in the case where ｀ 1 ′ (odd number) is obtained in the XOR output, drive currents Iab and Ic
The two currents d concentrate on one of the resistors R1 and R2 and do not flow on the other. Therefore, one of the output nodes N1 and N2 is set to a high potential (hereinafter, referred to as ′ H ′), the other is set to a double low potential (｀ 2L ′), and output to the output via the OR circuit W1. 1 '(odd number) is obtained.

[0004]

As described above, output nodes N1 and N2 operate with a signal amplitude of ｀ L 'or ｀ 2L'. Among them, the amplitude required for the XOR output to be "0" is "L". Therefore, no consideration has been given to the point that the shortening of the delay time of the four-input XOR circuit is rate-determined in the case of operating with an amplitude of 2 L '.

[0005] This point will be described with reference to a waveform diagram showing the operation of the conventional example shown in FIG. FIG. 14 shows input A,
When B, C, and D change in the order shown by X → Y → Z (the order of item numbers 1 → 2 → 5 in FIG. 13), the output node N
1, N2, and the change of the XOR output OUT are shown.

In the period X, the output nodes N1 and N2 are both at "L" and the XOR output is at "0". In the period Y, after a certain delay time (almost td1), the output node N1 is changed from ｀ L ′ to ｀ H ′, and the output node N2 is set to ｀ H ′.
L ′ → ｀ 2L ′, and the XOR output is set to ｀ 1 ′ (VBB in FIG. 14 is a reference potential of the next stage circuit: VBB = (｀
H ′ + ｀ L ′) / 2). In the period Z, after a certain delay time (almost td2), the output node N1 becomes ｀
H ′ → ｀ 2L ′, and the output node N2 becomes {2L ′ → ｀}.
H 'is made, and the XOR output goes from ｀ 1' to ｀ 0 'once and is made ｀ 1' again.

In periods Y and Z, output node N1
And N2 have equal rise times. However, the equivalent VB
The time required to cross the B potential is の of the rise time when ｀ L ′ → ｀ H ′, and when ｀ 2L ′ → ｀ H ′,
3/4 of the rise time. That is, the output node N1
And the smaller the amplitude of N2, the shorter the time it takes for the rising waveform of the XOR output to cross the VBB potential. Therefore X
The delay time of the OR output is td1 <td2.

As described above, the shortening of the delay time of the conventional four-input XOR circuit is based on the fact that output nodes N1 and N2
The speed is limited in the case of operating with the amplitude of L '.

It is an object of the present invention to reduce the signal amplitude .DELTA.H '-. DELTA.2L' at output nodes N1 and N2 of the XOR circuit and to speed up the XOR circuit.

[0010]

SUMMARY OF THE INVENTION The object of the present invention is to provide a third current switching circuit, wherein when the XOR output is "0", the current of the current switching circuit flows to the load resistor, while the XOR output is "1". In this case, it is achieved by controlling so that the current of the current switching circuit does not flow to the load resistance.

[0011]

FIG. 1 shows a first embodiment of the present invention. FIG. 2 shows the truth values of the XOR circuit of the present invention. This embodiment is different from the conventional circuit shown in FIG. 12 in that a current switching circuit Y1 and a resistor R3 in a load Z1 are added. The current switching circuit Y1 includes a transistor Q21 having an XOR output OUT as a base and an emitter connected to a current source Iy, a reference potential VBB1 as a base and an emitter connected to the current source Iy and a collector as resistors R3 and R10. The transistor Q20 is connected to the node of R20.

The operation will be described with reference to FIGS.
As a precondition, Iab = Icd, Iab ≧ Iy, OU
It is assumed that T (＞ 1 ′)>VBB1> OUT (｀ 0 ′). 4
All combinations of the inputs (A, B, C, D) are shown in item numbers 1 to 16. In the case where ｀ 0 ′ (even number) is obtained in the XOR output, currents Iab and Icd flow through one of resistors R10 and R20. VBB1> OUT
(｀ 0 ′), the current (Iab + I
cd + Iy) flows. Therefore, both output nodes N1 and N2 are set to ｀ L ', and X is output via OR circuit W1.
$ 0 '(even number) is obtained at the OR output. On the other hand, in the case where ｀ 1 ′ (odd number) is obtained in the XOR output, the current Iab
And Icd flow intensively in one of resistors R10 and R20 and do not flow in the other. Also, O
Since UT (｀ 1 ′)> VBB1, current Iy does not flow through resistor R3, and current (Iab + Icd) flows. Therefore, one of the output nodes N1 and N2 becomes ｀
H ′ and the other is set to a low potential (｀ αL ′). Therefore, ｀ 1 '(odd number) is obtained at the XOR output via the OR circuit W1. Note that R10 = R20 = R3, Iab =
When Icd = Iy, ｀ L ′ = ｀ αL ′. The signal amplitude is (｀ H '-′ αL') <(｀ H '-｀ 2L')
Becomes

Next, the effect will be described with reference to a waveform diagram shown in FIG. 3 showing the operation of the circuit of the present invention. The transition of the input is the same as in the case of the conventional example shown in FIG. In this embodiment, when the period Z is entered from the period Y, after a certain delay time (substantially td3), the output node N1 becomes {H ′ → Δα}.
Since the output node N2 is changed to L 'and the output node N2 is changed from 、 αL' to ｀ H ', the XOR output is temporarily changed from ｀ 1' to ｀ 0 'and changed to ｀ 1' again. At this time, since the potential levels of the output nodes N1 and N2 satisfy ｀ αL ′> ｀ 2L ′, ｀ αL ′ →
The time required for the rising waveform of ｀ H 'to cross the equivalent VBB potential is shorter than the case of 従 来 2L' → ｀ H 'in the conventional circuit. Therefore, the delay time of the XOR output is td3 <td2
Becomes When ｀ αL ′ is further reduced, the waveform that is once changed from ｀ 1 ′ to ｀ 0 ’and then set to ｀ 1’ again does not cross the VBB potential, and the delay time can be ignored.

As described above, according to this embodiment, the signal amplitudes of the output nodes N1 and N2 of the XOR output are reduced, and
The speed of the OR circuit can be increased.

FIG. 4 shows a second embodiment of the present invention. This embodiment is different from the first embodiment in that clamp transistors Q60 and Q61 are added. The emitters of transistors Q60 and Q61 are connected to output nodes N1 and N2, respectively, and their bases are commonly connected to clamp potential VCL. This allows, for example,
When the potential levels of output nodes N1 and N2 are low,
Transistor Q3 of current switching circuits X1, X2, Y1
Q6 and Q20 are prevented from being saturated.

FIG. 5 shows a third embodiment of the present invention. This embodiment is different from the first embodiment only in the configuration of the current switching circuit Y1. In the current switching circuit Y1 of this embodiment, the output nodes N1 and N2 are connected to the respective bases, and the transistors Q21 and Q22 whose emitters are commonly connected to the current source Iy, the base receives the reference potential VBB1 and the emitter The transistor Q20 has the current source Iy connected thereto and the collector connected to the resistor R3. Since the current switching circuit Y1 is not controlled by the XOR output, the current switching circuit Y1 is driven at high speed without being affected by the load on the XOR output line. still,
Transistor Q instead of transistors Q7 and Q8
Since the logical sum is obtained at 21 and Q22, the same logical operation as in the first embodiment is performed.

FIG. 6 shows a fourth embodiment of the present invention. This embodiment also differs from the first embodiment only in the configuration of the current switching circuit Y1. In the current switching circuit Y1 of this embodiment, the output nodes N1 and N2 are connected to the respective bases, and the transistors Q22 and Q23 whose emitters are commonly connected to the current source IEF2;
A transistor Q21 connected to the emitters of transistors 22 and Q23, the emitter of which is connected to current source Iy, and a transistor Q21 which receives reference potential VBB1 at the base, connects current source Iy to the emitter and connects resistor R3 to the collector
20. In this embodiment, the current switching circuit Y1
Is not controlled by the XOR output, the current switching circuit Y1 is driven at high speed without being affected by the load on the XOR output line.

FIG. 7 shows a fifth embodiment of the present invention. This embodiment is different from the first embodiment in that a transistor Q50 is added in the load Z1. In the first embodiment, the ｀ H 'level of output nodes N1 and N2 is
(H) = − R3 × (Iab + Icd) On the other hand, in the present embodiment, V (H) = − VBE (where VBE is the base-emitter voltage of the transistor Q50). Therefore, the above R3 × (Iab + Icd)
Is larger than VBE, the use of this embodiment can reduce the saturation of the transistor in the current switching circuit.

FIG. 8 shows a sixth embodiment of the present invention. This embodiment is different from the first embodiment in the configuration of the current switching circuits X1 and X2. In the first embodiment, the drive current is switched by a potential difference between complementary input signals (for example, A and / A, B and / B). On the other hand, in the present embodiment, the drive current is switched by the potential difference between the input signal (for example, A or B) and the reference potential (for example, VBB2 or VBB3). In this embodiment, a circuit in which the preceding-stage circuit does not generate a complementary signal (for example, the circuit shown in the first embodiment)
Applies in the case of.

FIG. 9 shows another example of the current switching circuits X1 and X2 used in the circuit of the present invention. FIG.
The current switching circuit shown in FIG. 9A includes, for example, the potentials of the output nodes N1 and N2 of the third embodiment and the reference potential (for example, V
BB2 or VBB3) so that the driving current can be switched according to the potential difference. That is, the transistors Q7 and Q8 of the OR circuit W1 of the third embodiment are configured to be taken in as the transistors Q3 and Q31 of the current switching circuit.

Therefore, the circuit shown in FIG. 10 as the seventh embodiment of the present invention (the circuit from which the OR circuit W1 of the third embodiment is deleted) is selected as the pre-stage circuit for driving the current switching circuit. It is. A detailed circuit in which the exclusive OR circuit and the exclusive OR circuit using the current switching circuit are cascaded is shown in FIG. 11 as an eighth embodiment of the present invention. In the eighth embodiment, it is important to shorten the XOR output line of the pre-stage circuit as much as possible for speeding up.

When the power supply voltage is high, the current switching circuit has three inputs (complementary input or VBB reception) as shown in FIG. 9B or more inputs within a range in which transistor saturation does not occur. A number configuration may be used. On the other hand, when the power supply voltage is small, the 1 as shown in FIG.
It consists of inputs (which may be complementary inputs or VBB receivers).

[0023]

As described above, according to the present invention, XO
The signal amplitudes at the output nodes N1 and N2 of the R circuit are reduced, and the speed of the XOR circuit can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an exclusive OR circuit according to the present invention.

FIG. 2 is a diagram showing truth values of the circuit shown in FIG. 1;

FIG. 3 is a waveform chart showing the operation of the circuit shown in FIG.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 9 is a circuit diagram showing another example of the current switching circuit used in the embodiment of the present invention.

FIG. 10 is a circuit diagram showing a seventh embodiment of the present invention.

FIG. 11 is a circuit diagram showing an eighth embodiment of the present invention.

FIG. 12 is a circuit diagram showing an example of a conventional exclusive OR circuit.

FIG. 13 is a diagram showing truth values of the circuit shown in FIG. 12;

FIG. 14 is a waveform chart showing the operation of the circuit shown in FIG.

[Explanation of symbols]

Z1: load, X1: first current switching circuit, X2: second current switching circuit, Y1: third current switching circuit, W1: OR circuit, OUT: exclusive OR output.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hiroaki Nambu 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. Central Research Laboratory (72) Inventor Kenichi Ohata 3681 Hayano, Mobara City, Chiba Prefecture Inside Hitachi Device Engineering Co., Ltd. (72) Inventor Fumihiko Arakawa 3681 Hayano, Mobara City, Chiba Prefecture Inside Hitachi Device Engineering Co., Ltd. 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (72) Inventor Keiichi Hishita 3-16, Shinmachi, Ome-shi, Tokyo 3 Device Development Center, Hitachi, Ltd. Ichijomizu Honcho 5-22-1, Hitachi Ultra LSI Systems Co., Ltd. (72) Inventor Takashi Kiba 5-22-1, Kamizu Honcho, Kodaira-shi, Tokyo Hitachi Ultra LSI, Inc.・ Systems F-term (reference) 5J042 AA10 BA14 CA06 CA11 CA23 CA26 DA03

Claims (15)

[Claims] 1. A first output terminal of a first current switching circuit is connected to a first node, and a second output terminal of the first current switching circuit is connected to a second node.
And a first output terminal of a second current switching circuit is connected to the second node, and a second output terminal thereof is connected to the first node. A first current switching circuit having an input terminal and a second current switching circuit, wherein the first terminal of a load having a first terminal, a second terminal, and a third terminal is connected to the first node; And a second terminal having a load connected to the second node, wherein the base of each transistor is connected to the first node.
And an OR circuit in which the emitter is connected to the third node and the current source is connected to the third node, respectively. A third current switching circuit having an input terminal connected to the third node and an output terminal connected to a third terminal of the load, wherein the third node is connected to the third node. An exclusive-OR circuit, characterized in that an exclusive OR circuit is used as an output. 2. The exclusive-OR circuit according to claim 1, further comprising a clamp circuit for clamping the potentials of said first and second nodes. . 3. The exclusive-OR circuit according to claim 1, wherein said first and second current switching circuits include a number of transistors having a set of true and complementary signals as input signals, and A current source that supplies a current flowing to any of the transistors based on an input signal, and the current of the current source is supplied to the first output terminal of the current switching circuit through the transistor based on the input signal; Alternatively, an exclusive-OR circuit, wherein the signal is supplied to one of the second output terminals. 4. An exclusive OR circuit according to claim 1, wherein said load has one end connected to a first terminal of said load, and the other end connected to a third terminal of said load.
And a second resistor having one end connected to a second terminal of the load and another end connected to a third terminal of the load, and one end connected to a third terminal of the load. An exclusive-OR circuit having a third resistor whose other end is connected to a first potential. 5. The exclusive OR circuit according to claim 1, wherein said load has one end connected to a first terminal of said load, and the other end connected to a fourth node. A second resistor having one end connected to the second terminal of the load and the other end connected to the fourth node; and a second end connected to the third terminal of the load, and a second end connected to the third terminal of the load. A third resistor connected to the first potential and a base connected to the third resistor of the load;
An exclusive-OR circuit comprising a transistor connected to a terminal of the third OR and having an emitter connected to the fourth node. 6. The exclusive-OR circuit according to claim 1, wherein said third current switching circuit has an input terminal and an output terminal, said input terminal is connected to a base, and a current source is connected to an emitter. An exclusive OR circuit comprising: a first transistor having a base connected to a reference potential; an emitter connected to the current source connected to an emitter; and a collector connected to the output terminal. 7. An exclusive OR circuit according to claim 1, wherein said third current switching circuit includes a first input terminal connected to said first node, and a third current switching circuit connected to said second node. A first transistor having a second input terminal connected thereto, and an output terminal connected to a third terminal of the load, wherein the first input terminal is connected to a base and a current source is connected to an emitter; A second transistor having the base connected to the second input terminal and the emitter connected to the current source;
An exclusive-OR circuit comprising: a third transistor having a base receiving a reference potential, the emitter connected to the current source, and the collector connected to the output terminal. 8. The exclusive-OR circuit according to claim 1, wherein said third current switching circuit is connected to a first input terminal connected to said first node, and to said second node. A second input terminal connected to the third terminal of the load, an output terminal connected to the third terminal of the load, a base connected to the first input terminal and an emitter connected to the fifth node; A first transistor, a second transistor having a base connected to the second input terminal and an emitter connected to the fifth node, and a first current source connected to the fifth node. A third transistor having a base connected to the fifth node and an emitter connected to the second current source, a base receiving a reference potential, an emitter connected to the second current source, and a collector connected to the output. Having a fourth transistor connected to the terminal Exclusive OR circuit, wherein. 9. A first current switching circuit having a first output terminal connected to a first node and a second output terminal connected to a second node.
And a first output terminal of a second current switching circuit is connected to the second node, and a second output terminal thereof is connected to the first node. A first current switching circuit having an input terminal and a second current switching circuit, wherein the first terminal of a load having a first terminal, a second terminal, and a third terminal is connected to the first node; A first input terminal of a third current switching circuit connected to the first node, the second terminal having a load connected to the second node, the second terminal having a load connected to the second node; A third current switching circuit having a second input terminal connected to the second node and an output terminal connected to a third terminal of the load, wherein the third current switching circuit is connected to the first node and the third node; An exclusive-OR circuit, wherein the second node is output. 10. An exclusive OR circuit according to claim 9, further comprising a clamp circuit for clamping the potentials of said first and second nodes. 11. The exclusive-OR circuit according to claim 9, wherein said first and second current switching circuits comprise a number of transistors having a set of true and complementary signals as input signals, and A current source for supplying a current flowing to any of the transistors based on an input signal; and a current output from the current source via the transistor based on the input signal. An exclusive-OR circuit, wherein the signal is supplied to one of the second output terminals. 12. The exclusive-OR circuit according to claim 9, wherein said load has one end connected to a first terminal of said load, and the other end connected to a third terminal of said load.
And a second resistor having one end connected to a second terminal of the load and another end connected to a third terminal of the load, and one end connected to a third terminal of the load. An exclusive-OR circuit having a third resistor whose other end is connected to a first potential. 13. An exclusive-OR circuit according to claim 9, wherein said load has one end connected to a first terminal of said load and said other end connected to a third node. And a second resistor having one end connected to the second terminal of the load and the other end connected to the third node, and one end connected to the third terminal of the load and the other end connected to the third terminal of the load. A third resistor connected to the first potential and a base connected to the third resistor of the load;
An exclusive-OR circuit comprising a transistor connected to the terminal of the third node and having an emitter connected to the third node. 14. The exclusive-OR circuit according to claim 9, wherein said third current switching circuit includes a base connected to said first current switching circuit.
A first transistor having an input terminal connected thereto and a current source connected to the emitter, a second transistor having the base connected to the second input terminal and having the emitter connected to the current source, and a reference potential connected to the base. Receiving the current source connected to the emitter and the output terminal connected to the collector.
An exclusive-OR circuit comprising: 15. An exclusive OR circuit according to claim 9, wherein said third current switching circuit has a base connected to said first current switching circuit.
And a second transistor whose base is connected to the second input terminal and whose emitter is connected to the fourth node. A first current source connected to the fourth node, a third transistor having a base connected to the fourth node and an emitter connected to the second current source, and a reference to the base. An exclusive-OR circuit comprising a fourth transistor having a potential and an emitter connected to the second current source and a collector connected to the output terminal.