JP2000091862A - Variable gain amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable gain amplifier capable of being operated at lower voltage, housing a widely stable frequency band and a high in input impedance. SOLUTION: This variable gain amplifier is provided with differential input circuits 26 and 27 to which two input voltages are inputted, gain control stages 60, 61 to which a gain control voltage 50 and the two output currents of the differential input circuits are inputted, and in which three or more transistor devices are included, output stages 16, 17, 18, 19, 22, 23, 24, 25, 30, 31, 32 and 33 for changing the output voltages based on the two output currents of the gain control stages, and feedback circuits 24, 25, 28, 40 and 46 for negative feedbacking the output voltages to the stage circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates generally to variable gain amplifiers and, more particularly, to a highly linear variable gain amplifier (VGA) that operates at low voltages.

[0002]

2. Description of the Related Art A variable gain amplifier (VGA) or a programmable gain amplifier (PGA) is an important component in any signal conditioning system and is widely used in A / D converters, digital oscilloscopes, signal conditioners, and the like. I have. Although there are many VGAs and PGAs produced by using the CMOS technique, all of them have some problems to be solved.

One example of such a variable gain amplifier is disclosed in Japanese Patent Application Laid-Open No. 7-122950. Although this circuit is a pure CMOS circuit whose frequency bandwidth does not depend on gain, it has a major drawback in that the power supply is large. For this reason, it does not meet the recent requirement of operating at a low voltage and is not practical.

FIG. 5 shows this circuit. The transistors used here are all MOSFETs (metal oxide field effect transistors) (hereinafter simply referred to as “FETs”). The input voltage 1 is applied to the two terminals indicated by Vin.
0 and 11 are input. Output voltage terminals are indicated by Vo ₊ and _Vo- , and output voltages 12 and 13 appear here. Here, the FETs 26, 27, 45, 47 constitute a differential input circuit, and the FETs 24, 25, 28, 29,
Reference numerals 40 and 46 constitute a negative feedback circuit for negatively feeding back the output voltages 12 and 13. And FETs 16, 18, 20, 2
2, 30, 32 and 17, 19, 21, 23, 31,
33 constitutes an output stage circuit. The input of the FET 34 and the gain control voltage 50 constitute a gain control stage. Where FE
T20, 21, 22, and 23 are all NFET devices, while FETs 30, 31, 32, and 33 are PFET devices.

The input voltages 10 and 11 are connected to FETs 26 and 27
And the sources of FETs 26 and 27 are connected to F
The source of the FET 45 is connected to the drain of the ET 45. Also, FET2
The drain of FET 6 is the source of FET 20, FET 16, 1
8 and the drain of the FET 34,
The drain of T27 is the source of FET21, FET1
7 and 19 are connected to the drains.

The drain of the FET 20 is connected to the drain of the FET 28 and the source of the FET 22. The drain of the FET 22 outputs the output voltage 12 and
And the gate of the FET 24 and the drain of the FET 30. The drain of the FET 21 is connected to the drain of the FET 29 and the source of the FET 23. The drain of the FET 23 outputs the output voltage 13,
It is connected to the gate of ET25 and the drain of FET31.

The sources of the FETs 28 and 29 are FE
Connected to the drain of T40, the source of FET40 is F
Connected to the drain of ET46. The sources of the FETs 30 and 31 are connected to the drains of the FETs 32 and 33, respectively. Further, the sources of the FETs 32, 33, 46, and 47 are connected to the positive voltage source _VDD , and the FETs 16, 18, 40, 17, and
The 19 source is connected to the ground (GND). Gate of FET32, 33, 46, 47, FET2
Bias voltages are applied to the gates 2 and 23 and the gates of the FETs 20 and 21, respectively.

The gates of the FETs 16 and 17 are connected to a common mode voltage V _CM . This common mode voltage is
It is proportional to the sum of the output voltages 12 and 13 and is proportional to the common mode of the output voltage. As a result, when the voltage V _CM increases, the FETs 16, 1
By the action of 7, a bias current flows in the output stage circuit,
The operation is performed so that the common mode of the output voltage is reduced. When the voltage V _CM decreases, the operation is performed so that the common mode of the output voltage increases. That is, the common mode feedback circuit operates as a negative feedback circuit.

The main disadvantage of the circuit described in Japanese Patent Application Laid-Open No. 7-122950 is that it has a configuration in which five transistors are connected in series, which limits the output swing and reduces the supply voltage. (1.2μ)
6 bolts in case of m processing). This is partly due to the large Vt in the 1.2 μm processed device. Vt can be reduced by using a newer processing technology (from 0.8 volts for 1.2 μm to 0.5 volts for 0.5 μm technology) but still 3.3 volts. It cannot be operated with power supply.

The reason that the frequency band of this prior art circuit is stable against fluctuations in gain is that the current signal from the differential input circuit can be adjusted without changing the characteristics of the feedback circuit. Such a function is achieved by the cascade stage including the FETs 20 and 21 shown in FIG. And FET2 of this cascade stage
The presence of 0 and 21 is the reason for increasing the required power supply voltage.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems in the prior art while operating at a lower voltage.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a variable gain amplifier having the advantages of the above-mentioned prior art such as frequency band stability and high input impedance.

[0012]

According to the present invention, a differential input circuit to which two input voltages are input, a gain control voltage and two output currents of the differential input circuit are input, and three or more are input. A gain control stage including the transistor device, an output stage for changing an output voltage based on two output currents of the gain control stage, and a feedback circuit for negatively feeding back the output voltage to the output stage. A variable gain amplifier is provided.

That is, a set of FETs 20 and 21 cascaded in series with the output stage circuit is removed and, as an alternative, one of the output stage circuits arranged in series with the input differential circuit. Two or more FETs that do not constitute a unit are employed. With such a configuration,
The current signal from the differential input circuit can be adjusted by the current signal from the differential input circuit without changing the characteristics of the feedback circuit. In the present invention, a circuit composed of these FETs and an FET receiving the gain control voltage is called a gain control stage. Thus, by reducing the number of FETs connected in series at the output stage, lower voltages, especially 3.3 volts, are a challenge while maintaining or improving the overall variable gain amplifier circuit characteristics. It enables the following operations.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, the same parts as those of the prior art described with reference to FIG. The invention according to the present application is defined by the claims, and it is needless to say that the invention is not limited to the embodiments described herein. In this embodiment, a description will be given using a metal oxide field-effect transistor. However, other devices, for example, a bipolar transistor or the like can be used.

In FIG. 1, FETs 20 and 21 have been removed with a bias voltage V _bias 4. Instead, the sources of FETs 60 and 61 are coupled to the drain and source of FET 62, respectively, which receives gain control voltage 50. The gates of these FETs 60 and 61 are both grounded. The drains of the FETs 60 and 61 are connected to the sources of the FETs 22 and 23 and the drains of the FETs 28 and 29 which constitute a part of the feedback circuit. These FETs 60 and 61 are PMOS. The FET 34 receiving the input of the gain control voltage 50 in the conventional example of FIG. 5 is an FET 62 in the circuit diagram of FIG.
It can be seen that it has been replaced by

That is, the output stage comprises FETs 16, 18,
22, 24, 30, 32 and FETs 17, 19, 2
3, 25, 31, and 33. By using four transistors connected in series in the output stage, operation at 3.3 volts becomes possible. The differential input circuit includes FETs 26, 27, 45, and 47. The negative feedback circuit includes FETs 24, 25, 2
8, 29, 40 and 46, and the output voltages 12 and 13 are negatively fed back.
Another similar FET (this F
(The source of ET connects to the drain of FET 46) can be provided on V _bias 2 in the same manner as FET 46 is provided on V _bias 1 shown.

The operation of the circuit of this embodiment is as follows. If the gain control voltage 50 is low, FET 62 is off. The current from the input FETs 28 and 29 is directed to the output node and the gain is maximized. As the gain control voltage 50 increases, a portion of the current from the input flows through the FET 62 and the gain decreases.

To show that the frequency band does not depend on the gain, consider the small signal equivalent half circuit shown in FIG. here,
α is a coefficient indicating how much of the current of the input section is input to the output node through the FETs 60 and 61. Therefore, the gain can be calculated as follows from FIG.

[0019]

(Equation 1) Here, R ₂ and C ₂ are the output resistance and the load capacitance of the output node B. C ₁ is the total capacitance of node A, and R ₁ is the input resistance of node A (1 /
g _m7 ). The above equation shows that the position of the pole, that is, the frequency band does not change with the gain. Note that changing the load capacitance at the output node can significantly change the frequency response. Therefore, two source followers are used at the output node to enable the variable gain amplifier to operate with relatively large load capacitance.

FIG. 3 illustrates the present invention at different gain voltage levels.
Simulation showing frequency response of variable gain amplifier of embodiment
Result. In this graph, Vgain is the gain control
Represents the voltage 50. Figure 4 shows the temperature dependence of the gain of this amplifier.
It shows the nature. Gain variation with temperature is extremely
small. At different signal strengths and frequencies and amplifier gains
Total harmonic distortion (THD) is as follows:
You. V at 78MHz output _ppIs 600 mV,
The simulated THD has a gain of up to -60 dB,
The minimum gain was -45.3 dB. In addition, 316MH
Noise in the frequency band of z is also simulated
According to the figure, the maximum gain is 86 μV and the minimum gain is 78 μV.
7 μV. Relatively large noise at low gain
Is the noise of the source follower and the output that is fed back to the input stage.
This is due to noise at the power stage. However, low profit
Since the gain is used only when the input signal is large,
The noise seen is-
Less than 60 dB.

This amplifier has a wide variable gain range of 18 dB, and the maximum gain is 19.5 dB. -3d
The frequency band at B was 310 MHz. Therefore, the product of the effective gain and the frequency band of this circuit is 3 GHz
It is. All of these are possible with a single-stage amplification with a power consumption of 22 mW. When such circuits are cascaded in two stages, a variable gain amplifier of approximately 40 dB is obtained.

[0022]

As described above, according to the present invention, 0.5
Using μm CMOS technology, a variable gain amplifier that operates at 3.3 volts can be made. Further, the frequency band does not depend on the gain. Operating at such a low voltage, in addition to the excellent characteristics of high input impedance and wide and stable frequency band, is very important in satisfying the current requirements for variable gain amplifiers. .

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a variable gain amplifier according to an embodiment of the present invention.

FIG. 2 shows an equivalent half circuit of the circuit of the embodiment according to FIG.

FIG. 3 is a graph showing a relationship between a gain control voltage and a frequency response of a variable gain amplifier.

FIG. 4 is a graph showing a change in frequency response of the variable gain amplifier with respect to temperature.

FIG. 5 is a circuit diagram showing a circuit configuration of a conventional example.

[Explanation of symbols]

10,11 input voltage 12,13 output voltage 16,17,18,19,22,23,24,25,2
6,27,28,29,30,31,32,33,4
5, 46, 47, 60, 61, 62 FET 50 Gain control voltage V _DD operating voltage V _CM common mode voltage GND Ground

Claims (1)

[Claims] 1. A differential input circuit to which two input voltages are inputted, a gain control stage to which a gain control voltage and two output currents of the differential input circuit are inputted, and comprising three or more transistor devices. A variable gain amplifier comprising: an output stage for changing an output voltage based on two output currents of the gain control stage; and a feedback circuit for negatively feeding back the output voltage to the output stage.