JP2000091418A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form fine trench element isolation layers which exceed the resolving limit of photolithography. SOLUTION: After a mask layer 6 is formed on the main surface of a semiconductor substrate 2, recessed sections 6a are formed on the surface of the layer 6, and sidewalls 10 are formed in the sections 6a. Grooves (trenches 2a) are formed on the surface of the substrate 2 by etching the portions of the mask layer 6 under the sidewalls 10, by using the sidewalls 10 as masks and etching the substrate 2 by using the mask layer 6 and sidewalls 10 as masks. After the trenches 2a are filled by depositing an insulator over the entire surface, the insulator is removed from the surface of the mask layer and the main surface of the substrate 2. Openings may also be formed through the mask layer 6 in the thickness direction rather than the recessed sections 6a and sidewalls on the internal surfaces of the openings may be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a trench element isolation layer. Specifically,
The present invention relates to a method for manufacturing a semiconductor device capable of miniaturizing a trench below the limit resolution of photolithography.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor devices, the development of element isolation forming techniques for reducing the area of element isolation regions has been actively carried out. Conventionally, LOCOS (Local Oxidation of Silo
icon) There is a law. In the LOCOS method, element isolation is performed by thickly thermally oxidizing the exposed surface of the silicon substrate using a nitride film patterned on the silicon substrate with a pad oxide film interposed therebetween as an oxidation prevention layer. The LOCOS method can be applied to a region having a relatively large element formation region, for example, a peripheral circuit portion of a memory device without any problem.

However, according to the LOCOS method, thermal oxidation for forming the LOCOS does not sufficiently proceed in a region where the element interval is relatively narrow, for example, in a memory cell array portion. Therefore, the LOCOS is thinner than the peripheral circuit portion. Easy to form. As a result, the insulation characteristics of the memory cell isolation deteriorate, the leak current increases between wells, and a parasitic MOS transistor having a thin wiring layer on LOCOS as a gate is easily formed. As a result, Transistor characteristics deteriorate. Further, since the LOCOS is formed by thermally oxidizing the substrate, crystal distortion is introduced into an active region around the LOCOS due to stress due to volume expansion at the time of thermal oxidation, and crystal defects occur. This crystal defect becomes a metal contamination trap when the gate electrode (metal polycide gate electrode) is processed, and the transistor characteristics may be degraded from this point as well. In addition, LOC
The occurrence of a bird's beak at the end of the OS limits the area of the active region, and this has the disadvantage of inhibiting the reduction of the cell area and increasing the surface step.

An STI (Shallow Trench Isolation) is known as a technique for forming an element isolation layer that solves the above problem. In STI, a trench is formed at an arbitrary depth by using a nitride film pattern formed on a substrate with a pad oxide film interposed therebetween as a mask layer for substrate etching, and an insulator is embedded in the trench to form a trench. An element isolation layer is formed. When this STI is used, there is no extra area such as a bird's beak that does not contribute to element isolation, so that the element isolation width, which was limited to about 0.8 μm in LOCOS isolation, can be reduced to about half of that. In addition, since the depth of the trench can be arbitrarily set, the insulating characteristics are good, and crystal distortion due to volume expansion of silicon does not occur.

[0005]

However, in such a conventional trench element separation method, there is a problem that the separation width is limited by the resolution limit of photolithography when processing an etching mask layer. . For this reason, it is difficult to form a trench isolation layer having an isolation width smaller than 0.4 μm with the current design rule of about 0.3 μm.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a fine trench element isolation layer exceeding the resolution limit of photolithography.

[0007]

According to a method of manufacturing a semiconductor device of the present invention, a step of forming a mask layer on a main surface side of a semiconductor substrate; a step of forming a concave portion on a surface of the mask layer; Forming a sidewall in the concave portion, etching the mask layer portion below the sidewall using the sidewall as a mask, etching the semiconductor substrate using the mask layer and the sidewall as a mask, Forming a groove (trench) on the surface of the substrate, filling the groove by depositing an insulator over the entire surface, and removing the insulator above the main surface of the mask layer and the semiconductor substrate. Have. The step of forming the recess preferably includes a step of etching the mask layer from the surface using a photoresist pattern formed on the mask layer as a mask, and the groove formed in the semiconductor substrate has a pattern minimum dimension. Is smaller than the resolution limit at the time of forming the photoresist pattern.

Preferably, the step of removing the mask layer and the insulator includes a step of polishing the surface of the insulator deposited by filling the trench. By planarizing, for example, a focus margin in a later photolithography step can be increased, and variation in a process can be reduced.

According to the semiconductor device of the present invention, a step of forming a mask layer on the main surface side of a semiconductor substrate, a step of forming an opening in the mask layer, and a step of reducing the size of the opening of the mask layer Etching the semiconductor substrate using the mask layer having the reduced size of the opening as a mask to form a trench on the surface of the semiconductor substrate;
A step of depositing an insulator over the entire surface to fill the groove; and a step of removing the insulator above a main surface of the mask layer and the semiconductor substrate.

In these semiconductor devices, the size of the opening of the mask layer is reduced by a sidewall or the like. For this reason, the minimum dimension of the trench formed in the semiconductor substrate is
It can be smaller than the resolution limit of photolithography when processing the mask layer.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings, taking an example in which the present invention is applied to a MOS type semiconductor device.

First Embodiment FIGS. 1 to 8 are sectional views showing the steps of manufacturing a semiconductor device according to this embodiment.

As shown in FIG. 1, a pad oxide film 4 made of, for example, silicon oxide and a mask layer 6 made of, for example, silicon nitride are sequentially formed on a semiconductor substrate 2 such as a silicon wafer. Specifically, the pad oxide film 4 is formed to a thickness of, for example, about 10 to 20 nm by a thermal oxidation method. A mask layer 6 having a thickness of about several hundred nm is formed on the pad oxide film 4 by CVD (C
Chemical Vapor Deposition). The pad oxide film 4 is provided for ensuring the adhesion between the mask layer 6 made of silicon nitride or the like and the silicon substrate, and may be omitted depending on the material of the mask layer 6. Mask layer 6
Functions as an etching mask when a groove (trench) is formed in the semiconductor substrate 2 later. Therefore, the mask layer 6
Is made of a material having a high etching selectivity with silicon, such as silicon nitride. The thickness of the mask layer 6 is determined in consideration of, for example, the depth of a trench to be formed.

Next, a pattern 8 made of, for example, a photoresist is formed on the mask layer 6 as an etching mask for forming a concave portion on the surface thereof. The resist pattern 8 has an opening at a position where a concave portion is formed.

As shown in FIG. 2, the resist pattern 8 is used as a mask to perform etching to a part of the mask layer 6.
Thereby, a recess 6 a is formed on the surface of the mask layer 6. The etching at this time is desirably anisotropic etching such as RIE (Reactive Ion Etching) from the viewpoint of pattern transfer accuracy.

After removing the resist pattern 8, as shown in FIG. 3, a film 10a made of, for example, non-doped polysilicon is formed on the entire surface of the mask layer 6 including the inner surface of the concave portion 6a. This width 10a is then subjected to the formation of a sidewall. Therefore, the thickness of the film 10a is important for determining the width of the sidewall, and is set to about several tens nm to one hundred and several tens nm. The material of the film 10a is non-doped polysilicon in terms of the etching selectivity with silicon nitride and the like, but other materials may be used to increase the etching selectivity with the silicon substrate.

Anisotropic etching is performed on the entire surface of the film 10a,
For example, RIE is performed. Thereby, as shown in FIG.
A sidewall 10 is formed inside the concave portion 6a of the mask layer 6.

Using the formed sidewalls 10 as a mask, the mask layer portion thereunder is etched, and then the pad oxide film 4 exposed by this etching and the semiconductor substrate 2 thereunder are etched. These etchings are performed by RIE or the like, and are preferably performed continuously under different conditions. Thus, a trench 2a is formed in the semiconductor substrate 2, as shown in FIG. The etching depth of the semiconductor substrate 2, that is, the depth of the trench 2a is, for example, 300
It is set to about 400 nm. The minimum pattern dimension of the trench 2a shown in FIG. 5 is smaller than the minimum pattern dimension F of the resist pattern 8 in the step of FIG. Therefore, when the pattern minimum dimension F of the resist pattern 8 is the resolution limit of the photolithography, the trench forming method according to the present embodiment makes it possible to form a trench having a width smaller than the resolution limit.

Next, as shown in FIG. 6, a buried insulating film 12 is deposited relatively thick on the entire surface, and the trench 2a is buried with an insulator. As the buried insulating film 12, a material having a good burying property is selected. In this case, TEOS (Tetraethyloxysila) is used.
ne or Tetraethylorthosilicate, Si (OC
_A silicon oxide film obtained by oxidizing and thermally decomposing the source gas of ₂ H ₅ ) ₄ ) with oxygen (O ₂ ) or ozone (O ₃ ) is used. In addition, a film such as silicon oxide (HDP (High Depth) formed in high-density plasma
nsity Plasma) film can also be used.

The surface of the buried insulating film 12 is polished, for example, by CMP (Chemical Mechanical Polishing). As a result, as shown in FIG. 7, the mask layer 6 is almost removed, and the buried insulating films 12 are separated from each other while being buried in each trench.

As shown in FIG. 8, a MOS transistor is formed. That is, after the mask layer 6 is completely removed, for example, the semiconductor substrate 2 is left while the pad oxide film 4 is left.
Ion implantation of p-type or n-type impurities under predetermined conditions,
A well 14 is formed on the inner surface of the substrate. This well 14
Is formed shallower than trench 2a. Next, the pad oxide film 4 is removed, and a new gate oxide film 16 whose thickness is strictly controlled is formed by thermally oxidizing the well surface, for example, by about 10 nm. The oxidation at this time is performed by, for example, a pyrogenic oxidation method. A gate electrode 18 of polysilicon or the like is formed on the gate oxide film 16,
An impurity is ion-implanted into the well 14 in a self-aligned manner to form an LDD (Lightly Doped Drain) impurity region 20a. Further, a sidewall insulating layer 22 is formed on the side surface of the gate electrode 18, an impurity is ion-implanted into the well 14 in a self-aligned manner with the sidewall insulating layer 22, and a high-concentration impurity region 20 b offset from the LDD impurity region 20 a outside the gate electrode. To form Source / drain impurity region 20
Is composed of these LDD impurity regions 20a and high concentration impurity regions 20b.

After that, through various steps such as wiring layer formation,
The semiconductor device 1 is completed.

In the method of manufacturing a semiconductor device according to this embodiment,
By forming sidewalls in the mask layer 6 for forming trenches, for example, trenches can be formed with a fine pattern width equal to or less than the limit resolution of photolithography. Therefore, a semiconductor device in which semiconductor elements are integrated at a high density can be provided.

Second Embodiment FIGS. 9 to 12 are sectional views showing the steps of manufacturing a semiconductor device according to this embodiment. In order to form the semiconductor device 30, a pad oxide film 4 and a mask layer 6 are stacked on a semiconductor substrate 2 and a resist pattern 8 is formed thereon as in the first embodiment.

Next, etching is performed using the resist pattern 8 as a mask. In this embodiment, the first etching is performed until the pad oxide film 4 is exposed through the mask layer 6 as shown in FIG. Thus, an opening 6b is formed in the mask layer 6.

After the resist pattern 8 is removed, as shown in FIG. 10, a film 32a to be a side wall is formed so as to cover the inner wall of the opening 6b and the exposed pad oxide film portion.
Is formed. In the first embodiment, as shown in FIG. 4, the sidewall 10 has a function as an etching mask for a portion of the mask layer therebelow, so that the material has to be made of, for example, non-doped polysilicon.
On the other hand, the film 32a serving as the sidewall in the present embodiment may be made of a material having a high selectivity with respect to the pad oxide film 4 and the silicon substrate, and is made of, for example, the same silicon nitride as the mask layer 6.

Thereafter, a sidewall 32 is formed in the opening 6b of the mask layer 6 (FIG. 11), and the trench 2a is formed in the semiconductor substrate 2 by anisotropic etching using the sidewall 32 and the mask layer 6 as a mask. (Fig. 1
2). Although not particularly shown, as in the first embodiment, a MOS transistor is formed and the semiconductor device 30 is completed through various steps such as a wiring layer.

According to the method of manufacturing the semiconductor device 30 of the present embodiment, the same effect as that of the first embodiment, that is, the trench can be formed with a fine pattern width equal to or less than the limit resolution of photolithography, and as a result, a high integration degree can be obtained. A semiconductor device can be provided.

The above-described first and second embodiments are not limited to the above description, and various modifications are possible. For example, the mask layer 6 can be composed of a plurality of layers having different etching rates. In this case, for example, in the first embodiment, it is desirable that the etching at the time of forming the concave portion 6a be completed when the lower layer film constituting the mask layer 6 is exposed. This is because, in this method, the depth of the concave portion 6a can be defined by the thickness of the upper layer film constituting the mask layer 6, and the depth of the concave portion 6a becomes uniform in the wafer surface.

After forming the trench 2a and before embedding an insulator in the trench 2a, it is desirable to thermally oxidize the inner surface of the trench to form a thin silicon oxide film. This is because the stress in the trench element isolation layer is reduced, and the isolation characteristics and the influence on the neighboring transistor formation region are reduced.

Further, in the description of the first and second embodiments, the trench is buried and then planarized by CMP or the like. However, the buried insulating film 12 can be etched back. However, the buried insulating film 1 is formed in
Since the isolation characteristic of the trench element isolation layer may be deteriorated when 2 retreats, in consideration of the in-plane variation of the etch-back, it is necessary to stop the etch-back at the bottom, that is, at a position above the substrate surface. . In that case, the buried insulating film 12 may protrude from the substrate surface, and thereafter, in photolithography when forming the gate electrode of the MOS transistor, a focus margin may not be obtained and the gate dimensions may vary. This is the reason why the planarization is performed by CMP or the like in the first and second embodiments. However, there is a process margin such that both the above-described degradation of the isolation characteristics and the variation in the size of the gate electrode do not occur. In such a case where there is no practical problem, there is no necessity to perform planarization by CMP or the like in the present invention.

[0032]

According to the method of manufacturing a semiconductor device according to the present invention, a trench can be formed with a fine pattern width equal to or less than the limit resolution of photolithography, and as a result, a semiconductor device with a high degree of integration can be provided. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention, showing up to the formation of a resist pattern for processing a mask layer.

FIG. 2 is a cross-sectional view showing the manufacturing process following FIG. 1 and shows up to the formation of the concave portion of the mask layer.

FIG. 3 is a cross-sectional view showing a manufacturing process following FIG. 2 up to formation of a film serving as a sidewall.

FIG. 4 is a cross-sectional view showing a manufacturing process following FIG. 3, up to formation of a sidewall.

FIG. 5 is a cross-sectional view showing a manufacturing process following FIG. 4, up to formation of a trench;

FIG. 6 is a cross-sectional view showing a manufacturing process following FIG. 5, up to deposition of a buried insulating film;

FIG. 7 is a sectional view showing a manufacturing process following FIG. 6;
Shows after P.

FIG. 8 is a cross-sectional view showing a manufacturing process following FIG. 7;
The steps up to the formation of the S transistor are shown.

FIG. 9 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention, showing up to the formation of an opening in a mask layer.

FIG. 10 is a cross-sectional view showing the manufacturing process following FIG. 9, up to formation of a film serving as a sidewall.

11 is a cross-sectional view showing a manufacturing process following FIG. 10;
The steps up to the formation of the sidewall are shown.

FIG. 12 is a cross-sectional view showing a manufacturing process following FIG. 11;
The steps up to the formation of a trench are shown.

[Explanation of symbols]

1, 30 semiconductor device, 2 semiconductor substrate, 2a trench, 4 pad oxide film, 6 mask layer, 6a recess, 6
b ... opening, 8 ... resist pattern, 10, 32 ... sidewall, 10a, 32a ... sidewall film, 12 ... buried insulating film, 14 ... well, 16 ... gate oxide film, 18 ... gate electrode, 20 ... Source / drain impurity region, 20a LDD impurity region, 20b high concentration impurity region, 22 sidewall insulating layer, F minimum size of resist pattern.

Claims (11)

[Claims] A step of forming a mask layer on the main surface side of the semiconductor substrate; a step of forming a recess in the surface of the mask layer; a step of forming a sidewall in the recess of the mask layer; Etching a mask layer portion below the sidewall using the wall as a mask, etching the semiconductor substrate using the mask layer and the sidewall as a mask, and forming a trench on the surface of the semiconductor substrate; A method of manufacturing a semiconductor device, comprising: depositing an insulator on a substrate to fill the groove; and removing the insulator above a main surface of the mask layer and the semiconductor substrate. 2. The method according to claim 1, wherein the step of forming the recess includes a step of etching the mask layer from a surface using a photoresist pattern formed on the mask layer as a mask, wherein the groove formed in the semiconductor substrate has a minimum pattern. 2. The method according to claim 1, wherein a dimension is smaller than a resolution limit at the time of forming the photoresist pattern. 3. The method according to claim 1, wherein said mask layer is made of silicon nitride, and further comprising a step of forming a pad oxide film made of silicon oxide on a main surface of said semiconductor substrate before said step of forming said mask layer. The manufacturing method of the semiconductor device described in the above. 4. The method according to claim 1, wherein said sidewall is made of polycrystalline or amorphous silicon. 5. The method according to claim 1, wherein the step of removing the mask layer and the insulator includes a step of polishing the surface of the insulator deposited by filling the trench. . 6. In the flattening step, chemical mechanical polishing (C
6. The method according to claim 5, wherein (MP) is used. 7. An insulator is formed by oxidizing or thermally decomposing tetraethyloxirane or tetraethylorthosilicate (TEOS) with oxygen or ozone using a chemical vapor deposition (CVD) method. A method for manufacturing a semiconductor device according to claim 1. 8. A step of forming a mask layer on the main surface side of the semiconductor substrate; a step of forming an opening in the mask layer; a step of reducing the size of the opening of the mask layer; Etching the semiconductor substrate using the reduced-size mask layer as a mask to form a groove (trench) on the surface of the semiconductor substrate; depositing an insulator over the entire surface to fill the groove; Removing the insulator above the main surface of the layer and the semiconductor substrate. 9. The step of forming the opening includes a step of etching the mask layer from a surface using a photoresist pattern formed on the mask layer as a mask, wherein the groove formed in the semiconductor substrate has 9. The method according to claim 8, wherein a minimum dimension is smaller than a resolution limit at the time of forming the photoresist pattern. 10. The method according to claim 1, wherein the mask layer and the side wall are made of silicon nitride, and a step of forming a pad oxide film made of silicon oxide on a main surface of the semiconductor substrate is provided before the step of forming the mask layer. A method for manufacturing a semiconductor device according to claim 8. 11. The method according to claim 8, wherein the step of reducing the size of the opening in the mask layer includes the step of forming a sidewall in the opening.