JP2000089954A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor capable of surely executing exceptional processing for exceptional information generated by an instruction executed speculatively without depending upon a register resource in a CPU and reducing the throughput of the CPU by using comparatively inexpensive constitution. SOLUTION: In the information processor, a CPU 10 constituting an arithmetic processing unit is provided with an exception detector 11 constituting an exception detecting means, an exception canceling device 12 or a pass storing register R3 constituting an exceptional information invalidating means, an exception processor 13 constituting an exception processing means, and an exception address control part 14 constituted of an exceptional information start address register R1 and an exceptional information stack pointer register R2 and an external memory 20 constituting an external storage device is provided with an exceptional information storing device 21 constituting an exceptional information storing means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to a good information processing apparatus applied to a computer having an exception handling function. Current computer systems attempt to improve processing performance by increasing the number of instructions that can be executed at a time, that is, instruction level parallelism.

The degree of instruction-level parallelism depends on the number of instructions (basic blocks) that can be optimized at once by a compiler. To increase the number of instructions in a basic block, a technique called "speculative execution processing of instructions" is used. "It has been known. "Speculative execution of instructions" refers to "speculatively" executing instructions that are not substantially restricted by the execution order at an arbitrary timing in performing arithmetic processing.
By speculative execution of such an instruction, it is possible to increase the number of instructions that can be optimized with the advance execution of an instruction having a large latency.
Processing performance can be improved.

When an instruction is speculatively executed by a general-purpose processor, exception processing of an instruction speculatively executed before an execution path is determined is performed for an instruction that may cause an exception. Therefore, a method is adopted in which exception processing is suppressed (prohibited) and the exception processing is executed after the execution path is determined. When an exception occurs in a plurality of speculatively executed instructions, a register for securing exception information of each instruction is required. The number of instructions that can be executed speculatively is determined by the register resources.

[0004]

2. Description of the Related Art A schematic configuration of a conventional processor (arithmetic processing unit: hereinafter referred to as a CPU) having an exception handling function will be described with reference to FIG. As shown in FIG.
The exception handling function realized inside the PU 10 ′ is roughly realized by the exception detection device 11, the exception cancellation device 12, the exception handling device 13, and the exception information storage register 15.

The exception detector 11 detects an exception that has occurred in an instruction executed speculatively, and stores the exception in a predetermined address of an exception information storage register 15 provided in an internal register of the CPU 10 '. The exception cancellation device 12
A process of invalidating (cancelling) the exception information of the speculatively executed instruction that is not on the execution path among the exception information stored in the exception information storage register 15 is performed.

The exception handling device 13 reads out exception information of an instruction speculatively executed on an execution path from among the exception information stored in the exception information storage register 15 and executes a predetermined exception process. A specific exception handling operation will be described with reference to the timing chart of FIG.

In FIG. 9, CLK is an operation clock for exception processing, COM1 is an instruction executed speculatively, COM2 is an instruction for determining an execution bus, and COM3 is an instruction for reading exception information. Each instruction COM1, COM2, COM3
Are fetch (Fetch), decode (Decode), and instruction execution (Execut) synchronized with the operation clock CLK, respectively.
e), which is executed based on a well-known procedure of writing.

As shown in FIG. 9, when the exception detector 11 detects the occurrence of an exception in the speculatively executed instruction COM1, the exception processing is suppressed or prohibited, and the timing T ₀₄ of the operation clock CLK, ie, the write timing Then, the exception information is stored in the exception information storage register 15 inside the CPU 10 '. Here, the reason why the exception processing is suppressed or prohibited when the occurrence of the exception is detected is that the exception processing cannot be performed on the speculatively executed instruction before the execution path is determined.

Next, after the execution path is determined by the execution path determination instruction COM2, of the exception information stored in the exception information storage register 15, the exception information of the instruction that is not on the execution path but is speculatively executed is: Operation clock CL
K timing T _14, that is canceled by the exception cancellation device 12 at the write timing. on the other hand,
After the execution path is determined, among the exception information stored in the exception information storage register 15, for the exception information of the speculatively executed instruction on the execution path, the operation clock CL is used.
At the timing T _{24 of} K, that is, at the write timing, the exception information is read (acquired) by the exception information read command COM3, and the exception processing device 13 executes a predetermined exception process.

[0010]

In an information processing apparatus having an exception handling function as described above, if a plurality of instructions are speculatively executed before an execution path is determined, exception information is provided for each instruction. Need to be stored in a register inside the CPU, the exceptional information occupies a register inside the CPU which is more expensive than an external memory provided outside the CPU, and the processing performance of the CPU cannot be improved. In addition, there is a problem that the capacity of the register must be increased according to the number of instructions to be executed speculatively.

[0011] The present invention solves the above-described problem, and enables exception information generated in an instruction executed speculatively to have a relatively inexpensive configuration and to reduce the processing power of the CPU without depending on register resources inside the CPU. An object of the present invention is to provide an information processing apparatus capable of reliably performing exception processing without lowering.

[0012]

In order to achieve the above object, according to the first aspect of the present invention, before the execution path is determined,
Exception detecting means for detecting an exception that has occurred in the speculatively executed instruction; exception information storing means for storing at least information on the exception at a predetermined address; and storing the exception information in the exception information storing means after the execution path is determined. Exception information generated in the speculatively executed instruction on the execution path from among the exception information, and exception processing means for executing exception processing, and after the execution path is determined, stored in the exception information storage means. An exception information invalidating means for invalidating exception information generated on the speculatively executed instruction, which is not on the execution path, of the exception information, The exception processing means and the exception invalidating means are provided in the same arithmetic processing device, and the exception information storage means is provided in a predetermined external storage device outside the arithmetic processing unit. Wherein the arithmetic processing unit determines whether the exception information is valid / invalid based on information on the execution path corresponding to the exception information held by the exception information invalidating means, and It is characterized in that execution of processing is controlled.

According to a second aspect of the present invention, in the information processing apparatus according to the first aspect, the external storage device is a cache memory provided outside the arithmetic processing unit, and the cache memory is normally A data storage unit for holding a copy of the memory data or the exception information, and a tag storage unit corresponding to the information held in the data storage unit and holding at least a flag bit for determining the content of the information. Determining information held in the data storage unit based on the flag bit, and prohibiting data read and write operations to the cache memory when the exception information is held. Features.

Further, the invention described in claim 3 is the invention according to claim 1.
The information processing apparatus according to claim 1, wherein the external storage device is a large-capacity memory device provided outside the arithmetic processing device, and the external storage device is detected by the exception detection means between the arithmetic processing device and the memory device. And an address conversion means for converting the address of the exception information stored in the memory device from a logical address to a physical address.

According to the information processing apparatus having such a configuration,
When an exception occurs in a speculatively executed instruction, the CPU
(Operation processing unit) Exception information is saved and stored in hardware in an external memory (external storage device) such as a relatively inexpensive cache memory or a large-capacity main storage device (memory device) for internal registers. After the execution path of the speculatively executed instruction is determined, based on the information on the execution path including the exception information, for the instruction to be actually executed,
The exception information stored in the external memory is read out by software, and exception processing is executed. On the other hand, for instructions that should not be executed, the exception information is canceled.

Here, since the capacity of an external memory such as a cache memory is generally sufficiently large as compared with the capacity of a register provided inside the CPU, even if an exception occurs due to a plurality of speculatively executed instructions, All these exception information are stored. Therefore, as shown in FIG. 8, the exception information generated in the speculatively executed instruction is
Compared to the conventional configuration of storing in an internal register, the configuration is relatively inexpensive, and even if an exception occurs in a plurality of speculatively executed instructions without lowering the processing capability of the CPU, Each exception can be reliably handled.

(Basic Configuration) The basic configuration of the information processing apparatus according to the present invention will be described with reference to FIG. As shown in FIG. 1, an information processing apparatus according to the present invention includes, in a CPU 10 constituting an arithmetic processing unit, an exception detecting apparatus 11 constituting an exception detecting means and an exception canceling apparatus 12 constituting an exception information invalidating means. Or, it is composed of a path storage register R3, an exception processing device 13 constituting an exception processing means, an exception information start address register (hereinafter, referred to as a start address register) R1, and an exception information stack pointer register (hereinafter, a stack pointer register) R2. And an exception address control unit 14
An exception information holding device 21 that constitutes exception information storage means is provided inside the external memory 20 that constitutes the external storage device.

Before the instruction path is determined, the exception detection device 11 detects an exception that has occurred in the speculatively executed instruction and stores a predetermined memory space defined in the external memory 20 into the exception information holding device. 21 as exception information at a predetermined address. Exception cancellation device 1
After the execution path is determined, the processing 2 invalidates (cancels) the exception information of the speculatively executed instruction that is not on the execution path among the exception information stored in the exception information holding device 21.

Here, as a method of invalidating the exception information,
As described above, in addition to the method of canceling the exception information stored in the exception information holding device, information on the validity / invalidity of the execution path is stored in advance in the path storage register R3, and the exception information is read prior to the exception processing. At times, a method may be employed in which exception processing is disabled (not executed) for exception information on an invalid path based on the information on the execution path. Details will be described later in Examples.

After the execution path is determined, the exception processing unit 13 extracts exception information of the speculatively executed instruction on the execution path from the exception information stored in the exception information holding unit 21.
Read and execute predetermined exception processing. Further, the start address register R1 and the stack pointer register R2 provided in the exception information address control unit 14 control the setting of the storage / read address of the exception information stored in the exception information holding device 21 described above. Details will be described later.

Next, the instruction execution processing of the information processing apparatus according to the present invention will be described with reference to the flowchart of FIG. 2 and the timing chart of FIG. Note that steps equivalent to those in the timing chart shown in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG.
First, the stack pointer register R2 is
The stack point is set in (S11), and then, FIG.
As shown in (5), the speculative execution command COM1 is instructed (S12).

The instruction COM1 executed speculatively as described above.
In the case where an exception occurs (S13), exception processing cannot be performed on an instruction executed speculatively before the execution path is determined, so that exception processing is suppressed, and the exception processing is suppressed at timing T ₀₄ , that is, at the write timing. The exception detection device 11 outputs a request for storing exception information to the address indicated by the stack pointer register R2 to the exception information holding device 21 together with the corresponding exception information. Then, in response to this storage request, the corresponding exception information is stored at the specified address of the exception information holding device 21 at a predetermined timing _T0n (S14).

Next, an execution path determination command COM2
After the execution path is determined (S15), the exception information holding device 2
1 of the exception information stored in
Regarding the exception information of the executed instruction (S16), the operation
Lock CLK timing T _{twenty four}, Ie writing ties
In response to the exception information read command COM3,
Start address indicated by the address register R1
Stack pointer specified by the stack pointer register R2.
The request for reading the exception information sequentially
It is output to the exception information holding device 21 together with the dress. So
Then, by this read request, the corresponding exception information is
Predetermined timing T_0nRead from the exception information holding device 21
Issued (acquired) and given by the exception handling device 13
External processing is executed (S18).

On the other hand, after the execution path is determined by the execution path determination instruction COM2, among the exception information stored in the exception information holding device 21, the exception information of the instruction that is not on the execution path but is speculatively executed is: At the timing T ₁₄ of the operation clock CLK, that is, at the write timing,
Invalidating (cancelling) exception information using the following two methods
The process is executed (S17).

The first approach is not on execution path, the exception information of the instruction that speculatively executed, to the exception information holding device 21 from the exception cancellation device 12 at a timing T ₁₄ of the operation clock CLK, a cancellation request Is output, and the corresponding exception information is canceled, that is, invalidated at the timing T _1n . The second approach, rather than on the execution path, when storing exception information generated in instruction speculatively executed, at the timing T ₀₄ of the operation clock CLK to the exception information holding device 21, the speculative instruction which execution path The information (flag) indicating whether the exception has occurred in step (1) is added to the exception information and stored, and after the execution path is determined, the information indicating which execution path is valid is stored in the path storage register R3. . Then, the exception information read request output to the exception information holding device 21 at timing T ₁₄ of the operation clock CLK, the appropriate exception information, and information (flag) indicating that the an exception information which execution path, the path store By comparing with the information indicating which execution path is valid stored in the register R3, only exception information determined as a valid execution path is exception-processed. Does not perform exception handling. That is, it is invalidated as non-execution at the timing _T1n .

As described above, according to the information processing apparatus of the present invention, all the algorithms related to the speculative execution instruction processing are processed by hardware. In particular, the processing for storing exception information in the cache memory or the memory device is automatically performed by hardware when an exception occurs in a speculative execution instruction. Conventionally, for example, in a super scalar processor with a strict exception architecture, when speculative execution is performed by Out-OF-Order, a buffer called a reorder buffer or a history buffer inside the CPU is required to guarantee the order of programs. However, in the present invention, the storage location of the exception information is not a register inside the CPU but an external memory such as a cache memory or a memory device. The processing performance is prevented from deteriorating.

Therefore, when an exception occurs in an instruction to be executed speculatively, predetermined information relating to the exception information is added and stored in an external memory so that exception processing can be performed without being affected by register resources inside the CPU. Can be executed reliably.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Next, a first embodiment of the information processing apparatus according to the present invention will be described with reference to FIG. The same components as those described above are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIG. 4, the information processing apparatus of this embodiment includes a CPU 10 and a cache memory 20a. The CPU 10 includes an exception detecting device 11, an exception canceling device 12, an exception processing device 13, a start address register R1, a stack pointer register R2, and an incrementer INC. On the other hand, the cache memory 20a stores the cache tag device 21 in a predetermined memory space.
a, 21ba and cache data devices 22a, 22b
Is configured.

Here, the start address register R1 holds the start address of the exception information stored in the cache memory 20a, while the stack pointer register R2 stores the last address of the stored exception information. Will be retained. The incrementer INC increments the stack point held in the stack pointer register R2, that is, the final address of the exception information by one every time the exception information is stored.

The cache tag devices 21a, 21b
Is a Valid bit indicating whether or not the memory line storing the exception information is valid;
a and 21b are composed of an Exp flag indicating whether the content stored in the memory 21b is a copy of normal memory data or exceptional information, and a cache tag Tag. The cache data devices 22a and 22b are associated with information stored in the cache tag devices 21a and 21b.
A copy of memory data or predetermined exception information is stored. Specifically, the cache data devices 22a, 22
b, a flag indicating whether the exception information is valid,
Instruction address, instruction type, exception type, effective address (LD / ST instruction), destination register number, whether the exception occurred due to the exception of the preceding instruction, and which execution path Information such as whether or not speculative execution is being performed is held.

In the information processing apparatus having such a configuration,
When an exception occurs in the speculatively executed instruction, the exception detection device 11 outputs a request for storing exception information to the cache memory 20a by specifying the address AD indicated by the stack point, and the exception information is stored in the cache data device 22a or the cache data device 22a. 2
2b is stored in a predetermined address space. The stack point held by the stack pointer register R2 is used to store the next exception that occurs in the speculatively executed instruction in the next address space.
C is incremented by one.

Here, when the data stored in the address space of the cache data device 22a or 22b is the exception information, the Exp tag of the cache tag device 21a or 21b is used.
“1” is set in the flag, and “0” is set if the stored data is a copy of normal memory data. Therefore, when the Exp flag is “1”, reading of data from the corresponding memory line,
The write operation is prohibited and the cache data device 22
This prevents erroneous overwriting or reading of the exception information stored in a or 22b as normal data.

Next, after the execution path is determined, the exception information of the instruction that is not on the execution path but executed speculatively is as follows:
The cancellation information on the execution path that becomes invalid from the exception cancellation device 12 is transmitted to the cache tag devices 21a and 21b.
And transmitted to the cache data devices 22a and 22b,
By clearing the flag indicating whether the exception information in the cache data devices 22a and 22b is valid to "0", the exception information is canceled.

On the other hand, after the execution path is determined, the exception information of the speculatively executed instruction on the execution path is read from the start address stored in the start address register R1 by the stack pointer register by the exception information read instruction. For the address AD up to the stack point held in R2, a request for reading exception information is sequentially instructed, and the cache tag device 21a or 21
1b, and if the exception information is valid (flag "1"), the exception information of the corresponding address space of the cache data device 22a or 22b is sent to the exception processing device via the multiplexer MUX. 13 is read (acquired) and predetermined exception processing is executed.

(Second Embodiment) Next, a second embodiment of the information processing apparatus according to the present invention will be described with reference to FIG. In addition, about the structure equivalent to the above-mentioned Example,
The same reference numerals are given and the description is omitted. As shown in FIG. 5, the information processing apparatus according to the present embodiment includes a CPU 10 and a large-capacity memory device 20b. The CPU 10 includes an exception detecting device 11, an exception canceling device 12, The exception processing device 13 includes a start address register R1, a stack pointer register R2, and an incrementer INC.
Is configured to have a predetermined memory space 21.

Here, in the memory space 21, a flag indicating whether the exception information is valid, an instruction address, an instruction type, an exception type, an effective address (LD / ST instruction), a destination register Information such as the number, whether or not the exception occurred due to the exception of the preceding instruction, and which execution path is performing speculative execution, etc., are stored as a set of information in association with each other. .

Further, between the CPU 10 and the memory device 20b, the address AD of the exception information output from the exception detecting device 11 and the exception processing device 13 is converted from a logical address to a physical address and sent to the memory device 20b. A memory management unit MMU is provided. In the information processing apparatus having such a configuration, when an exception occurs in a speculatively executed instruction, the exception detection device 11
Outputs an exception information storage request to the memory device 20b by specifying the address AD indicated by the stack point, and the exception information is stored at a predetermined physical address in the memory space 21. Then, the stack point held by the stack pointer register R2 is incremented by one by the incrementer INC in order to store the next exception that occurs in the speculatively executed instruction at the next address.

Next, after the execution path is determined, the exception information of the instruction which is not on the execution path but executed speculatively is as follows:
The exception canceling device 12 sends cancellation information on the execution path that becomes invalid to the memory space 21 and clears the flag indicating whether the exception information in the memory space 21 is valid to “0”. Is executed.

On the other hand, after the execution path is determined, the exception information of the instruction speculatively executed on the execution path is read by the exception information read instruction and the start address register R1 is read.
A from the start address held by the stack pointer to the stack point held by the stack pointer register R2
Regarding D, a request for reading the exception information is sequentially instructed. Here, the address AD is converted from a logical address to a physical address by the memory management unit MMU, a predetermined address in the memory space 21 is designated, and when the corresponding exception information is valid, the address AD is read by the exception processing device 13. Is issued (acquired), and predetermined exception processing is executed.

(Third Embodiment) Next, a third embodiment of the information processing apparatus according to the present invention will be described with reference to FIG. The same components as those in the above-described first embodiment are denoted by the same reference numerals, and description thereof will be omitted. FIG.
As shown in FIG. 7, the information processing apparatus of the present embodiment includes a CPU 10 and a cache memory 20a, as in the first embodiment, and the CPU 10 includes an exception detecting device 11, an exception processing device 13, a start address register R1. , A stack pointer register R2, an incrementer INC, and an exception path storage register R3, while the cache memory 20a includes cache tag devices 21a, 21b and cache data devices 22a, 22b. .

That is, the information processing apparatus of this embodiment is different from the first embodiment in that the exception canceling device 12
, An exception path storage register R3 is provided. After the path of the speculatively executed instruction is determined, information on the determined execution path is stored in the exception path storage register R3. Is done. In the information processing device having such a configuration, when an exception occurs in an instruction executed speculatively, the exception detection device 11 specifies the address AD indicated by the stack point and specifies the cache memory 20a.
Is output to the cache data device 22a or 22b, and the exception information is stored in a predetermined address space of the cache data device 22a or 22b. The stack point held by the stack pointer register R2 is incremented by one by the incrementer INC in order to store the next exception that occurs in the speculatively executed instruction in the next address space.

Here, when the data stored in the cache data device 22a or 22b is the exception information, the Exp flag of the cache tag device 21a or 21b contains "
When "1" is set and the stored data is a copy of normal memory data, "0" is set.Thus, when the Exp flag is "1", data for the corresponding memory line is set. Read and write operations are prohibited, and erroneous overwriting or reading of exception information is prevented.

Next, when the execution path is determined, information on the determined execution path is stored in the exception path storage register R3. The exception information is read from the cache memory 20a by the exception information read instruction.
The flag indicating which execution path has been speculatively executed is set as additional information with respect to the exception information read out in the above, and the information on the execution path held in the exception path storage register R3. Compare and collate.

Then, based on the collation result, predetermined exception processing is executed for exception information where both information matches, and exception processing is not performed (prohibition or non-execution) for exception information that does not match. To Such reading of the exception information, collation, and determination of whether or not to execute the exception processing are executed for each address from the start address stored in the cache memory 20a to the stack point.

(Fourth Embodiment) Next, a fourth embodiment of the information processing apparatus according to the present invention will be described with reference to FIG. The same components as those in the above-described second and third embodiments are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 7, the information processing apparatus of this embodiment
A PU 10 and a large-capacity memory device 20b;
U10 comprises an exception detection device 11, an exception processing device 13, a start address register R1, a stack pointer register R2, an incrementer INC, and an exception path storage register R3, while the memory device 20b
Is configured to have a predetermined memory space 21.

That is, the information processing apparatus of the present embodiment is different from the second embodiment in that
, An exception path storage register R3 is provided. After the path of the speculatively executed instruction is determined, information on the determined execution path is stored in the exception path storage register R3. Is done. In the information processing device having such a configuration, when an exception occurs in an instruction executed speculatively, the exception detection device 11 specifies the address AD indicated by the stack point and outputs a storage request for exception information to the memory device 20b. Then, the exception information is stored at a predetermined physical address in the memory space 21. Then, the stack point held by the stack pointer register R2 is incremented by one by the incrementer INC in order to store the next exception that occurs in the speculatively executed instruction at the next address.

Next, when the execution path is determined, information on the determined execution path is stored in the exception path storage register R3. A flag indicating which execution path has been speculatively executed is set as additional information for the exception information read from the memory space 21 to the exception processing device 13 by the exception information read instruction. ,
The information on the execution path stored in the exception path storage register R3 is compared and collated.

Next, based on the collation result, predetermined exception processing is executed for exception information where both information matches, and exception processing is not performed (prohibition or non-execution) for exception information that does not match. To Such reading of the exception information, collation, and determination of whether or not to execute the exception processing are executed for each address from the start address stored in the cache memory 20a to the stack point.

[0050]

As described above, according to the information processing apparatus of the present invention, when an exception occurs in a speculatively executed instruction, a relatively inexpensive cache memory or a large capacity Exception information is saved and stored by hardware in an external memory such as a memory device, and after the execution path of the speculatively executed instruction is determined, the execution should be actually performed based on information on the execution path including the exception information. For the instruction, the exception information stored in the external memory is read out by software, and the exception processing is executed. On the other hand, for the instruction that should not be executed, the exception information is canceled, thereby achieving a relatively inexpensive configuration. Even if an exception occurs in a plurality of speculatively executed instructions without lowering the processing performance of the CPU, it is possible to reliably process each exception. Can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of an information processing apparatus according to the present invention.

FIG. 2 is a flowchart of speculative execution instruction processing of the information processing apparatus according to the present invention.

FIG. 3 is a timing chart of speculative execution instruction processing of the information processing apparatus according to the present invention.

FIG. 4 is a schematic configuration diagram illustrating an information processing apparatus according to a first embodiment.

FIG. 5 is a schematic configuration diagram illustrating an information processing apparatus according to a second embodiment.

FIG. 6 is a schematic configuration diagram illustrating an information processing apparatus according to a third embodiment.

FIG. 7 is a schematic configuration diagram illustrating an information processing apparatus according to a fourth embodiment.

FIG. 8 is a schematic configuration diagram of a conventional CPU having an exception handling function.

FIG. 9 is a timing chart in a conventional exception handling function.

[Explanation of symbols]

 10, 10 'CPU 11 Exception detection device 12 Exception cancellation device 13 Exception processing device 14 Exception address control unit 15 Exception information storage register 20 External memory 20a Cache memory 21 Exception information holding device 21a, 21b Cache tag device 22a, 22b Cache data device 23a, 23b Comparator 24 Multiplexer 30 Memory Management Unit R1 Start Address Register R2 Stack Pointer Register R3 Exception Path Storage Register INC Incrementer

Claims (3)

[Claims] An exception detecting means for detecting an exception occurring in an instruction executed speculatively before an execution path is determined; an exception information storing means for storing at least information on the exception at a predetermined address; After the execution path is determined, the exception information stored in the exception information storage unit, the exception information generated in the speculatively executed instruction on the execution path is read out, and exception processing means for executing exception processing, After the execution path is determined, the exception information invalidating means for invalidating exception information generated in the speculatively executed instruction that is not on the execution path among the exception information stored in the exception information storage means. In the information processing apparatus, the exception detection unit, the exception processing unit, and the exception invalidation unit are provided in the same arithmetic processing unit, and the exception information storage unit Is provided in a predetermined external storage device outside the arithmetic processing device, the arithmetic processing device is held in the exception information invalidating means, based on information on the execution path corresponding to the exception information, An information processing apparatus for determining whether the exception information is valid or invalid, and controlling execution of the exception processing. 2. The external storage device is a cache memory provided outside the arithmetic processing unit, wherein the cache memory includes a data storage unit that holds a copy of normal memory data or the exception information, A tag storage unit corresponding to the information held in the data storage unit and holding a flag bit for determining at least the content of the information;
Determining the information held in the data storage unit based on the flag bit, and prohibiting data read and write operations to the cache memory when the exception information is held The information processing apparatus according to claim 1, wherein: 3. The external storage device is a large-capacity memory device provided outside the arithmetic processing device, wherein the external storage device is detected by the exception detecting means between the arithmetic processing device and the memory device. 2. The information processing apparatus according to claim 1, further comprising address conversion means for converting an address of the exception information stored in the memory device from a logical address to a physical address.