JP2000088924A - Logic integrated circuit with diagnosing function and method for designing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve productivity without lowering a defective detection ratio by shortening a diagnosing necessary time of a logic integrated circuit containing a shift scanning type diagnosing circuit. SOLUTION: If flip-flops separated at a predetermined distance or more are existed in the case of constituting a scanning shift register by connecting flip-flops FF1 to FFi+1 for constituting a logic circuit, a transit flip-flop FFd is disposed between the flip-flops, and the flip-flops are connected therebetween via the transit flip-flop.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diagnostic technique for a semiconductor logic integrated circuit, and more particularly to a technique which is effective when applied to shorten a test time in a logic integrated circuit incorporating a shift scan type diagnostic circuit.

[0002]

2. Description of the Related Art Conventionally, there is a logic integrated circuit provided with a diagnostic function of a shift scan system. The shift scan type diagnostic circuit connects a plurality of flip-flops constituting a logic circuit in a serial form to enable a shift register to be configured, and at the time of diagnosis, scans test data from an input pin into the shift register and scans the shift register for test data. A technology that allows efficient diagnosis by operating by directly putting data inside and scanning out data held in a flip-flop at a certain point to an output pin using a shift register. It is.

[0003]

In a conventional logic integrated circuit incorporating a shift scan type diagnostic circuit, a shift register is formed by connecting only flip-flops constituting a logic circuit in a serial form. For example, as shown in FIG. 7, when the distance between two flip-flops to be connected is large, the signal transmission delay time tpd between the two flip-flops is large, so that the delay time is large. There was a problem that it became a bottleneck and the total test time became longer.

That is, in the diagnostic circuit of the shift scan system, data transfer between flip-flops constituting a shift register is performed by a clock signal called a scan clock. Defines the cycle of the scan clock. Therefore, if there is a path having an extremely long delay time, the cycle of the shift scan clock becomes considerably large, and the total test time becomes extremely long. As a result, there is a problem that the productivity is reduced or that a failure detection rate has to be sacrificed when the test is completed within a limited time.

An object of the present invention is to shorten the period required for diagnosis of a logic integrated circuit having a built-in shift scan type diagnosis circuit, and to improve the productivity without lowering the defect detection rate.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, when a flip-flop circuit constituting a logic circuit is connected to form a scan shift register, if a flip-flop circuit that is separated by a predetermined distance or more exists, the flip-flop circuit is interposed between the flip-flop circuits. A relay flip-flop circuit is arranged, and the flip-flop circuits are connected via the relay flip-flop circuit.

More specifically, the flip-flop circuit includes a flip-flop circuit that can form a shift register for normal logic and scan, and a flip-flop circuit for relay that can form a shift register for scan. The relay integrated flip-flop circuit is inserted in a portion where the distance between the configurable flip-flop circuits is long, thereby realizing a logic integrated circuit with a diagnostic function.

According to the above-described means, since there is no path with an extremely long delay time, the cycle of the shift scan clock can be reduced, thereby shortening the total test time and reducing the defect detection rate. And the productivity can be improved.

In the above case, the relay flip-flop circuit does not contribute to forming the original logic of the logic integrated circuit. Therefore, the relay flip-flop circuit is designed as much as possible within a range having the functions necessary for forming the shift register. It is desirable to select a circuit type that is easy and has a small number of elements. Specifically, the flip-flop circuit capable of configuring the normal logic and scan shift register includes a normal logic flip-flop circuit and a scan flip-flop circuit, and the scan flip-flop circuit and the relay flip-flop circuit The circuit has a similar circuit configuration. This facilitates the design of the relay flip-flop.

The relay flip-flop circuit is a master-slave flip-flop circuit in which two level trigger flip-flops are cascaded. This makes it possible to reduce the test time while minimizing the increase in the size of the semiconductor chip.

Further, the logic integrated circuit is provided with a pseudo random number generation circuit for randomly generating test data shifted by the scan shift register. In such a case, the speed of the self-test can be increased by including the relay flip-flop circuit.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the relationship between a flip-flop and a general logic section such as a random logic or a combinational logic in a gate array as a logic LSI having a diagnostic function according to the present invention. In this embodiment, the internal logic is represented by two general logic units LG1 and LG2 for the sake of convenience in the drawing. Also, for ease of understanding, it is assumed that signals are input from the left side of the drawing, transmitted to the right side, and output.

In FIG. 1, 2 is provided on the input side of the general logic section LG1.
Two flip-flops FF11 and FF12 are arranged,
Similarly, two flip-flops FF31 and FF32 are arranged on the output side of the general logic unit LG2.
Three flip-flops FF21, FF22, FF23 are arranged between the general logic units LG1 and LG2.
During normal operation, these flip-flops FF11 to FF32 take in the signal input to the data terminal D in synchronization with the clock signal CK, and from the data output terminal Q to the next-stage general logic units LG1, LG2 or external output terminals. Operate to output.

In the LSI of this embodiment configured to have a diagnosis function, the flip-flops FF1 arranged before, after and between the general logic units LG1 and LG2 are provided.
1 to FF32 are connected in series to form a shift register. That is, each of the flip-flops FF11 to FF32 has a scan-in data terminal SID and a scan-out data terminal SO in the shift register operation in addition to the normal data terminal D and the output terminal Q.
D, the scan-in data terminal SID of the flip-flop IFFF is connected to the scan-out data terminal SOD of the preceding flip-flop FF-1, and the scan-out data terminal SOD of the FFi is connected to the scan-in data of the next flip-flop FFi + 1. Each is connected to the terminal SID.

The signal input to the scan-in data terminal SID is taken in synchronization with the scan clock signal C1 or C2 and output from the scan-out data terminal SOD.

In this embodiment, a clock generating circuit CPG for generating the normal clock signal CK and the scanning clock signals C1 and C2, and a pseudo random number generating circuit PRG for generating test data scanned in a shift register at the time of diagnosis. And a test result recovery circuit TSC for recovering data transferred from the shift register and outputting the data from an external terminal SDOUT. When the pseudo-random number generation circuit PRG is provided, the self-test can be sped up by having the relay flip-flop circuit.

Next, the gist of this embodiment will be described with reference to FIG.

In this embodiment, when the flip-flop circuits FF11 to FF32 forming the logic circuit are connected by the method described with reference to FIG. If the flip-flop circuits FFi and FFi + 1 exist,
As shown in FIG. 2, those flip-flop circuits FF
flip-flop circuit FFd for relay between i and FFi + 1
Are arranged between the preceding flip-flop circuit FFi and the relay flip-flop circuit FFd and between the relay flip-flop circuit FFd and the subsequent flip-flop circuit FFi.
And Fi + 1.

Further, in this embodiment, the relay flip-flop circuit FFd does not contribute to the construction of the original logic of the logic integrated circuit, so that the flip-flop circuit FFd has a function necessary for constituting the shift register. A circuit form that is as simple as possible and has as few elements as possible is selected. That is, a normal flip-flop that constitutes a logic is composed of a logic F / F section and a scan F / F section, whereas a relay flip-flop FFd is composed of only a scan F / F section. Circuit.

Thus, the increase in the size of the semiconductor chip due to the addition of the relay flip-flop can be minimized, and the scan F / F section of the original flip-flop can have almost the same configuration. There is little effort to newly design. Moreover, by registering this relay flip-flop as one cell in the cell library, automatic design using CAD (computer aided design) is facilitated. Moreover, in an LSI such as a gate array, the addition of the relay flip-flop is relatively easy.

FIG. 3 shows a part of the procedure for designing a logic integrated circuit to which the present invention is applied, particularly a part related to the design of a diagnostic circuit. To explain this design procedure in order, first,
A logic design of an integrated circuit having a desired function is performed (step S1). Next, a circuit cell such as a logic gate to be used is selected from a cell library based on a logic design document, and automatic placement and automatic wiring between cells are performed according to the logic design using CAD (step S2). At this time,
It also designs the wiring for the scan shift register that constitutes the diagnostic circuit.

Next, based on the wiring design data, the signal transmission delay time between flip-flops constituting the scan shift register is sequentially calculated from the length of the signal line (step S3). Then, it is determined whether or not the obtained delay time tpd is smaller than a predetermined time tmax (the cycle of the scanning clock to be used) tmax (step S4). As a result, if there is a flip-flop pair determined to be longer than the specified time tmax, the design is changed so that a relay flip-flop is inserted between the flip-flops (step S5), and the process returns to step S2 to perform CAD. The arrangement is performed using.

Then, the delay time tpd1 from the preceding flip-flop and the delay time tpd2 to the subsequent flip-flop of the inserted relay flip-flop are calculated, and these delay times tpd1 and tpd2 are set in advance. It is determined whether or not the time is shorter than the specified time tmax. If it is determined that the time is longer than the specified time tmax, another relay flip-flop is inserted between the flip-flops. The design is completed by performing the above operation for all flip-flops of the scan shift register (step S6).

FIG. 4A shows an example of the configuration of the flip-flop circuits FF11 to FF32 which can constitute the above-mentioned normal logic and scan shift registers, and FIG. 4B shows the relay flip-flop which can constitute the scan shift registers. The configuration example of the flip-flop FFd is shown.

As shown in FIG. 4A, the flip-flop circuits FF11 to FF32 have a set / reset function in which a logic F / F section capable of forming normal logic has a set terminal S and a reset terminal R. And a slave master flip-flop RS / FF.
The scan F / F section, which can constitute a scan shift register, is a set / reset signal forming circuit including two AND gates G1 and G2 to which a scan-in data terminal SID and a scan clock signal C1 are input. S
An output of the set / reset signal forming circuit SRG in the preceding stage of the scanning F / F unit is constituted by an RG and a level trigger flip-flop D-FF2, and a slave having a set / reset function constituting the logic F / F unit The set signal and the reset signal are input to the set terminal S and the reset terminal R of the master flip-flop, and the output Q of the logic F / F unit is connected to the level trigger type flip-flop D at the subsequent stage of the scan F / F unit. -Input to the data input terminal D of FF2.

The data input terminal of the level trigger flip-flop D-FF1 at the preceding stage of the scanning F / F section is used as the input terminal of the scan-in data SID at the time of the test, and the level trigger flip-flop D-FF2 at the subsequent stage.
Are output terminals of the scan-out data SOD.

On the other hand, the relay flip-flop FFd is
As shown in FIG. 4 (B), it is configured as a master-slave type flip-flop in which two level-triggered flip-flops D-FF1 and D-FF2 are connected in cascade, and a level-triggered flip-flop of a preceding stage is provided. The first scan clock C1 is supplied to the clock terminal of the flip-flop D-FF1, and the scan clock C1 is supplied to the clock terminal of the subsequent level-triggered flip-flop D-FF2.
And a second scanning clock C2 having a phase different from that of the first stage, the output Q of the preceding level trigger flip-flop D-FF1 is input to the input terminal of the subsequent level trigger flip-flop D-FF2.

FIG. 5A shows flip-flop circuits FF11 to FF32 which can constitute a scan shift register.
5B is a circuit diagram of the set / reset signal forming circuit SRG of the scanning F / F section, and FIG. 5B is a circuit diagram of the first level trigger flip-flop D-FF1 of the relay flip-flop FFd. Have been.

As shown in FIG. 5A, the set / reset signal forming circuit SRG of the scanning F / F section
Is a CMOS-NAND gate G11, a CMOS inverter INV1 connected to its output terminal, a CMOS inverter INV2 for inverting the clock C1, and INV.
2 with the output of 2 and scan-in data SID as input
It comprises an OS-NOR gate G12.

As shown in FIG. 5B,
The first level-triggered flip-flop D-FF1 of the relay flip-flop FFd is a CMOS inverter INV2 'for inverting the clock C1, and a clock which receives scan-in data SID as input and is clock-controlled by the output of INV2' and the clock C1. De inverter CIN
V1, a CMOS inverter INV1 'connected to its output terminal, and INV2'
And a clocked inverter CINV2 clocked by the clock C1.

The CMOS-NAND gate G shown in FIG.
11 and the clocked inverter CINV1 of (B), the CMOS-NOR gate G12 of (A) and the clocked inverter CINV2 of (B), and the inverters INV1, INV2 and (B) of (A). 5 corresponding to the inverters INV1 'and INV2' of FIG.
As is clear from comparison between (A) and (B), both are P
It can be seen that the numbers of -MOS and N-MOS are the same, and any circuit can be configured by changing the wiring pattern.

As described above, in this embodiment, the relay flip-flop FFd is a flip-flop circuit FF1 that can constitute a normal logic and scan shift register.
1 to FF32, a level trigger flip-flop D-FF1 having a configuration similar to the set / reset signal forming circuit SRG of the scanning F / F unit, and a level trigger flip-flop D-FF2 cascade-connected to this. And a flip-flop having a master-slave configuration. Therefore, the flip-flop circuit FF1
1 to FF32 for the scanning F / F section, and a relay flip-flop FFd with only a slight change.
Is very easy to design. In addition, since the level trigger type flip-flop is used, the circuit is simple and the number of elements is small, so that an increase in the size of the semiconductor chip can be minimized.

Here, the operation of the flip-flop circuits FF11 to FF32 which can configure the shift register for normal logic and scan shown in FIG.
During normal operation, the clock CK is input in a state where the scanning clocks C1 and C2 are stopped, so that the input data Din from the preceding logic gate input to the data terminal D at that time is output from the RS flip-flop RS. FF
And the output data Dout is output accordingly.

On the other hand, when the test data is to be scanned into each of the flip-flop circuits FF11 to FF32 during the test, as shown in FIG.
In synchronization with the scan-in data SID output from, the scan clocks C1 and C2 are input in the order of C1 and C2 by the number corresponding to the number and position of the flip-flop circuits FF11 to FF32 for which data is desired to be set. Then, the scan-in data SID is taken into the flip-flop D-FF1 at the preceding stage of the scan F / F section by the scan clock C1, and the RS flip-flop RS · FF is set or reset according to the latch data.

Subsequently, the output of the RS flip-flop RS / FF is changed to the scan F by the scan clock C2.
The data is taken into the flip-flop D-FF2 at the subsequent stage of the / F section and output to the scan-out terminal. Therefore, it is as if the flip-flop D-
The FF1 and the subsequent flip-flop D-FF2 perform the same operation as the master-slave configuration flip-flop, and the scan-in data is successively transmitted to the next-stage flip-flop.

Further, the data scanned in as described above at the time of the test is input to the general logic units (LG1, LG2) using the clock CK to operate, and at a certain time, the logic signals of the flip-flops FF11 to FF32 are used. The data held in the F / F unit (RS flip-flop) is transferred to the scan data output terminal SDOU using the scan path.
When the data is output from T, the data of the logic F / F unit (RS flip-flop) is determined from the time when the data is determined.
As shown in (B), the scan clocks C1 and C2 are
2, flip-flop circuits FF11-FF in the order of C1
Out of 32, the number corresponding to the position and the number of data to be output is entered.

Then, the data held in the RS flip-flop RS / FF is taken into the flip-flop D-FF2 at the subsequent stage of the scan F / F section by the scan clock C2 and output to the scan-out terminal. The scan-out data SOD is taken into the flip-flop D-FF1 at the preceding stage of the scan F / F unit of the next-stage flip-flop by the scan clock C1, and the RS flip-flop RS / FF is set or set according to the latch data. Reset. By repeating the above operation, the flip-flop D-
The FF1 and the subsequent flip-flop D-FF2 perform the same operation as the master-slave configuration flip-flop, and the scan-out data is successively transmitted to the next-stage flip-flop and recovered by the test result recovery unit TSC. You. The operation of the relay flip-flop FFd is as follows.
The description is omitted because it is the same as that of a normal master-slave configuration flip-flop.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the above-described embodiment, flip-flop circuits (FF11 to FF3) capable of configuring a shift register for normal logic and scan are used.
As 2), a description has been given of an RS flip-flop and two level-triggered flip-flops. However, as long as the flip-flop has the same function and terminal, three flip-flops are clearly used as in the embodiment. It is also possible to use a circuit in which the functions of the three flip-flops according to the embodiment are not completely divided but are integrally formed. Further, the test data can be given from an external tester.

In the above description, the invention made by the present inventor is mainly applied to a gate array which is a field of application as a background, but the present invention is not limited to this. Of course, the present invention can be used for an LSI in which a digital circuit and an analog circuit are mixed.

[0043]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the time required for diagnosis of a logic integrated circuit having a built-in shift scan type diagnosis circuit can be shortened, and the productivity can be improved without lowering the defect detection rate.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of the configuration of an entire chip showing one embodiment of an internal logic unit of a logic LSI having a diagnostic function according to the present invention and a diagnostic function part therearound.

FIG. 2 is an explanatory view showing the gist of the present invention.

FIG. 3 is a flowchart showing a part related to the design of a diagnostic circuit in a design procedure of a logic integrated circuit to which the present invention is applied;

FIG. 4 is a logical configuration diagram showing a configuration example of a flip-flop circuit capable of configuring a normal logic and scan shift register used in the diagnostic circuit of the present invention, and a relay flip-flop circuit capable of configuring a scan shift register; is there.

FIG. 5A is a circuit diagram of a set / reset signal forming circuit SRG of a scan F / F section of flip-flop circuits FF11 to FF32 which can configure a scan shift register, and FIG. 5B is a relay flip-flop FFd; 1 is a circuit diagram of a first level trigger flip-flop D-FF1.

FIG. 6A is a timing chart showing data and clock timings at the time of scan-in of test data of a flip-flop circuit capable of forming a normal logic and scan shift register used in the diagnostic circuit of the present invention;
(B) is a timing chart showing the timing of data and clock at the time of scan-out of data of a flip-flop circuit which can constitute a normal logic and scan shift register used in the diagnostic circuit of the present invention.

FIG. 7 is an explanatory diagram showing a problem in a conventional scan shift type diagnostic circuit.

[Explanation of symbols]

FF11 to FF32 Flip-flop circuit capable of forming a shift register for normal logic and scan FFd Relay flip-flop circuit LG1, LG2 General logic section SDOUT Scan data output terminal PGR Pseudo random number generation circuit

Continued on the front page F term (reference) 2G032 AA01 AA09 AB01 AC10 AD05 AD06 AG02 AG03 AK01 AK16 5F038 CA17 CD09 DF16 DT02 DT04 DT05 DT06 DT07 DT14 DT18 EZ09 EZ20

Claims (5)

[Claims] 1. A flip-flop circuit capable of forming a shift register for normal logic and scan, and a flip-flop circuit for relay capable of forming a shift register for scan, wherein the shift register for normal logic and scan can be formed. A logic integrated circuit with a diagnostic function, wherein the relay flip-flop circuit is inserted in a portion where the distance between the flip-flop circuits is long. 2. The flip-flop circuit capable of forming the normal logic and scan shift register comprises a normal logic flip-flop circuit and a scan flip-flop circuit, wherein the scan flip-flop circuit and the relay flip-flop circuit are provided. 2. The logic integrated circuit with a diagnosis function according to claim 1, wherein the logic integrated circuit has a circuit configuration similar to that of the circuit. 3. The relay flip-flop circuit according to claim 1, wherein
3. The logic integrated circuit with a diagnosis function according to claim 2, wherein the level-triggered flip-flops are cascade-connected flip-flop circuits having a master / slave configuration. 4. A logic integrated circuit with a diagnostic function according to claim 1, further comprising a pseudo-random number generating circuit for randomly generating test data shifted by said scan shift register. . 5. When designing a logic integrated circuit incorporating a shift scan type diagnostic circuit, when a flip-flop circuit constituting a logic circuit is connected to form a scan shift register, the logic circuit is separated by a predetermined distance or more. If a flip-flop circuit exists, a relay flip-flop circuit is arranged between the flip-flop circuits, and the flip-flop circuits are connected via the relay flip-flop circuit. Design method of logic integrated circuit with diagnostic function.