JP2000082938A - Matched filter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress power consumption by bit-shifting the outputs of bit adders in accordance with the weights of respective bits in an exclusive OR circuit output. SOLUTION: An adder circuit ADD has bit adders BAD0-BADk to which the respective corresponding bits of the outputs b10-b1k and b20-b2k...bn0-bnk of an exclusive OR circuit are inputted. The outputs of the bit adders are inputted to corresponding shifters BSF0-BSFk. The bit adders BAD0-BADk add the bit sum of the corresponding bits as digital data, and BAD0 bit-adds n-bits of b10, b20...bn0, for example. The shifters BSF0-BSFk respectively shift the outputs of the bit adders by 0 bit, 1 bit, ...k bits in accordance with the weight of the bit inputted to the bit adder. The outputs of the respective shifters BSF0- BSFk are inputted to a final digital adder FAD and are digitally added.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a matched filter circuit, and more particularly to a matched filter circuit suitable for spread spectrum communication.

[0002]

2. Description of the Related Art In frequency spread communication, a high-speed correlation operation is required because data is spread by a predetermined spreading code, and this is despread and demodulated. Generally, a SAW filter, a sliding correlator, or a matched filter is used for this correlation operation, but the matched filter is superior in the speed of initial synchronization acquisition. However, the matched filter has a large circuit scale and large power consumption, so that it has been difficult to apply it to a portable terminal.

[0003]

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and has as its object to provide a matched filter circuit capable of suppressing power consumption.

[0004]

A matched filter circuit according to the present invention converts an input signal into an analog voltage signal, converts the analog signal into a digital voltage signal by an A / D converter, and sequentially holds the digital voltage signal by a register. Then, a plurality of 1-bit coefficients corresponding to these registers are held in a shift register, an exclusive OR of the digital voltage signal and the coefficient is calculated by an exclusive OR circuit, and an output of the exclusive OR circuit is calculated. Is digitally added by a bit adder for each bit, the result of the bit addition is bit-shifted according to the bit weight, and the bit-shifted result is digitally added.

[0005]

Next, a first embodiment of a matched filter circuit according to the present invention will be described with reference to the drawings.

[0006]

1, a received signal is input to a matched filter circuit in the form of an analog voltage signal Ain.
The signal is converted into a digital voltage signal in a D converter (indicated by A / D). This digital voltage signal is input in parallel to two register series R11 to R1n and R21 to R2n. The first series R11 to R1n take in the signal alternatively by the clock CLK0, and the second series R21 to R2n are the clocks CLK1 to R2. To take in the signal alternatively. The clocks CLK0 and CLK1 are clocks of the same frequency shifted by a half cycle from each other, and perform so-called double sampling. First and second series of corresponding registers, R
11 and R21, R12 and R22,. . . , R1ntoR
The output of 2n is input to the selectors SEL1 to SELn,
These selectors selectively output the outputs of one of the series of registers.

The outputs of the selectors SEL1 to SELn are input to exclusive OR circuits XOR1 to XORn, respectively.
A 1-bit spreading code (the entire spreading code sequence is indicated by PN) is input to these exclusive OR circuits. When the spreading code is "1", the selector output is output from the exclusive OR circuit as it is, and when the spreading code is "0", the bit inversion thereof is output. The spreading code sequence is a shift register S
REG, and the last stage is fed back to the first stage. The clock CLK0 or C
The same clock CLKS as that of LK1 is input, and the spread code sequence is cyclically shifted in synchronization with the loading of data into the register. CLK0 and CLK1 are R11 to R1n and R21.
.. R2n are cyclically fetched, and the fetched data and the spread code sequence correspond to each other. When a new spreading code is taken into the shift register, CLKS is input while supplying data to the data input terminal Din of the first stage.

The outputs of the exclusive OR circuits XOR1 to XORn are added by an adder ADD, and the correlation output Out is obtained.
Is generated.

FIG. 2 shows an adder circuit ADD. Adder circuit A
DD is the outputs b10 to b1k, b2 of the exclusive OR circuit.
0 to b2k,. . . , Bn0 to bnk, and bit adders BAD0 to BADk to which the corresponding bits are input. The outputs of these bit adders are corresponding shifters BSF0 to BSF0 to
SFk. Bit adders BAD0-BA
Dk adds the bit sum of the corresponding bits as digital data, and for example, BAD0 adds b10, b20,. . . , B
Bit addition of n bits of n0 is performed. Shifter BSF0
BSFk is the weight of the bit input to the bit adder, for example, the weight of b10 to bn0 “2 <SUP> 0 </ SUP>
> ”, Weight of b11-bn1“ 2 <SUP> 1 </ SUP ”
> ”,. . . , Weight of b1k to bnk "2 <SUP> k </ SUP
>, The bit adder output is set to 0 bit, 1 bit,. . . , K bits, respectively. The output of each shifter BSF0 to BSFk is the final digital adder FAD
And is digitally added.

Here, the bit adders BAD0-BAD
k can be configured by a digital parallel counter that counts the number of “1” in the corresponding bit in parallel. Further, instead of the digital parallel counter, “Parallel using a neuro MOS transistor” by Tomozu Nakagawa et al. Design of Counter Type Multiplier ", IEICE Tech.
3, VLD94-119, ICD94-227 (199
The circuit introduced in 5-03) can also be employed.

FIG. 3 shows a threshold type bit adder. This threshold type bit adder can be used as the adder BAD0. The threshold type bit adder has the number of input bits (k + 1)
, And each one threshold-type bit adder has m threshold circuits TH1 to THm represented by Expression (1).

(Equation 1) BAD0 calculates the sum of the input least significant bits and outputs the result as m-bit digital data. Threshold circuit T
Hm outputs the most significant bit (MSB) Bm of the digital data, and THm-1 is the second bit Bm-1,. . . , T
H1 outputs the least significant bit (LSB) B1. The input of each of the threshold circuits TH1 to THm is connected to a capacitive coupling formed by connecting a plurality of capacitances in parallel, and through these capacitive couplings, each threshold circuit is connected to the maximum of the outputs of all exclusive OR circuits. Lower bits (LSB) b10 to bn0 are input. Furthermore, the threshold circuit TH1 for the second bit or less
ＴTHm−1 is input with an inverted output of a threshold circuit of a higher-order bit via the capacitive coupling. Where B1
Bm to Bm are input to the threshold circuit THm-1, and b10 to bn0, B'm, and B 'are input to the threshold circuit THm-2.
m-1 is input, and. . . , TH1 have b10 to bn0
And B'm to B'2 are input.

Each of the threshold circuits TH1 to THm is provided with an inverter or a comparator I11 to Im1 corresponding to each output bit B1 to Bm, respectively, and the capacitive coupling is connected to the inputs of these inverters. Inverters I12 to Im2 are respectively connected to outputs of the inverters I11 to Im1, and outputs B1 to Bm are output from I12 to Im2.
Is output. The inverted outputs B′1 to B′m are I11 to I11.
Each is output from Im1.

Here, taking the threshold circuit TH1 as an example, the capacitances C01 to C0n connected to b1, 0 to bn0 in the capacitive coupling have the same capacitance.
The capacity is set to a threshold value of 1. B'2
Capacitances CB12 to CB1m connected to B'm
Is a capacity corresponding to the threshold value of the threshold circuits TH2 to THm. All of the above inverters (I11 to Im1
If the threshold value _{V T} etc.) is fixed to VDD / 2, the relative relationship between the capacitance at the threshold circuit TH1~THm becomes as illustrated in formula (2).

(Equation 2) Therefore, if the binarization process is represented by a Gaussian symbol [],
The output of each of the threshold circuits TH1 to THm is expressed as in equation (3). That outputs "1" if and equal if exceeds the threshold value V _T of the inverter, performs a process of outputting the otherwise "0". Note that other bit adders B
AD1 to BADk are configured in the same manner, and the description is omitted.

(Equation 3)

FIG. 4 shows a modification of the threshold type bit adder.
However, BAD0 is representatively shown as in FIG. Of this modification
The threshold type bit adder outputs the outputs b1, 0 of the exclusive OR circuit.
~ Bn0 is not directly input to the capacitive coupling, and each bit is temporarily
SEL41 to SEL4n, and
The collector output is used as the input for capacitive coupling. Selector SE
As shown by L4n, each selector has a reference high voltage.
Pressure V_HAnd reference low voltage V _LIs input and the bit value is
According to V_HOr V_LIs output. Like this
By converting the reference voltage without directly inputting the
The operation accuracy of the bit adder can be improved. Figure 3 and
Similarly, the outputs of the selectors SEL41 to SEL4n
A plurality of capacitances Cm1 to Cm corresponding to the selector
mn. Also, the upper bits
The inverted signal of the output of the module is directly connected to the capacitive coupling of the lower bit.
Without using the same selector (SELBm-1, m,...,
SELB1m, SELB1, m-1,..., SELB1,
Connect through 1).

Further, the selectors SEL4m1 to SEL4mn can output a reference voltage Vref corresponding to the threshold voltage of the inverting amplifier circuit.
By inputting ref to all capacitances of the capacitive coupling, the capacitive coupling can be refreshed. The refresh eliminates the residual charge of the capacitance, and improves the calculation accuracy.

FIG. 5 shows a second modification of the threshold type bit adder.
Is shown. In this modification, two exclusive OR circuits are provided.
, One selector is provided for each output bit, and p = n /
There are two selectors SEL51 to SEL5p. This
Here, taking the selector SEL51 as an example, the input bit b1
The sum of 0 and b20 is used as ternary data, and
SEL 51 is controlled. Selector SEL
51 has a reference high voltage V _H, Reference intermediate voltage V_ref, Standards
Low voltage V_LIs input and b10 = b20 = 1
V_H, When one of them is 1 and the other is 0,
V_ref, When b10 = b20 = 0, the reference low voltage V_LTo
Output. Input ternary input for capacitive coupling in this way
By doing so, the number of inputs for capacitive coupling is reduced by half.
You.

FIG. 6 shows a second embodiment of the present invention, in which an analog type adder is used in place of the digital type adder of FIG. The adder ADD outputs the outputs b10 to b1k, b20 to b2k,. . . , Bn
It has analog bit adders ABAD0 to ABADk to which corresponding bits 0 to bnk are input, and performs analog addition in these bit adders. Outputs BS0 to BSk of the bit adder are input to a weighted analog adder circuit AFAD, and are analog-added.

FIG. 7 representatively shows the bit adder ABAD0 of FIG. The bit adder ABAD0 outputs each bit b10
Bn, 0 are connected to the selectors SEL71 to SEL71, respectively.
SEL7n, and these selectors output the reference high voltage _VH or the reference low voltage _VL according to the value of each bit.
As described above, by performing the reference voltage conversion without directly inputting the digital data, the calculation accuracy of the bit adder can be improved. The outputs of the selectors SEL71 to SEL7n are
A plurality of capacitances C71 corresponding to these selectors
To C7n. The output of this capacitive coupling is an inverting amplifier circuit I composed of a MOS inverter.
7 and the output of the inverting amplifier is connected to its input by a feedback capacitance Cf7. The capacitances C71 to C7n are equal in capacitance, and the capacitance of the capacitance Cf7 is equal to the sum of the capacitances of C71 to C7n.
As a result, the output BS0 of the bit adder ABAD0 becomes the bit sum of the equation (4). In equation (4), Vb indicates a threshold voltage of the inverting amplifier circuit.

(Equation 4) The bit adders ABAD1 to ABADk in FIG.
Since the configuration is the same as that of AD0, the description is omitted.

Further, the selectors SEL71 to 7n can output a reference voltage Vref corresponding to the threshold voltage of the inverting amplifier circuit.
By inputting f to I7, C71 to C7n, C7
5 can be refreshed. The refresh eliminates the residual charge of the capacitance, thereby improving the calculation accuracy.

FIG. 8 shows the final adder AFAD of FIG.
The final adder AFAD outputs the outputs BS0 to B of each bit adder.
It has a capacitive coupling composed of a plurality of capacitances C80 to C8k corresponding to Sk. The output of this capacitive coupling is MOS
The output of the inverting amplifier circuit is connected to an input of the inverting amplifier circuit by a feedback capacitance CfF. Capacitance C80-C8
k is a capacitance corresponding to the weight of the bits BS0 to BSk, and the capacitance of the capacitance CfF is equal to the sum of the capacitances of C80 to C8k. As a result, the output Out of the final adder AFAD becomes the weighted addition result of Expression (5).

(Equation 5) If weighted addition is performed after analog addition for each bit as described above, the overall capacitance capacity can be reduced, and the circuit scale can be reduced.

FIG. 9 shows a modification of the bit adder ABAD0 of FIG.
An example is shown, and two exclusive OR circuits are
A plurality of separated selectors SEL91 to SEL9p.
Have been. Here, taking the selector SEL91 as an example,
The sum of the input bits b10 and b20 is defined as ternary data.
The selector SEL91 is controlled accordingly.
The selector SEL91 has the reference high voltage V_H, Reference intermediate voltage
V_ref, Reference low voltage V _LIs input, and b10 = b20
= 1 when V_H, When either one is 1 and the other is 0
Quasi-intermediate voltage V_ref, Reference low when b10 = b20 = 0
Voltage V_LIs output.

FIG. 10 shows an example of a logic circuit for realizing such a logic. b01 and b02 are AND gates _GH and N
The _signals are input to the OR gate G _L and the XOR gate G _ref , and the switches SWH, SWL, SW
REF is controlled to open and close. These switches SWH,
The voltages _VH , _VL and _Vref are applied to SWL and SWREF.
Are respectively input, and the ternary output is realized. This reduces the number of input signals of the bit adder by half.

FIGS. 11 to 13 show a third embodiment. The adder circuit ADD has the same configuration as that of FIG. However, the bit adder and the final adder in the adder circuit have resistance as a basic element as described below. FIG. 11 representatively shows a bit adder ABAD0 as in FIG. The bit adder ABAD0 outputs each bit b1
Selector SEL1 to which 0 to bn, 0 are respectively connected
1, 1 to SEL11n, and these selectors output the reference high voltage _VH or the reference low voltage _VL according to the value of each bit. The outputs of the selectors SEL11, SEL11-SEL11n are connected to a plurality of resistances R corresponding to these selectors.
11, 11 to C11n. The output of this resistance coupling is connected to an inverting amplifier circuit I11 composed of a MOS inverter, and the output of the inverting amplifier circuit is connected to its input by a feedback capacitance Rf11. Resistance R11,1 to R1
1n is an equal resistance value, and the reciprocal of the resistance value of the resistance Rf11 is equal to the sum of the reciprocals of R11, 1 to R11n.
Thereby, the output BS0 of the bit adder ABAD0 becomes the bit sum of the equation (6).

(Equation 6) The other bit adders ABAD1 to ABADk are ABA
Since the configuration is the same as that of D0, the description is omitted.

FIG. 12 shows the final adder AFAD. The final adder AFAD is the output BS0 to BSk of each bit adder.
Has a resistance connection composed of a plurality of resistances R120 to C12k. The output of this resistance connection is an inverting amplifier circuit I12 comprising a MOS inverter.
And the output of the inverting amplifier circuit is a feedback resistance R
Connected to its input by fF. The resistances R120 to R12k have resistance values proportional to the reciprocals of the weights of the bits BS0 to BSk, and the resistance value of the resistance RfF is equal to the sum of the reciprocals of the resistance values of R120 to R12k. Thus, the output Out of the final adder AFAD becomes the weighted addition result of Expression (7).

(Equation 7)

FIG. 13 shows the bit adder ABAD0 of FIG.
9 and 2 corresponding to adjacent bits as in FIG.
A plurality of selectors SEL131 to SEL13p provided corresponding to each exclusive OR circuit are provided. Here, taking the selector SEL131 as an example, the selector SEL131 is controlled in accordance with the sum of the input bits b10 and b20 as ternary data. The selector SEL131 has a reference high voltage _VH and a reference intermediate voltage VH.
_ref , the reference low voltage _VL is input, and b10 = b20 =
When _H is 1, V _H is output, when one is 1 and the other is 0, the reference intermediate voltage V _ref is output, and when b 10 = b 20 = 0, the reference low voltage V _L is output.

It is also possible to combine a capacitance type bit adder (FIGS. 3 to 5, 7, and 9) with a resistance type final adder (FIG. 12). Of course, it is also possible to combine (FIGS. 11 and 13) with a capacitance type final adder (FIG. 8).

[0027]

As described above, the matched filter circuit according to the present invention converts an input signal into an analog voltage signal, converts the analog signal into a digital voltage signal by an A / D converter, and sequentially holds the digital voltage signal by a register. Then, a plurality of 1-bit coefficients corresponding to these registers are held in a shift register, an exclusive OR of the digital voltage signal and the coefficient is calculated by an exclusive OR circuit, and an output of the exclusive OR circuit is calculated. Is digitally added by a bit adder for each bit, and the result of the bit addition is bit-shifted according to the bit weight, and the bit-shifted result is digitally added, so that power consumption can be reduced. Has excellent effects.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a matched filter circuit according to the present invention.

FIG. 2 is a circuit diagram showing an adding circuit of the embodiment.

FIG. 3 is a circuit diagram showing a bit adder of the embodiment.

FIG. 4 is a circuit diagram showing a modification of the bit adder.

FIG. 5 is a circuit diagram showing a second modification of the bit adder.

FIG. 6 is a circuit diagram illustrating an addition circuit according to a second embodiment.

FIG. 7 is a circuit diagram illustrating a bit adder according to a second embodiment.

FIG. 8 is a circuit diagram showing a final adder according to a second embodiment.

FIG. 9 is a circuit diagram showing a modification of the bit adder of the second embodiment.

FIG. 10 is a circuit diagram illustrating a logic circuit for the bit adder of FIG. 7;

FIG. 11 is a circuit diagram illustrating a bit adder according to a third embodiment.

FIG. 12 is a circuit diagram illustrating a final adder according to a third embodiment.

FIG. 13 is a circuit diagram showing a modification of the bit adder of the third embodiment.

[Explanation of symbols]

A / D. . . A / D converters R11 to R1n, R21 to R2n. . . Registers SEL1 to SELn. . . Selector XOR1 to XORn. . . Exclusive OR circuit ADD. . . Adder circuit SREG. . . Shift register BAD0-BADk. . . Bit addition circuit ABAD0-ABADk. . . Analog bit addition circuit BSF0 to BSFk. . . Shifter FAD. . . Final digital adder AFAD. . . Weighted analog addition circuits TH1 to THm. . . Threshold circuits I11 to Im1, I12 to Im2. . . Inverters C00-C0n, C10-C1n,. . . , Cm1-C
mn, C71-C7n, Cf7, C81-C8k, Cf
F, C51-C5p, C91-C9p, Cf9, CB0
1 to CB0m, CB12 to CB1m,. . . , CBm-
1, m. . . Capacitance R11,1 to R11n, Rf11, R121 to R12
k, RfF, R131 to R13p, Rf13. . . Resistance SEL41-SEL4n, SEL51-SEL5p, S
EL71 to SEL7n, SEL91 to SEL9p. . .
The selectors b10 to b1k, b20 to b2k,. . . , Bn0-b
nk. . . Exclusive OR circuit output B0 to Bm. . . Bit adder output.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Kunihiko Suzuki 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Takayamauchi Co., Ltd. F-term (reference) 5K022 EE02 EE33

Claims (12)

[Claims] An A / D converter for converting an analog voltage signal into a digital voltage signal; a plurality of registers for sequentially holding digital voltage signals output from the A / D converter; and a plurality of registers corresponding to these registers And a shift register for holding a 1-bit coefficient and performing a cyclic shift; and a plurality of exclusive OR circuits connected to the register,
An exclusive-OR circuit for calculating an exclusive-OR for each bit of the coefficient and the digital voltage signal; and a plurality of bit adders corresponding to each bit of the output of the exclusive-OR circuit, Each adder circuit is a bit adder for digitally adding the corresponding bit of the exclusive OR circuit; and a plurality of shifters provided corresponding to each bit adder. A matched filter circuit comprising: a shifter that bit-shifts the output of the bit adder according to the weight; and a final adder that digitally adds the outputs of the shifters. 2. The matched filter according to claim 1, wherein the bit adder comprises a parallel counter for counting the number of “1” in the output of the corresponding exclusive OR circuit in parallel. circuit. 3. An A / D converter for converting an analog voltage signal into a digital voltage signal; a plurality of registers for sequentially holding digital voltage signals output from the A / D converter; and a plurality of registers corresponding to the registers. And a shift register for holding a 1-bit coefficient and performing a cyclic shift; and a plurality of exclusive OR circuits connected to the register,
An exclusive-OR circuit for calculating an exclusive-OR of each bit of the coefficient and the digital voltage signal; and a plurality of threshold-type bit adders corresponding to the number of output bits of the exclusive-OR circuit. A threshold number corresponding to the weight of each bit of the binary number, and a threshold value corresponding to the weight of each bit of the binary number is set for each threshold value circuit. The inputs are connected to the capacitive couplings to which the corresponding bits of all the exclusive OR circuits and the inverted output of the higher-order threshold circuit are input.
A weight corresponding to the threshold value of the threshold circuit is given to the inverted output of the higher-order threshold circuit, and a capacitance corresponding to the weight corresponding to the threshold value of the threshold circuit is given to the exclusive OR circuit output. And a plurality of shifters provided corresponding to each of the threshold-type bit adders, wherein an output of the bit adder is output in accordance with the weight of each bit of the exclusive-OR circuit output. A matched filter circuit comprising: a shifter that performs a bit shift; and a final adder that digitally adds the outputs of the shifters. 4. A threshold bit adder comprising: a selector provided corresponding to each exclusive OR circuit, for outputting a reference high voltage or a reference low voltage according to an output of the exclusive OR circuit; 4. The matched filter circuit according to claim 3, wherein the outputs of the selectors are input to the capacitances of the corresponding threshold circuits. 5. Each threshold type bit adder is: a plurality of selectors provided corresponding to two exclusive OR circuits, each of which outputs the output of each of the two exclusive OR circuits to a ternary value. A selector for outputting, as data, a reference high voltage, a reference intermediate voltage or a reference low voltage corresponding to the ternary data; outputs of the selectors are input to the capacitances of the corresponding threshold circuits, respectively. The matched filter circuit according to claim 3. 6. An A / D converter for converting an analog voltage signal to a digital voltage signal; a plurality of registers for sequentially holding digital voltage signals output from the A / D converter; and a plurality of registers corresponding to the registers. And a shift register for holding a 1-bit coefficient and performing a cyclic shift; and a plurality of exclusive OR circuits connected to the register,
An exclusive-OR circuit for calculating an exclusive-OR for each bit of the coefficient and the digital voltage signal; and a plurality of bit adders corresponding to each bit of the output of the exclusive-OR circuit, A bit adder for analog-adding the corresponding bit of the exclusive-OR circuit; and a final adder for weighting the output of the bit-adder according to the weight of each bit of the exclusive-OR circuit output. A matched filter circuit comprising: an adder; 7. Each bit adder is provided corresponding to each exclusive OR circuit, and outputs a reference high voltage or a reference low voltage according to an output of the exclusive OR circuit; Capacitive coupling whose output is composed of an equal-capacitance capacitance respectively input; an inverting amplifier circuit to which the output of this capacitive coupling is input; and a feedback capacitance connecting the output of the inverting amplifier circuit to its input. The matched filter circuit according to claim 6, wherein: 8. The final adder is a capacitive coupling composed of a capacitance provided corresponding to each bit adder, and each capacitance has a capacity corresponding to the weight of each bit of the output of the exclusive OR circuit. An inverting amplifier circuit to which the output of the capacitive coupling is input; and a feedback capacitance connecting the output of the inverting amplifier circuit to its input;
7. The matched filter circuit according to claim 6, further comprising: 9. Each bit adder is: a plurality of selectors provided corresponding to two exclusive OR circuits, wherein outputs of each of the two exclusive OR circuits are ternary data. A selector for outputting a reference high voltage, a reference intermediate voltage, or a reference low voltage corresponding to the ternary data; a capacitive coupling composed of equal-capacitance capacitances to which the outputs of the selectors are input; and an output of the capacitive coupling. 7. The matched filter circuit according to claim 6, further comprising: an input inverting amplifier circuit; and a feedback capacitance connecting an output of the inverting amplifier circuit to the input. 10. A bit adder comprising: a selector provided corresponding to each exclusive OR circuit, for outputting a reference high voltage or a reference low voltage according to an output of the exclusive OR circuit;
A resistance coupling comprising resistances of equal resistance values to which outputs of the selectors are respectively inputted; an inverting amplifier circuit to which an output of the resistance coupling is inputted; and a feedback resistance for connecting an output of the inverting amplifier circuit to its input; 7. The matched filter circuit according to claim 6, further comprising: 11. The final adder is a resistance combination consisting of resistances provided corresponding to each bit adder, each resistance being a resistance value corresponding to the weight of each bit of an exclusive OR circuit output. 7. A matched circuit according to claim 6, further comprising: a resistance coupling having: an inverting amplifier to which an output of the resistance coupling is input; and a feedback resistance connecting an output of the inverting amplifier to its input. Filter circuit. 12. Each bit adder is: a plurality of selectors provided corresponding to two exclusive OR circuits, wherein outputs of each of the two exclusive OR circuits are ternary data. A selector for outputting a reference high voltage, a reference intermediate voltage, or a reference low voltage corresponding to the ternary data; a resistance combination formed by resistances of equal resistance values to which the outputs of the selectors are input; and an output of the resistance combination 7. The matched filter circuit according to claim 6, further comprising: an inverting amplifier circuit to which is input; and a feedback resistance connecting an output of the inverting amplifier circuit to an input of the inverting amplifier circuit.