JP2000078890A - Device and method for controlling drive - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable simple drive control by reducing the load of a CPU, when control data of a motor increase. SOLUTION: A motor driving current is freely set in one step, by installing a DMA control circuit 26 which reads control data 30 from a RAM 5 with a DMA, and a rotating speed setting register of motors 6-8, and using a DMA demand flag for determining whether DMA is generated or not.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive control device and a drive control method for driving and controlling a motor, and more particularly to a drive control device and a drive control device for performing recording on a recording medium by operating a recording head by the motor. It relates to a drive control method.

[0002]

2. Description of the Related Art Conventionally, a recording apparatus having functions such as a printer, a copying machine, and a facsimile, or a recording apparatus used as an output device of a multifunction machine or a workstation including a computer or a word processor, etc., is based on paper based on image information. Generally, it is configured to record an image (including characters and symbols) on a recording material such as a sheet or a plastic thin plate (OHP sheet).

[0003] In a serial type recording apparatus that employs a method of recording in the main scanning direction along a direction intersecting with the recording material conveyance direction (sub-scanning direction), a carriage that moves along the recording material (main scanning direction). An image (including characters and symbols) is recorded by a recording means (recording head) mounted thereon, and after a recording of one line is completed, a predetermined amount of paper feed (sub-scan) is performed, and then a next line is recorded. Record an image (sub-scan)
By repeating this operation, an image is recorded in a desired range of the recording material.

As a motor used in such a recording apparatus, a line field motor, a carriage motor, a paper feeding motor, and a recovery motor for a recording head are currently generally a DC motor or a stepping motor controlled by a pulse. .

Here, a stepping motor will be described.

[0006] Due to the nature of the stepping motor, positioning control can be performed in an open loop without a feedback system. The fact that positioning control can be performed in an open loop in this way leads to simplification of the system and is extremely advantageous in terms of cost. For this reason, stepping motors are widely used in OA equipment-related control systems.

As a motor driving method, there are a constant current driving method, a constant voltage PWM driving method, a micro step driving method and the like.

[0008] The constant current drive system is a drive system for controlling the current flowing through the stepping motor to be always constant. Among them, the chopper drive system has a lighter load on the power transistor and is more efficient than the analog drive system. Since it is a driving method, it is used relatively frequently.

Conventionally, the PWM driving method changes the time width of a voltage applied to a transistor of a motor driver to create an arbitrary current waveform. Actually, a desired current waveform is obtained by dividing one phase into a plurality of parts and setting whether or not to apply a voltage for each division. Generally, when the current waveform is closer to the sin curve, smooth driving can be obtained with less vibration.

In the micro-step driving method, the basic step angle is further refined by circuit technology, and it is possible to realize the step driving of a minute angle. Therefore, there is also an effect of reducing the vibration of the rotor. In principle, the stationary point of the rotor is determined by supplying an arbitrary drive current to each of the two excitation coils. If the exciting current is increased as a property of the magnetic circuit, the generated magnetic field becomes correspondingly strong, and the stationary point of the rotor can be set arbitrarily.

Next, an example of a conventional drive control using the above-described drive method will be described.

FIG. 9 shows an example of conventional motor drive control. Reference numeral 2 denotes a CPU, and reference numeral 3 denotes a ROM in which a motor control table is stored. Reference numeral 14 denotes a motor driver that drives a motor.

The motor driver 14 uses a motor driver having four-phase input constant current chopping and a 2-bit current value switching function.

As a motor control signal from the CPU 2, IN
A, INA *, INB, INB * phase selection signals and I
0, I1 current value switching signal and the motor driver 14
Is output to The direction of the current flowing through the coil can be set by the control signals INA and INB, and the value of the current flowing through the motor can be set by the signals I0 and I1.

In this configuration, the rotational speed of the motor, that is, the moving speed of the carriage is determined by the CPU 2 and
This is realized by changing the pulse length of NA, INA *, INB, INB *. The pulse length is determined as a timer function of the CPU 2. In a printing apparatus that performs printing by operating the carriage mainly, the position of the carriage and the image data must always be linked, and the absolute value (absolute position) of the carriage is determined by how many steps the CPU 2 drives. The absolute value of the carriage is managed by storing it in an internal register. For the absolute value, the absolute value 0 is determined at the home position. The home position is a positioning shielding plate physically provided in the movement range of the carriage, and is configured to be detected by an optical sensor provided on the carriage.

[0016]

In the motor driver 14 according to the conventional drive control, the current value can be controlled in two bits. That is, four-stage switching is possible. In recent years, motor drivers that can further subdivide the current value setting and have various drive modes have been commercialized.

However, the control method of the motor driver 14 having such various settings complicates the configuration of the control section and the processing thereof, and increases the control data.

It is an object of the present invention to provide a drive control device and a drive control method capable of reducing the load on the CPU and performing simple drive control even when the control data of the motor increases. It is in.

[0019]

SUMMARY OF THE INVENTION The present invention relates to an apparatus for controlling the driving of a motor, comprising storage means for storing motor control data for controlling the driving of the motor, and means for driving the motor one step. Read means for reading the motor control data from the storage means by at least one read processing, wherein the motor control data read out by the read means by one read processing includes motor drive current value information. And the drive control device is configured by changing the motor drive current for each single read process.

The present invention also relates to an apparatus for controlling the drive of a motor, comprising: storage means for storing motor control data for controlling the drive of the motor; and at least one unit for driving the motor by one step. Reading means for reading out the motor control data from the storage means by at least one DMA process, wherein the motor control data read out by one DMA process of the reading means includes motor drive current value information, A drive control device is configured by changing the motor drive current for each DMA process.

Further, the present invention constitutes a printing apparatus by including the drive control device and a print head driven by a motor of the drive control device.

The present invention also relates to a method for controlling the driving of a motor, comprising a step of reading motor control data from a storage means by at least one or more reading processes in order to drive the motor one step. A drive control method is provided by including motor drive current value information in the motor control data read by one read process and changing the motor drive current for each one read process.

The present invention also relates to a method for controlling the driving of a motor, comprising a step of reading motor control data from a storage means by at least one DMA process in order to drive the motor one step. One D
The present invention provides a drive control method by including motor drive current value information in the motor control data read out by the MA process and changing the motor drive current for each DMA process.

Further, the present invention is a medium in which a program for controlling the drive of a motor by a computer is recorded, and the control program causes the computer to execute at least one or more operations to drive the motor one step. The motor control data is read from the storage means by the read processing, and the motor control data read by one read processing includes motor drive current value information,
A recording medium in which a motor drive control program is recorded is provided by changing a drive current of a motor for each reading process.

Further, the present invention is a medium in which a program for controlling the drive of a motor by a computer is recorded. The control program causes the computer to execute at least one or more operations to drive the motor one step. The motor control data is read from the storage means by the DMA process, and the motor control data read out by the one DMA process contains the motor drive current value information, and the motor drive current changes every one DMA process. Accordingly, a recording medium on which the motor drive control program is recorded is provided.

Here, one step is constituted by a range unit obtained by dividing the inside of the one step at equal time intervals, and the reading means reads the motor control data of the one step from the storage means by DMA. , It is possible to determine whether or not to DMA the motor control data on a range-by-range basis.

The above determination can be made using a DMA request flag register.

According to the value of the DMA request flag register, if the value of the flag corresponding to the predetermined range is set to perform DMA, the address pointer is counted up after the DMA is completed. , The address pointer can be counted up.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Outline) First, an outline of the present invention will be described.

In order to cope with an increase in the control data of the motor, the control data is reduced by R to reduce the load on the CPU.
One solution is to expand to AM and read control data from RAM by DMA. Storing the control data of the motor in a RAM or the like in this manner has conventionally been difficult.
Not much done.

In view of the above, the present invention proposes a circuit configuration having control data in storage means such as a RAM and having the most flexibility.

That is, the present invention provides a CPU, a ROM and a RAM in which a motor control table is stored, a motor driver for motor control, a DMA control circuit for reading control data from the RAM by DMA, and a rotational speed of the motor. A circuit configuration that includes a setting register and an absolute value counter circuit synchronized with the motor and that can set the motor drive current in detail and freely by using a DMA request flag that determines whether DMA is generated or not. Is what you do.

(Specific Example) Hereinafter, a specific example will be described.

(System Configuration) First, a configuration example of a system according to the present invention will be described.

FIG. 1 shows the configuration of a recording apparatus applicable to the present invention.

Reference numeral 1 denotes a recording device.

Reference numeral 2 denotes a CPU that plays a central role in controlling the recording apparatus 1.

3 is a control program according to the present invention,
U2 is a ROM in which motor control data 30 of each of the motors 6 to 8, CG, and the like are stored.

Reference numeral 4 denotes a gate array (GA).
The features that cannot be fulfilled by the function of U2 are supplemented in the form of custom devices by logic design.

5 is a RAM. The RAM 5 stores motor control data 30 of the motors 6 to 8,
Data transferred from the host device 100 (print data,
This is used for a reception buffer for storing control codes and symbols, a print buffer for reading data from the reception buffer and storing the data expanded into bit data, a control register used in the gate array 4, and the like.

A carriage motor (CR motor) 6 moves the recording head 10 in the main scanning direction along the recording material.
It is.

Reference numeral 7 denotes a line feed motor (LF motor) for feeding paper in the recording material conveyance direction (sub-scanning direction).

Reference numeral 8 denotes a motor (ASF motor) used for sucking ink from the discharge nozzles of the recording head 10 and for feeding and discharging the paper in order to maintain the print quality of the recording head 10.

Reference numeral 9 denotes a motor driver (corresponding to motor drivers 15 and 16 in FIG. 2 described later) necessary for driving each of the motors 6 to 8 and a motor drive circuit as a peripheral circuit thereof.

Reference numeral 10 denotes a recording head including an ink jet head mounted on a carriage and performing recording by discharging ink along a recording material.

Reference numeral 11 denotes a head control circuit. The head control circuit 11 is configured to appropriately print the print head 10 by detecting a type of the print head 10, a variation in resistance for heating a heater in each ejection nozzle, a temperature, and the like. .

12 is a case where the user sets the power ON and the power O
This is an operation panel for actually operating FF, ONLINE, line feed (LF), and menu (setting of paper feeding method, used I / F, used cartridge, other functions, etc.).

Reference numeral 13 denotes a panel control circuit for controlling the operation panel 12.

Reference numeral 26 denotes motor control data 3 from the RAM 5
This is a DMA control circuit that DMA-reads 0.

A host device 100 is connected to the recording device 1 via an interface (I / F).

FIG. 2 shows a main configuration of the present system.

This system is mainly composed of ROM 3, CPU
2, a RAM 5, a gate array 4, a carriage (CR) motor driver 15, a line feed (LF) motor driver 16, a home position (HP) sensor 17, and a paper presence / absence (PE) sensor 18.

The CPU 2 reads out the motor control data stored in the ROM 3 in advance and stores it in the RAM 5. R
The read and write operations of the AM 5 are performed via the gate array 4.

Upon receiving a start trigger from the CPU 2, the gate array 4 reads data from the RAM 5 by DMA and transfers the data to the motor drivers 15 and 16,
Drive the motor. Read data from the RAM 5 is performed in units of bytes or words, and data processing is performed based on the data in accordance with the input / output interface of the motor drivers 15 and 16. In particular, when serially transferring data to the motor driver 15, it is necessary to convert the data in the RAM 5 into parallel data.

The outputs of the home position sensor 17 and the paper presence / absence sensor 18 are input to the gate array 4. As will be described later, this is performed by hardware in order to detect the value of the absolute value counter when the output of the sensor changes in more detail.

(DMA Control Circuit / Absolute Value Counter) Next, the configurations of the DMA control circuit and the absolute value counter will be described with reference to FIGS.

FIG. 3 shows the configuration of the DMA control circuit.

A DMA 25 latches data from the CPU 2 at a predetermined address WRITE in the gate array area.
Request flag register.

This DMA request flag register 25 stores 1
It consists of 6 bits and corresponds to 0 to 15 ranges of each range from 0 to 15 bits. 0
When the bit is “Hi”, the motor drive data for the 0 range is read by DMA, and the 0th bit is “Lo”.
In the case of w ", the control data for the 0 range is not read by the DMA.

Similarly, from 1 range to 15 range, D
According to the value of the MA request flag register 25, the occurrence or non-occurrence of DMA is determined.

Reference numeral 22 denotes a range counter, which is a 4-bit counter. The range counter 22 counts the time obtained by dividing one step by 16 into the pulse width counter 21 (FIG. 3).
), And counts up in synchronization with CO (carry) of the pulse width counter 21.

The signal st input to the DMA control circuit 26
art adr is the DMA from which address in the RAM 5
Is an output signal from a register for setting whether to start. The number of addresses is 22 bits.

Signal stop adr is an output signal from a register for setting up to which address of the RAM the DMA is to be performed. Similarly, the number of addresses is 22 bits.

The signal control is composed of a start trigger and a stop trigger.
1 is controlled.

The signal dma ack is a signal for notifying the latch timing of data output from the RAM 5 by reading the DMA.

The DMA control circuit 26 has these input signals, and comprises an address pointer 27 and a DMA request generation circuit 28. Note that a signal ram indicating a RAM address to be read by DMA is used. adr
And the DMA request signal dma rq as an output signal.

FIG. 4 shows the structure of the absolute value counter.

In synchronization with the counter output of the absolute value counter, the DMA from the RAM 5 and the motor drivers 15, 1
Transfer to 6 is performed.

21 is an enable control circuit 19
This is a pulse width counter that counts up when the enable signal from is high.

The pulse width counter 21 outputs a carry (CO) when the output value of the pulse width counter 21 matches the output of the pulse width setting register 20. The width of one range is set in the pulse width setting register 20 by the CPU 2.

A range counter 22 counts up when the carry of the pulse width counter 21 is Hi. The output of this range counter 22 is counted from 0 to 16
When it becomes, the carry is output.

Reference numeral 23 denotes a step counter that counts up and down when the carry output from the range counter 22 is Hi. This step counter 23
Can be read by the CPU 2. It also has an output value loading (LOAD) function.

The counting up and down of the number of steps is managed in hardware by the absolute value counter having the above-described configuration.

(System Operation) Next, the drive control of the motor will be described.

FIG. 5 shows the waveform of the drive current of the motor.

In this example, one step is defined as a range indicated by a double arrow. One range is defined as 1/16 step obtained by dividing one step into 16 steps.

The motor driver 15 used in this example,
Reference numeral 16 denotes a stepping motor driver of a constant current chopping method, which has a microstep driving function, and is capable of switching a current value to be chopped in 16 steps.

The input interface of the motor driver is configured for serial transfer, and includes STB, DAT
Control data is input by three signals A and CLK.

In FIG. 5, one word (WORD) is required to drive one range.
The data amount for driving one step is 16 words. One word of data includes motor drive setting data such as the direction of the current flowing through the A-phase and B-phase coils and the current value for chopping.

Since the DMA handles one word of data at a time, one-step (16 range) driving requires one word.
Six DMAs are required.

When the gate array 4 receives the start trigger from the CPU 2, it reads the motor control data stored in the RAM 5 by DMA, converts the data into parallel data, and converts the data into motor drivers 15, 16 (motor drive circuit 9). Is performed in one range. One step is formed by repeating the sequence 16 times.

FIGS. 6 and 7 show the operation timing of the DMA control circuit 26. FIG.

FIG. 6 shows the timing when the value of the DMA request flag register 25 is temporarily set to (HEX) 7777 in one step.

FIG. 7 is an enlarged view of the second to fourth ranges in FIG. The DMA request flag is “1” in the second and fourth ranges.

In this case, the DMA generation timing, that is, the signal dma The generation timing of rq is a switching point of the range. When the range changes, the signal dma rq is set to “Hi”, and a DMA request is made.

The address switching timing is the pulse signal dma in the case of the second range and the fourth range in which DMA is performed. ack as a trigger, and at the same time, the signal dma Drop rq to "Low". On the other hand, D
In the case of the third range in which MA is not performed, the address is counted up by using a switch of the range as a trigger. In this case, the signal dma rq does not occur.

Then, the second range and the fourth
In the case of the range, the RAM 5 read by the DMA
Is transferred to the motor drivers 15 and 16. In this case, address 10000 in the second range
Data transfer at address 6 is performed, and data transfer at address 10000a is performed in the fourth range. on the other hand,
In the case of the third range in which the DMA is not performed, the data transfer to the motor drivers 15 and 16 is not performed, and the output signals of the motor drivers 15 and 16 are held at the outputs corresponding to the previously transferred data. .

FIG. 8 shows an example of motor drive using the DMA request flag.

In the first step, the DMA request flag is changed to change the motor drive current. Also, 2
In the fourth to fourth steps, a current value is set so as to approach a sine wave, and DMA is performed for each range within one step, thereby achieving about 16 steps of microstep driving.

As described above, when one-step motor control data is read from the RAM 5 by the DMA, it is determined whether or not the motor control data is to be DMA-per-range units.
The determination is made using the request flag register 25. If the value of the flag corresponding to the predetermined range is set to perform the DMA according to the output value from the DMA request flag register, the address pointer 27 is counted up after the DMA is completed, and if the setting is made not to perform the DMA, , Such that the address pointer 27 is counted up without performing DMA.

The present invention can be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, and a printer).
The present invention may be applied to an apparatus including two devices (for example, a copying machine and a facsimile machine).

The present invention can of course be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus. Then, a storage medium storing a program represented by software for achieving the present invention is supplied to a system or an apparatus, and the computer (or CPU or M) of the system or the apparatus is supplied.
PU) can read and execute the program code stored in the storage medium, so that the effects of the present invention can be enjoyed.

In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

Examples of a storage medium for supplying the program code include a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, and CD.
-R, magnetic tape, nonvolatile memory card, ROM
(A mask ROM, a flash EEPROM, or the like) can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written in a function expansion port inserted into the computer or a memory provided in a function expansion unit connected to the computer, the program code is read based on the instruction of the program code. It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0098]

As described above, according to the present invention,
DMA for reading control data from RAM by DMA
Since a control circuit and a motor rotation speed setting register are provided, and a DMA request flag for determining whether DMA is generated or not is used and the motor drive current can be set freely within one step, It is possible to set an optimal current value and to create an optimal control table, such as when suppressing fluctuations in the rotation speed of the motor or reducing vibrations of the motor. , The load on the CPU can be reduced, and drive control can be simplified.

Further, according to the present invention, the DMA frequency can be reduced in accordance with the number of current changes in one step, so that the DMA occupancy of the motor can be reduced.
In addition, since there are other functions using DMA, such as expansion of print data and I / F reception, it is necessary to increase the DMA occupancy for other functions by reducing the DMA occupancy of the motor. Is also possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration of a recording apparatus according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a main part of the present system.

FIG. 3 is a block diagram illustrating a configuration of a DMA control circuit.

FIG. 4 is a block diagram illustrating a configuration of an absolute value counter.

FIG. 5 is a waveform diagram showing a motor drive current.

FIG. 6 is an explanatory diagram showing a flag configuration in one step in DMA control.

FIG. 7 is a timing chart illustrating DMA control.

FIG. 8 is a waveform chart showing an example of motor drive control using a DMA control flag.

FIG. 9 is a block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Recording device 2 CPU 3 ROM 4 Gate array 5 RAM 6-8 Motor 9 Motor drive circuit 10 Recording head 15, 16 Motor driver 25 DMA request flag register 26 DMA control circuit 100 Host

Claims (17)

[Claims] 1. An apparatus for controlling driving of a motor, comprising: storage means for storing motor control data for controlling driving of the motor; and at least one unit for driving the motor by one step.
Reading means for reading out the motor control data from the storage means by one or more reading processes, wherein the motor control data read out by one reading process of the reading means includes motor drive current value information; A drive control device, wherein a motor drive current is changed every one read process. 2. An apparatus for controlling driving of a motor, comprising: storage means for storing motor control data for controlling driving of the motor; and at least one unit for driving the motor by one step.
Reading means for reading the motor control data from the storage means by one or more DMA processes, wherein the motor control data read by one DMA process of the reading means includes motor drive current value information,
A drive control device characterized in that a motor drive current is changed for each one of the DMA processes. 3. One step is constituted by a range unit obtained by dividing the inside of the one step at equal intervals in time. The reading means reads the one-step motor control data from the storage means by DMA. 3. The drive control device according to claim 1, wherein it is determined whether or not the motor control data is to be DMA-per-ranged. 4. The drive control device according to claim 3, wherein the determination is made using a DMA request flag register. 5. When the value of the flag corresponding to the predetermined range is set to perform DMA according to the value of the DMA request flag register, the address pointer is counted up after the DMA is completed. , DMA
The drive control device according to claim 4, wherein the address pointer is counted up without performing the operation. 6. A printing apparatus, comprising: the drive control device according to claim 1; and a print head driven by a motor of the drive control device. 7. A method for controlling driving of a motor, comprising: at least one step for driving the motor by one step.
A step of reading motor control data from the storage means by one or more readout processes, wherein the motor control data read out by one readout process includes motor drive current value information, and the motor A drive control method characterized by changing a drive current. 8. A method for controlling driving of a motor, comprising: driving at least one motor to drive the motor by one step;
Reading motor control data from the storage means by one or more DMA processes, wherein the motor control data read by one DMA process includes motor drive current value information, and the one DM process
A drive control method, wherein a motor drive current is changed for each A process. 9. One step is constituted by a range unit obtained by dividing the inside of the one step at equal intervals in time. When the motor control data of the one step is read out from the storage means by DMA, the motor is divided by the range unit. 9. The drive control method according to claim 7, wherein it is determined whether or not to DMA the control data. 10. The drive control method according to claim 9, wherein said determination is made using a DMA request flag register. 11. When the value of the flag corresponding to the predetermined range is set to perform DMA according to the value of the DMA request flag register, the address pointer is counted up after the completion of the DMA. , DM
11. The drive control method according to claim 10, wherein the address pointer is counted up without performing A. 12. A recording method for performing a recording operation on a recording medium by driving a recording head using the drive control method according to claim 7. 13. A medium in which a program for controlling driving of a motor by a computer is recorded, wherein the control program causes the computer to drive at least one step of driving the motor by one step.
The motor control data is read out from the storage means by one or more readout processes, and the motor control data read out by one readout process includes motor drive current value information. A recording medium storing a motor drive control program, wherein the drive current is changed. 14. A medium in which a program for controlling driving of a motor by a computer is recorded, wherein the control program causes the computer to drive at least one step of driving the motor.
The motor control data is read from the storage means by one or more DMA processes, the motor control data read by one DMA process includes motor drive current value information, and the one DM process
A recording medium on which a motor drive control program is recorded, wherein a motor drive current is changed for each A process. 15. One step is constituted by a range unit obtained by dividing the inside of the one step at equal intervals in time. When the motor control data of the one step is read from the storage means by DMA, the motor is divided by the range unit. The recording medium according to claim 13, wherein it is determined whether or not the control data is to be DMAed. 16. A DMA request flag register,
The recording medium according to claim 15, wherein it is determined whether or not to perform DMA. 17. When the value of the flag corresponding to the predetermined range is set to perform DMA according to the value of the DMA request flag register, the address pointer is counted up after the DMA is completed. , D
17. The recording medium according to claim 16, wherein the address pointer is counted up without performing the MA.