JP2000078056A - Sliding correlator and matched filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a sliding correlator and a matched filter by which the precision of calculation is enhanced by dissolving a problem that a calculation result is deteriorated owing to a parasitic capacitance in a sample-and-hold circuit in a conventional sliding correlator and a matched filter. SOLUTION: The second switch 13 of the sample-and-hold circuit 5 is arranged on an addition signal line so that an electrostatic capacitance 12 for holding information is coupled with the parasitic capacitance Cp generated at a contact point of the capacitance 12 with the additional signal line, the occurrence of the re-distribution of electric charges between the electrostatic capacitance 12 and the parasitic capacitance Cp is suppressed even when the second switch 13 is turned on and calculation precision is enhanced in the sliding correlator and the matched filter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sliding correlator and a matched filter used on the receiver side of a spread spectrum communication system in mobile communication, wireless LAN, and the like. The present invention relates to a sliding correlator and a matched filter that can prevent a deterioration in calculation accuracy.

[0002]

2. Description of the Related Art In general, spread spectrum (SpreadSpec)
In a trum: SS) communication system, narrowband modulation (primary modulation) and spread modulation (secondary modulation) are performed on transmission data on the transmission side.
The data is transmitted by performing the two-stage modulation of
After the received data is despread and returned to the primary modulation signal, the baseband signal is reproduced by a normal detection circuit.

Conventionally, as a despreading circuit for a spread-spectrum received signal, a sliding correlator composed of a logic circuit has been used in order to acquire synchronization and take a correlation with a detected synchronization phase thereafter. . The sliding correlator shifts the local oscillation code sequence one bit at a time using a 1-bit correlator, and obtains a correlation with the received code sequence every time. Is obtained, and a synchronous acquisition is performed.

Here, a sliding correlator, which is one of the conventional despreading circuits, will be described with reference to FIG. FIG. 10 is a configuration block diagram of a part of a conventional sliding correlator.

The correlation output portion of the conventional sliding correlator is composed of an AD converter 1, a multiplier 2 ', a PN code register 3, and an adder 4'.

[0006] The AD converter 1 is provided with a code division multiplex (CodeDivi).
sionMultipleAccess: CDMA) modulated and transmitted
It is a high-precision analog / digital converter that converts an analog signal received by an antenna (not shown) into a digital signal.

[0007] The PN code register 3 is a CDM on the transmitting side.
The same spreading code PN (Pseu
doRandomNoise) This register outputs the code.

The multiplier 2 ′ is a multiplier that multiplies digital reception data output from the AD converter 1 by a PN code output from the PN code register 3.

The adder 4 'accumulates the multiplication result output from the multiplier 2' for one symbol period and outputs an integrated value as a correlation output. Here, in order to cumulatively add the multiplication results, the output from the adder 4 'is fed back, and the output delayed by one bit by a delay device or the like (not shown) is input to the adder 4'. The adder 4 'adds the output from the multiplier 2' to perform cumulative addition.

The operation of the conventional sliding correlator is such that an analog signal of received data received by an antenna is converted into a digital signal by an AD converter 1, and a PN code output from a PN code register 3 is multiplied by a multiplier 2 '. The signals are cumulatively added by an adder 4 ', and the addition result for one symbol is output as a correlation signal. The multiplication and the cumulative addition are repeated while changing the phase by shifting the timing of the multiplication in the multiplier 2 'by one chip, and the synchronous phase at which the correlation output reaches a peak is detected.

The configuration using a sliding correlator as a despreading circuit is relatively simple, has a small number of gates, and consumes little power. However, when converting a received analog signal into a digital signal, a high-precision analog / digital converter is used. (The above-mentioned AD converter 1) is indispensable,
There is a problem that the total power consumption is increased, and furthermore, it takes a time (cumulative addition time for one symbol × the number of chips in one symbol) to obtain a correlation output. there were.

As a method of solving this problem relating to time, a matched filter (matched filter or Matche filter) is used.
dFilter: MF). The matched filter performs synchronization acquisition within one symbol time by simultaneously taking correlations when the phases are shifted.

However, in a general matched filter,
In order to take a correlation when the phases are simultaneously shifted, for example, the sliding correlator described above requires gates that are several times the number of chips in one symbol, which increases the gate scale and power consumption, It is difficult to apply to mobile terminals.

As a countermeasure, a matched filter that directly demodulates an analog signal without using an analog / digital converter is disclosed in Japanese Patent Application Laid-Open No. 9-46231, "Matched Filter Circuit".

Here, a matched filter which is another example of the conventional despreading circuit will be described with reference to FIG. FIG. 11 is a block diagram showing a configuration example of a conventional matched filter. The conventional matched filter includes a PN code register 3 for outputting a PN code, which is a spreading code, and a CD.
A plurality of sample-and-hold circuits (S / H) 5 'for sequentially receiving and holding MA-modulated analog signals, and a potential P with respect to the potential held by each sample-and-hold circuit 5'.
It comprises a multiplier 2 "for multiplying the PN code from the N code register 3 and an adder 4" for simultaneously adding outputs from the multiplier 2 ".

In the invention disclosed in Japanese Patent Application Laid-Open No. 9-46231, a so-called neuro operational amplifier circuit is used for the sample and hold circuit 5 for the purpose of reducing power consumption. The neuro operational amplifier circuit is disclosed in Japanese Patent Application Laid-Open No. 6-45839, "Operational Amplifier" and the like, and in addition to the '97 ISSCC Digest of Technical Paper TP6.5P.
It is also described in age100.

[0017]

However, in the above-mentioned conventional digital sliding correlator, A
There is a problem that the power consumption by the D converter 1 is large, and it takes a long time to obtain a correlation output.

The conventional analog matched filter disclosed in Japanese Patent Application Laid-Open No. 9-46231 consumes much less power (approximately one-tenth) than the digital type matched filter, but has an analog type operation. In the circuit, since a neuro operational amplifier is used, an offset voltage is generated due to residual charges in the inverter itself, the operation, and the capacitance constituting the circuit, causing a large offset error between a large number of amplifiers and deteriorating output accuracy. was there.

In order to eliminate such residual charges, it is necessary to periodically perform a so-called refresh in which the capacitor portion is short-circuited, and the operation must be stopped during this refresh. It is necessary to form an extra element for performing the above, and it is necessary to provide a control circuit for controlling the refresh time. Therefore, the circuit configuration is complicated, and there are problems in terms of performance and manufacturing.

Therefore, a sliding correlator as shown in FIG. 12 is conceived as a sliding correlator that can be realized with a simple and small-scale configuration by performing analog arithmetic processing using a normal operational amplifier and that can suppress power consumption. Have been. FIG. 12 is a configuration block diagram of a sliding correlator that performs analog arithmetic processing using a normal operational amplifier. Note that parts having the same configuration as in FIG. 11 are described with the same reference numerals.

As shown in FIG. 12, a sliding correlator for performing an analog operation using a normal operational amplifier includes a positive-phase / negative-phase generating amplifier 6 for generating a positive-phase / negative-phase signal from a CDMA-modulated analog input signal. And CDM
P storing a PN code as a spreading code of A modulation
An N code register 3, a multiplier 2 that multiplies an analog input signal by a PN code using a signal output from a positive-phase / negative-phase amplifier 6 and outputs a multiplication result, and a plurality of samples that hold the multiplication result A hold circuit (S / H) 5; and an adder 4 that, after the end of a predetermined period (generally one symbol period), cumulatively adds the signals held by all the sample / hold circuits 5 and outputs the result as a correlation signal. It is basically composed of

That is, in the sliding correlator, the positive-phase / negative-phase generating amplifier 6 outputs the input signal as it is as a positive-phase signal from the CDMA-modulated analog input signal, and converts the analog signal around a specific voltage. The signal is turned back and output as an inverted phase signal.

Then, according to the PN code output from the PN code register 3 every one chip time, the multiplier 2
Select one of the positive-phase signal and the negative-phase signal and output the result as a multiplication result, and the plurality of sample-and-hold circuits 5 sequentially take in and hold the multiplication result every chip time.

After one symbol time has passed,
The result of the multiplication of the PN code and the analog input signal is held in the number of sample-and-hold circuits 5 corresponding to the spreading factor one chip at a time. Then, at this timing, the signals held by the sample and hold circuit 5 are output all at once, and the adder 4 accumulatively adds the signals output by the sample and hold circuit 5 and outputs the result as a correlation signal.

Here, the sample-and-hold circuit 5 corresponds to FIG.
As shown in FIG. 3, the first switch 11 is normally off and is turned on at the timing when the multiplication result is held.
And an information holding capacitance 12 for holding a multiplication result output from the multiplier 2 at the timing,
It mainly includes a second switch 13 that is turned on at the timing of the addition and is held and outputs the signal to the adder 4. FIG. 13 is a block diagram showing a configuration of the sample-and-hold circuit 5 in a sliding correlator that performs analog operation using a normal operational amplifier.
Note that FIG. 13 illustrates the parasitic capacitance that is not actually connected but is generated during the operation inside a broken line.

The first switch 11 and the second switch 1
3 is a switch using a MOS transistor. In FIG. 13, IN is a terminal that takes in the multiplication result output from the multiplier 2, and S / H is a terminal that receives an input of a signal indicating a timing at which a signal corresponding to each sample-and-hold circuit 5 holds a signal. ADD is a terminal for receiving a signal representing the timing of addition, and ADD
T is a signal line (addition signal line) for simultaneously outputting the held signals.

Here, each sample and hold circuit 5 has
A parasitic capacitance Cp is generated at the junction between the addition signal line and the output-side terminal of the second switch 13 as the capacitance shown in the broken line in FIG. 13, and accordingly, the timing at which the second switch is turned on Then, in the next and subsequent symbols, the electric charge is accumulated in the parasitic capacitance, and every time the second switch is turned on, the electric charge accumulated in the calculation of the previous symbol and the information holding capacitance 12 are multiplied. Is redistributed between the parasitic capacitance and the information holding electrostatic capacitance 12, and the correlation signal as a result of the calculation is deteriorated.

Although the first switch 11 and the second switch 13 use nMOS transistors,
The input signal Vin is a control signal (the first switch 11 outputs S
/ H, which is ADD in the second switch 13), which is not a problem when the voltage is sufficiently large compared to the voltage V ctl, but when Vin and V ctl become substantially equal, The first switch 11 or the second switch 13
The voltage signal transmitted from the input terminal to the output terminal is nM
Assuming that the threshold voltage (threshold voltage) of the OS transistor is Vth, the threshold voltage is degraded to about Vin−Vth.
When Vin becomes smaller than V ctl, there is a problem that the transmitted voltage signal is degraded to V ctl−Vth.

In order to prevent such deterioration, it is considered that the first switch 11 and the second switch 13 are formed as circuits as shown in FIG. FIG. 14 is a circuit diagram illustrating another circuit example of the first switch 11 and the second switch 13.

The first switch 11 and the second switch 13 for preventing the deterioration are, as shown in FIG.
An inverter circuit 21 that receives the input of the voltage Vctl of the control signal, inverts and outputs the voltage signal, a pMOS transistor 22 that performs a switching operation using the signal output from the inverter circuit 21 as a control signal, An nMOS transistor 23 that performs a switching operation using the signal Vctl as it is as a control signal.

That is, in the circuit shown in FIG. 14, the input control signal is inverted, and the pMOS transistor 22 and
By controlling the nMOS transistor 23 to be on or off at the same time, a sufficient voltage signal can be transmitted as compared with the case of a single nMOS transistor.

However, when such a circuit shown in FIG. 14 is used as the first switch 11 and the second switch 13, the scale of the circuit becomes large. For example, when the circuit is formed into an LSI, the area occupied by the circuit of the switch is increased. However, there is a problem that the number increases.

The present invention has been made in view of the above circumstances, and provides a sliding correlator and a matched filter which can be realized with a simple and small-scale configuration, can reduce power consumption, and can increase calculation accuracy. It is intended to be.

[0034]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, a first aspect of the present invention is to provide a CDMA-modulated analog input signal for generating a normal-phase signal and a negative-phase signal. A generation amplifier and a PN code as a CDMA modulation spreading code are stored.
A PN code register that outputs a code, a multiplier that multiplies an analog input signal by a signal output from the positive-phase / negative-phase amplifier and a PN code input from the PN code register, and outputs a multiplication result. A plurality of sample-and-hold circuits for holding the multiplication result output from the multiplier for each chip timing, and an addition signal line, which is a signal line for transmitting each of the sample-and-hold circuits and the multiplication result held by each of the sample-and-hold circuits. A sliding correlator comprising: an adder that is connected, receives a multiplication result held by each of the sample-and-hold circuits through the addition signal line, accumulates and adds the multiplication result held by each of the sample-and-hold circuits, and outputs the result as a correlation signal. A first switch that is turned on at a timing when each of the sample and hold circuits holds a signal; When the switch is turned on, an information holding capacitance that holds an analog signal of a multiplication result input through the first switch, and an information holding capacitance that is provided on the addition signal line and is turned on at the timing of addition. And a second switch for transmitting the multiplication result held by the information holding capacitance to the adder. Without increasing the correlation signal, it is possible to suppress the deterioration of the correlation signal and increase the accuracy of the calculation.

According to a second aspect of the present invention, there is provided a sliding correlator having a positive-phase / negative-phase generating amplifier for generating a positive-phase / negative-phase signal from a CDMA-modulated analog input signal. And CDMA
A PN code register that stores a PN code as a modulation spreading code and outputs each PN code at each chip timing; and an analog input signal and an input from the PN code register using a signal output from the positive-phase / negative-phase amplifier. Multiplied by a given PN code to output a multiplication result, a plurality of information holding capacitances provided corresponding to the spreading factor, and holding the multiplication result output by the multiplier; A first switch that is an nMOS transistor that is turned on at a chip timing, transmits a multiplication result output from the multiplier to the information holding capacitance, and holds the information holding capacitance at the information holding capacitance. An nMOS transistor that is turned on and outputs the multiplication result held by the information holding capacitance to an addition signal line, which is a signal line connected to the adder. A sample-and-hold circuit including a second switch serving as a first switch, and a control for turning on the nMOS transistor so as to transmit a sufficient voltage signal to the nMOS transistor as the first switch of the sample-and-hold circuit. And a first switch control circuit for amplifying and outputting the signal at a specific timing and transmitting a sufficient voltage signal to the nMOS transistor as the second switch of the sample and hold circuit. A second switch control circuit that amplifies and outputs a control signal for turning on the nMOS transistor and outputs a held multiplication result, and is connected to each of the sample and hold circuits and the addition signal line. Receiving the multiplication result held by each of the sample and hold circuits via the addition signal line. It is characterized by having an adder for accumulative addition and outputting as a correlation signal, with a simple and small-sized configuration, suppressing deterioration of the correlation signal without increasing power consumption, and improving the accuracy of calculation. be able to.

According to a third aspect of the present invention, there is provided a sliding correlator according to the second aspect, wherein a control signal in the first switch control circuit or the second switch control circuit is provided. Amplifying means for amplifying includes first, second, and third inverters having an input terminal, an output terminal, a power supply terminal, and a ground terminal;
An nMOS transistor having gate and drain terminals, and a capacitor having first and second terminals;
Power supply terminals of the first and second inverters, and nM
A power supply voltage is applied to the drain terminal of the OS transistor, the ground terminals of the first, second, and third inverters are grounded, and the output terminal of the first inverter is connected to the input terminal of the second inverter. A terminal, a gate terminal of the nMOS transistor, and an input terminal of the third inverter, and an output terminal of the second inverter,
The nMOS connected to a first terminal of the capacitor;
A source terminal of the transistor is connected to a second terminal of the capacitor and a power supply terminal of the third inverter, and the first inverter controls a high voltage level for instructing ON before amplification. An input of a signal or a signal having a low voltage level for instructing OFF is received from an input terminal, and the voltage level of the signal is inverted and output to the second inverter, the nMOS transistor, and the third inverter. A first inverter, and the nMOS
The transistor is turned on when the voltage level of the voltage signal output from the first inverter is high, conducts between the drain terminal and the source terminal, and supplies a power supply voltage to the second terminal of the capacitor. NMOS transistor, and the second inverter is connected to the first
When the voltage level of the voltage signal output by the first inverter is inverted, and the voltage level of the voltage signal output by the first inverter increases, the voltage signal of the low voltage level, which is obtained by inverting the voltage level to the capacitor, is output to the capacitor. When the voltage level of the voltage signal supplied to the first terminal and output by the first inverter decreases, the voltage level of the first terminal of the capacitor is set to a high voltage level, and the voltage level of the second terminal of the capacitor is A second inverter that raises a potential, wherein the third inverter is connected to the first inverter;
Inverting the signal output by the inverter of (1), when the voltage level of the signal output by the first inverter becomes low, the high voltage boosted to the voltage level that is the potential of the second terminal of the capacitor Amplifying means, which is a third inverter that outputs a voltage signal of the level as an amplified control signal from an output terminal and discharges the electric charge held in the second terminal of the capacitor. In addition, with a small-scale configuration, it is possible to suppress the deterioration of the correlation signal and increase the accuracy of the calculation without increasing the power consumption.

According to a fourth aspect of the present invention, there is provided a matched filter in which a plurality of matched filters are provided corresponding to a spreading factor, and multiply an input analog signal by a corresponding PN code. A multiplier that outputs a result of the multiplication, a matrix sample-and-hold circuit including a plurality of basic correlator blocks each including a plurality of sample-and-hold circuits provided corresponding to each of the multipliers according to a spreading factor; An adder for accumulatively adding signals input from the respective basic correlator blocks of the matrix sample and hold circuit via an addition signal line and outputting the signals as a correlation signal;
Each of the basic correlator blocks of the hold circuit holds a multiplication result, which is sequentially shifted in phase by one chip and output by the multiplier, in each sample and hold circuit corresponding to the multiplier, and each of the sample and hold circuits stores the multiplication result. A basic correlator block for sequentially outputting the multiplication results held by each sample-and-hold circuit for each one-chip time from the basic correlator block in a state where the result is held, wherein each of the sample-and-hold circuits holds a signal. A first switch that is turned on at a timing when the first switch is turned on, and an information holding capacitance that holds an analog signal of a multiplication result input through the first switch when the first switch is turned on. , Provided on the addition signal line, turned on at the timing of addition, and the multiplication result held by the information holding capacitance. A sample and hold circuit having a second switch for transmitting the signal to the adder, a simple and small-scale configuration, suppressing deterioration of a correlation signal without increasing power consumption, and performing an arithmetic operation. System can be enhanced.

According to a fifth aspect of the present invention, there is provided a matched filter, comprising:
A plurality of second switch control circuits, a plurality of multipliers corresponding to the spreading factor, multiplying an analog signal by a corresponding PN code, and outputting the result as a multiplication result; and a plurality of multipliers provided corresponding to the respective multipliers. A matrix sample-and-hold circuit including a plurality of basic correlator blocks each including a plurality of sample-and-hold circuits corresponding to the spreading factor, and accumulatively adding signals input from the basic correlator blocks of the matrix sample-and-hold circuit. An adder that outputs a correlation signal, wherein each of the basic correlator blocks of the matrix sample-and-hold circuit sequentially outputs a multiplication result that is shifted in phase by one chip and output by the multiplier to the multiplier. Each sample and hold circuit holds the corresponding multiplication result. A basic correlator block that sequentially outputs the multiplication results held by each sample-and-hold circuit for each one-chip time from the basic correlator block in a state of being in a state, and each of the sample-and-hold circuits is turned on at a timing when a signal is held. a first switch that is an nMOS transistor, an information holding capacitance that holds an analog signal of a multiplication result input via the first switch when the first switch is turned on,
NMO which is turned on at the timing of addition and transmits the multiplication result held by the information holding capacitance to the adder.
A second switch, which is an S transistor, wherein the first switch control circuit transmits a sufficient voltage signal to the nMOS transistor as a first switch of the sample and hold circuit. A first switch control circuit for amplifying and outputting a control signal for turning on the nMOS transistor, wherein the second switch control circuit comprises the nMOS as a second switch of the sample and hold circuit;
It is a second switch control circuit that amplifies and outputs a control signal for turning on the nMOS transistor in order to transmit a sufficient voltage signal to the transistor, and has a simple and small configuration. Further, it is possible to suppress the deterioration of the correlation signal without increasing the power consumption, and to improve the accuracy of the calculation.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described with reference to the drawings. An embodiment according to the present invention will be described separately for a first sliding correlator and a second sliding correlator. The first sliding correlator according to the embodiment of the present invention has a CD at each chip timing.
In a plurality of sample-and-hold circuits for holding a multiplication result of an MA-modulated analog signal and a PN code, a second switch that is turned on when outputting a held signal is simultaneously transmitted to the held signals. A state in which the information holding capacitance for holding the multiplication result and the parasitic capacitance generated at the contact point between the capacitance and the addition signal line are always provided on the addition signal line which is a signal line to be output. As
This prevents charge redistribution between the electrostatic capacitance and the parasitic capacitance when the second switch is turned on, and can calculate a correlation signal with high accuracy.

The first sliding correlator of the present invention is the same as the sliding correlator which performs analog arithmetic processing by using the ordinary operational amplifier shown in FIG. 12, but the sample and hold circuit 5 has the configuration shown in FIG. Thus, it is slightly different from that of FIG. FIG. 1 is a circuit diagram showing a specific circuit of the sample and hold circuit 5 of the first sliding correlator according to the present invention.

That is, the sample and hold circuit 5 in the first sliding correlator of the present invention is normally in the off state, and the first switch 11 which is turned on at the timing of holding the multiplication result, and the multiplier at the timing The information holding capacitance 12 that holds the multiplication result output by 2 and the signal that is normally off and is turned on in response to the input of the signal (ADD) indicating the timing of performing addition are added, and the added signal is added. The second output to the adder 4 via the signal line
And the switch 13 of FIG.

Here, the first switch 11 is the same as that of the sample and hold circuit 5 shown in FIG. 13, except that the information holding capacitance 12 is directly connected to the addition signal line. The second switch 13 is provided on the addition signal line. That is, the plurality of sample-and-hold circuits 5
Are connected in series, respectively.

Therefore, a parasitic capacitance Cp (illustrated in a broken line) generated at a contact point (sampling node) with the addition signal line.
And the information holding capacitance 12 are always connected in parallel, and no charge is redistributed each time the second switch 13 is turned on. Therefore, the correlation by the parasitic capacitance Cp This has the effect of suppressing signal degradation.
The results of specific experiments will be described later.

Next, a second sliding correlator according to the present invention will be described with reference to the drawings. The second sliding correlator amplifies in advance a signal for controlling on / off of a first switch that is turned on at a timing of capturing a signal and a second switch that is turned on at a timing of addition in the sample and hold circuit, and , Second
Are capable of transmitting a sufficient voltage signal, and the accuracy of calculation of the correlation signal can be improved.

As shown in FIG. 2, the second sliding correlator of the present invention comprises a positive-phase / negative-phase generating amplifier 6 for generating positive-phase and negative-phase signals from a CDMA-modulated analog input signal, and a CDMA-modulated amplifier. A PN code register 3 storing a PN code as a spreading code and an analog input signal and a PN
A multiplier 2 that multiplies the code and outputs a multiplication result;
A plurality of sample-and-hold circuits (S / H) 5-1 to 5-n provided corresponding to the spreading factors and holding the multiplication results;
After the specified period (generally one symbol period),
An adder 4 for accumulatively adding signals held by all the sample and hold circuits 5 and outputting as a correlation signal; a first switch control circuit 31 for controlling the first switch 11 of the sample and hold circuit 5; 5 second switch control circuit 3 for controlling the second switch 13
And 2. FIG. 2 is a block diagram showing a configuration of a second sliding correlator according to the present invention.

Here, the positive-phase / negative-phase generating amplifier 6, the PN code register 3, the multiplier 2, the sample hold circuit 5, and the adder 4 are the same as those already described in FIG. Since there is, description is omitted. Here, the sample hold circuit 5 may be the one shown in FIG. 13 or the one shown in FIG.

The first switch control circuit 31 includes first amplifying means 33, and supplies a signal for turning on the first switch 11 to the plurality of sample-and-hold circuits 5 sequentially at each chip timing. And amplifies the output. That is, the first switch control circuit 31 amplifies the signal for turning on the first switch 11 to the first sample hold circuit 5-1 at the first chip timing by the first amplifying means 33 and outputs the signal. Then, at the next chip timing, the signal for turning on the first switch 11 is amplified and output by the first amplifying means 33 to the second sample and hold circuit 5-2, and so on. Output. Also, the second switch control circuit 32
Is provided with a second amplifying means 34, and after a predetermined period of time, a signal for simultaneously turning on the second switches 13 of the sample and hold circuit 5 is amplified by the second amplifying means 34 and output. Things.

First amplifying means 33 and second amplifying means 3
4 are three inverters 4 as shown in FIG.
1-1 to 41-3, a capacitor C, and an nMOS transistor 42. FIG. 3 is a schematic circuit diagram showing the first amplifying unit 33 and the second amplifying unit 34.

Each inverter 41 has an input terminal (IN)
, An output terminal (OUT), a ground terminal (GND), and a power supply terminal (V). Then, OUT of the first inverter 41-1 and IN and n of the second inverter 41-2
The gate terminal (G) of the MOS transistor 42 and the IN of the third inverter 41-3 are connected to each other, and the OUT terminal of the second inverter 41-2 is connected to one end (first terminal) of the capacitor C. The V of the third inverter 41-3 and the source terminal (S) of the nMOS transistor 42
Is connected to the other end (second terminal) of the capacitor C. In addition, the ground terminal (GND) of each inverter 41
Is grounded.

On the other hand, the V of the first inverter 41-1, the V of the second inverter 41-2, the nMOS transistor 4
The second drain terminal (D) is connected to the power supply voltage VDD.

Here, each inverter 41 is composed of a pMOS transistor 51 and an nMOS transistor 52 as shown in FIG. FIG.
1 is a schematic circuit diagram of FIG. As shown in FIG. 4, the inverter 41 connects the drain terminals (D) and the gate terminals (G) of the pMOS transistor 51 and the nMOS transistor 52 to each other, and connects the gate terminal (G) to the input terminal (IN). Are connected, and the output terminal (OUT) is connected to the drain terminal (D). The source terminal (S) of the pMOS transistor 51 becomes the power terminal (V) of the inverter as it is, and the nMOS transistor 52
Is the ground terminal (GND) of the inverter as it is.

That is, each inverter 41 shown in FIG.
When the voltage signal is not input to the input terminal (IN) (when the voltage level is “L”), the pMOS transistor 51 is switched from the source terminal (S) to the drain terminal (D).
Current flows (turns on), the nMOS transistor 52 is turned off, and the output terminal (OU
The voltage level of T) becomes “H”. On the other hand, when a signal is input (when the voltage level is “H”), the pMOS transistor 51 is turned off and the nMOS transistor 52
Is turned on, and the voltage level of the output terminal (OUT) becomes “L”.

Therefore, in the amplifying means shown in FIG. 3, when the voltage level of the input terminal (IN) of the first inverter 41-1 is "L", the output terminal (OUT) of the first inverter 41-1 is output. Becomes "H", the nMOS transistor 42 is turned on, and the power supply voltage VDD is supplied to the power supply terminal V of the third inverter 41-3.

The voltage level of the input terminal IN of the second inverter 41-2 and the third inverter 41-3 is "H".
And the voltage level of the output terminal of the second inverter 41-2 becomes "L". Therefore, the charge of the power supply voltage VDD−Vth is stored in the capacitor C. At this time, the output terminal (OUT) of the third inverter 41-3
Also becomes “L”.

When the voltage level of the input terminal (IN) of the first inverter 41-1 becomes "H", the voltage level of the output terminal (OUT) of the first inverter 41-1 becomes "L". The voltage level of the output terminal (OUT) 2 is "H", that is, the level of the voltage VDD. At this time,
The nMOS transistor 42 is off.

Therefore, the voltage signal boosted to 2VDD-Vth together with the electric charge stored in the capacitor C is applied to the power supply terminal V of the third inverter 41-3. At this time, the input terminal (I
Since the voltage level of N) is "L", the voltage of the output terminal (OUT) of the third inverter 41-3 is 2VDD-Vth
Becomes

That is, both the first amplifier 33 and the second amplifier 34 output 2V depending on whether the level of the input voltage signal is “H” or “L”.
A signal of a voltage of DD-Vth and a voltage signal of a GND level are output.

Next, the operation of the second sliding correlator of the present invention will be described. First, the normal-phase / negative-phase generating amplifier 6 outputs the input signal as it is as a normal-phase signal from the CDMA-modulated analog input signal, and folds the analog signal around a specific voltage to output it as a negative-phase signal. I do. Then, according to the first PN code output from the PN code register 3,
The multiplier 2 selects one of the positive-phase signal and the negative-phase signal and outputs the result as a multiplication result.

At this time, the first switch control circuit 31
Amplifies the signal for turning on the first switch to the first sample-and-hold circuit 5-1 with the first amplifying means 33, and outputs the amplified signal. When turned on, the information holding capacitance 12 holds the multiplication result output from the multiplier 2.

Here, 2VDD-Vth is applied as the control voltage Vctl to the nMOS transistor forming the first switch 11 by the function of the first amplifying means 33, and the nMOS transistor eventually has a maximum of 2VDD. -V
th−Vth, that is, 2VDD−2Vth. In general, VDD is about 3 V, Vth is about 1 V,
The input voltage Vin is equal to or lower than VDD. Therefore, the maximum voltage signal transmitted from the nMOS transistor is 2VDD-2Vth =
Vin ≦ 3 V is always smaller than 2 × 3−2 × 1 = 6−2 = 4 V, and the nMOS transistor always transmits Vin without deterioration. Then, the undegraded Vin is held in the information holding capacitance of each sample and hold circuit 5.

Then, at the next chip timing, the multiplier 2
Selects and outputs either the positive-phase signal or the negative-phase signal output from the positive-phase / negative-phase generation amplifier 6 according to the second PN code output from the PN code register 3, and outputs the first switch control circuit. 31 supplies a signal for turning on the first switch 11 to the second sample-and-hold circuit 5-2 for the first time.
The information holding capacitance 12 of the sample hold circuit 5-2 holds the multiplication result output from the multiplier 2. Thereafter, in a similar manner, the plurality of sample-and-hold circuits 5 sequentially take in and hold the multiplication result of the CDMA-modulated analog input signal and the PN code at the corresponding timing.

When one symbol time has elapsed,
The result of the multiplication of the PN code and the analog input signal is held in the number of sample-and-hold circuits 5 corresponding to the spreading factor one chip at a time. Then, at this timing, the second switch control circuit 32 outputs a signal amplified by the second amplifying means 34, and each sample and hold circuit 5 turns on the second switch 13 at once,
The held signal is output, and the adder 4 accumulatively adds the signal output from the sample and hold circuit 5 and outputs the signal as a correlation signal.

Here, a second amplifier similar to the first amplifier 33 is used.
Of the amplifying means 34, 2VDD-Vth is applied as a control voltage Vctl to the nMOS transistor forming the second switch 13, and the nMOS transistor transmits a maximum of 2VDD-Vth-Vth, that is, 2VDD-2Vth. Therefore, the held voltage is output to the adder 4 as it is.

According to the second sliding correlator of the present invention, the transfer characteristic of the nMOS transistor has no effect on the calculation result of the correlation signal, and there is an effect that a highly accurate correlation signal can be obtained.

Since a matched filter can be constructed using the first and second sliding correlators of the present invention, such a matched filter will be described below. A matched filter (first matched filter) using the first sliding correlator according to the present invention includes:
In the above-described first sliding correlator of the present invention, as shown in FIG.
Is used as the basic correlator block 10, and the basic correlator blocks 10 are arranged by the number corresponding to the spreading factor (in the claims, the arrangement of the basic correlator blocks 10 is referred to as a matrix sample and hold circuit). The phase of the PN code or the phase of capturing the analog input is shifted one chip at a time,
At the timing of the addition, the signals held sequentially for each of the basic correlator blocks 10 are added, and the multipliers 2 are provided by the number of spreading factors, and the PN codes are set in advance. K of correlator block 10
The sample-and-hold circuit 5 receives the signal output from the k-th multiplier 2. FIG.
1 is a schematic configuration diagram of a matched filter of the present invention.

That is, assuming that the spreading factor is n, each sample and hold circuit 5-1 to 5-n of the first basic correlator block 10 has a corresponding multiplier 2 at the first to n-th chip timings. , And the sample-hold circuits 5-1 to 5-n of the second basic correlator block fetch the multiplication results at the second to (n + 1) th chip timings, respectively. The correlator blocks 10 hold the multiplication results output from the corresponding multipliers 2 at the timing shifted by one chip, and add the signals held for each basic correlator block 10. By doing so, correlation signals in each phase are sequentially obtained from the timing at which one symbol time has elapsed, and it is possible to operate as a matched filter.

Further, the matched filter (second matched filter) using the second sliding correlator of the present invention is the same as the above-described matched filter using the first sliding correlator of the present invention. Basically, each of the arranged basic correlator blocks 10
The signal output from the first switch control circuit 31 is input to each sample-and-hold circuit 5 with a shift by one, and the signal output from the second switch control circuit 32 is Is sequentially input to each of the web pages. FIG. 6 is a schematic configuration diagram of the second matched filter of the present invention.

That is, assuming that the spreading factor is n, each of the sample-and-hold circuits 5-1 to 5-n of the first basic correlator block 10 performs the first-to-first conversion according to the signal output from the first switch control circuit 31. The multiplication results output by the corresponding multipliers 2 at the chip timings of the n-th to n-th are fetched, and the sample-hold circuits 5-1 to 5-n of the second basic correlator block are used for the second to (n + 1) -th Each of the basic correlator blocks 10 holds the multiplication result at a timing shifted by one chip so that the multiplication result output from the corresponding multiplier 2 is fetched at the chip timing, and the second switch control circuit 32
Output the signals sequentially for each of the basic correlator blocks 10, so that the signals held for each of the basic correlator blocks 10 are added. By doing so, correlation signals in each phase are sequentially obtained from the timing at which one symbol time has elapsed, and it is possible to operate as a matched filter.

Here, a circuit in which a plurality of basic correlator blocks 10 of such a matched filter are arranged includes an information holding capacitance 12, a first switch 11 and a second switch 13 arranged in a grid pattern. As a configuration,
Easy to use LSI layout pattern
Can be manufactured as

When such a matched filter is used, once synchronization can be supplemented, demodulation can be performed using a part (for example, three) of the basic correlator blocks 10. Also, when performing delayed RAKE combining of delayed waves,
Since the number of basic correlator blocks 10 to be operated can be freely adjusted, there is an effect that unnecessary power is not consumed and power consumption can be reduced.
The oversampling and the processing for each of the I phase and the Q phase can be performed by appropriately providing a plurality of the above-described sliding correlators and matched filters.

In each of the above-described sliding correlators and matched filters of the present invention, the positive-phase / negative-phase generating amplifier 6 and the multiplier 2 are, for example, differential amplifiers that return a voltage input with a constant DC voltage and output the same. Amplifier and P
A switch may be used to select and output either the inverted negative-phase signal or the original positive-phase signal in accordance with the N code. If the input voltage is large, it outputs a specific voltage (for example, 2.5 V), and if it is not high, it outputs another specific voltage (for example, 0.5 V). Alternatively, a switch for selecting whether to output the signal output from the AD converter as it is or not may be used.

Further, when an AD converter is used, two thresholds may be provided to convert an input analog signal into a step-like signal.

According to the sliding correlator and the matched filter of the present invention, when they are used as a despreading circuit in a demodulation unit of a receiver, they are simple, small-scale, and have low power consumption. This has the effect of being suitable for various mobile terminals, and has the effect of enabling synchronization acquisition and demodulation with high accuracy.

[0074]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the first sliding correlator of the present invention will be described with reference to FIGS. FIG.
FIG. 7A is a circuit diagram illustrating an example of a simulation circuit of a sample and hold circuit 5 in a conventional sliding correlator, and FIG. 7B is an example of a simulation circuit of the sample and hold circuit 5 in the first sliding correlator of the present invention. FIG. 8 is a circuit diagram showing
FIG. 8A is an explanatory diagram illustrating a simulation result of an output of the sample and hold circuit 5 in the conventional sliding correlator, and FIG. 8B is a diagram illustrating an output of the sample and hold circuit 5 in the first sliding correlator of the present invention. FIG. 9 is an explanatory diagram illustrating a simulation result.
In FIG. 7, the capacitor Cp represents a parasitic capacitance generated at the point, and the resistor R represents the resistance of the addition signal line.

As described above, as shown in FIG. 7 (b), the sample and hold circuit 5 in the first sliding correlator of the present invention has the second switch 13 on the addition signal line. Regardless of whether the second switch is on or off, the parasitic capacitance and the information holding electrostatic capacitance 12 are always in a coupled state. Here, the voltage Vin applied to the input terminal (IN) is 2
V, the voltage Vctl applied as a control signal to the first switch 11 is 3 V when “H”, 0 V when “L” (hereinafter referred to as “3 V / 0 V”), and the second switch 13 The voltage VGATE applied as a control signal is 3 V / 0
V, and the reference voltage VREF is 1.5 V.

As shown in FIG. 8A, the simulation result in such a case shows that the output of the conventional circuit is deteriorated by about 0.02 V where the output should be the same 2 V as the input voltage Vin. On the other hand, it can be seen that the sample-and-hold circuit 5 of the first sliding correlator of the present invention shown in FIG. 8B outputs a 2V voltage signal.

Next, an embodiment of the second sliding correlator of the present invention will be described with reference to FIGS. 9 (a) to 9 (c). FIGS. 9A to 9C are explanatory diagrams illustrating simulation results of signal changes at respective points of the first amplifying unit 33 and the second amplifying unit 34 of the second sliding correlator of the present invention.

FIG. 9B shows the power supply of the third inverter 41-3 when a signal as shown in FIG. 9A is applied to the input terminal (IN) of the first inverter 41-1. The change of the voltage signal applied to the terminal (V) is shown. FIG.
As shown in (b), the signal is VDD-Vth when in the state of "L", and 2VDD-Vth in the state of "H".
It can be seen that it is Vth. Here, VDD is 3
V, and Vth is about 0.4V.

FIG. 9C shows a change in the voltage signal obtained at the output terminal (OUT) of the third inverter 41-3. As shown in FIG. 9C, it can be seen that the signal is 0 V when in the “L” state and 2VDD−Vth when in the “H” state.

[0080]

According to the first aspect of the present invention, the first switches in the plurality of sample-and-hold circuits provided corresponding to the spreading factor are turned on at each chip time, and the analog signal and the PN signal are turned on. Sliding for holding the multiplication result with the code in the information holding capacitance, turning on the second switch provided on the addition signal line at the timing of addition, and outputting the held multiplication result to the addition signal line. Since a correlator is used, the parasitic capacitance generated at the contact between the information holding capacitance and the addition signal line is coupled to the information holding capacitance, so that the second switch is turned on. There is no redistribution of electric charge at the timing of, and with a simple and small configuration, it is possible to suppress the deterioration of the correlation signal without increasing the power consumption and to improve the accuracy of the calculation. That.

According to the second and third aspects of the present invention, control is performed so that a sufficient voltage signal is transmitted to the nMOS transistor as the first switch in the plurality of sample and hold circuits provided corresponding to the diffusion rates. A first switch control circuit for amplifying the signal and outputting the signal to be turned on at each chip time, and holding a multiplication result of the analog signal and the PN code in an information holding capacitance; and a second switch as a second switch. a second switch control circuit for amplifying a control signal, outputting the signal to be turned on at the addition timing, and outputting the held multiplication result to an addition signal line in order to transmit a sufficient voltage signal to the nMOS transistor; Since it is a correlator, even if the switch of the sample-and-hold circuit is realized by an nMOS transistor, nM
By amplifying the signal for controlling the OS transistor, signal degradation due to the characteristics of the nMOS transistor can be prevented. With a simple and small-scale configuration, degradation of the correlation signal is suppressed without increasing power consumption. Thus, there is an effect that the arithmetic system can be enhanced.

According to a fourth aspect of the present invention, there is provided a matrix sample-and-hold circuit provided with a number of basic correlator blocks each having a number corresponding to the spreading factor and corresponding to the spreading factor. The second signal is turned on to transmit the signal held in the information holding capacitance to the addition signal line at the timing of addition.
Are provided on the addition signal line, each basic correlator block holds the multiplication result of the analog signal shifted in phase by one chip and the PN code, and the multiplication result held for each basic correlator block. Is a matched filter that outputs a correlation signal having a phase shift of one chip at a time, so that the parasitic capacitance generated at the contact point between the information holding capacitance of each sample and hold circuit and the addition signal line indicates the information. By being coupled to the holding capacitance, electric charge is not redistributed at the timing of addition when the second switch is turned on, and power consumption is increased with a simple and small-scale configuration. Thus, there is an effect that the deterioration of the correlation signal can be suppressed and the accuracy of the calculation can be increased.

According to a fifth aspect of the present invention, there is provided a matrix sample-and-hold circuit provided with a number of basic correlator blocks each having a number corresponding to the spreading factor, the number corresponding to the spreading factor. First and second switch control circuits each outputting a signal for controlling an nMOS transistor which is a first and second switch, and a control signal for transmitting a sufficient voltage signal to the first and second switches. Are amplified and output. Each basic correlator block holds a multiplication result of an analog signal shifted in phase by one chip and a PN code, and a multiplication result held for each basic correlator block is held. By performing a cumulative addition, it becomes a matched filter that outputs a correlation signal shifted in phase by one chip. Even if the switch of the hold circuit is realized by an nMOS transistor, signal deterioration due to the characteristics of the nMOS transistor can be prevented by amplifying the signal for controlling the nMOS transistor. There is an effect that it is possible to suppress the deterioration of the correlation signal and increase the accuracy of the calculation without increasing the power.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a specific circuit of a sample and hold circuit 5 of a first sliding correlator according to the present invention.

FIG. 2 is a block diagram showing a configuration of a second sliding correlator according to the present invention.

FIG. 3 is a schematic circuit diagram showing a first amplifier 33 and a second amplifier 34.

FIG. 4 is a schematic circuit diagram of an inverter 41.

FIG. 5 is a schematic configuration diagram of a matched filter of the present invention.

FIG. 6 is a schematic configuration diagram of a second matched filter of the present invention.

7A is a circuit diagram illustrating a simulation circuit example of a sample and hold circuit 5 in a conventional sliding correlator, and FIG. 7B is a circuit diagram illustrating the sample and hold circuit 5 in the first sliding correlator of the present invention.
FIG. 4 is a circuit diagram illustrating a simulation circuit example of FIG.

FIG. 8A is an explanatory diagram illustrating a result of a simulation of an output of the sample and hold circuit 5 in the conventional sliding correlator, and FIG. 8B is a diagram illustrating a first example of the present invention;
FIG. 9 is an explanatory diagram illustrating a simulation result of an output of the sample and hold circuit 5 in the sliding correlator of FIG.

FIG. 9 is an explanatory diagram showing a simulation result of a signal change at each point of the first amplifying unit 33 and the second amplifying unit of the second sliding correlator of the present invention.

FIG. 10 is a configuration block diagram of a part of a conventional sliding correlator.

FIG. 11 is a block diagram showing a configuration example of a conventional matched filter.

FIG. 12 is a block diagram illustrating a configuration of a sliding correlator that performs analog arithmetic processing using a normal operational amplifier.

FIG. 13 is a block diagram showing a configuration of a sample-and-hold circuit 5 in a sliding correlator that performs an analog operation using a normal operational amplifier.

FIG. 14 is a circuit diagram illustrating another circuit example of the first switch 11 and the second switch 13.

[Explanation of symbols]

1 AD converter, 2, 2 ', 2 "... multiplier, 3 P
N code register, 4, 4 ', 4 "... adder, 5,
5 ': sample-and-hold circuit, 6: positive-phase / negative-phase generating amplifier, 10: basic correlator block, 11: first switch, 12: capacitance for holding information, 13: second
Switches 21 ... inverters 22 ... pMOS transistors 23 ... nMOS transistors 31 ...
First switch control circuit, 32 second switch control circuit, 33 first amplifier means, 34 second amplifier means, 41 inverter, 42 nMOS transistor, 51 pMOS transistor, 52 nMOS
Transistor

Claims (5)

[Claims] 1. A normal-phase / negative-phase generating amplifier for generating a normal-phase and negative-phase signal from a CDMA-modulated analog input signal, and a PN code as a CDMA modulation spread code,
A PN code register that outputs each PN code for each chip timing; and a signal output from the positive-phase / negative-phase amplifier multiplied by an analog input signal and a PN code input from the PN code register. A plurality of sample-and-hold circuits that hold the multiplication result output by the multiplier for each chip timing; a signal line that transmits each of the sample-and-hold circuits and the multiplication result that is held by each of the sample-and-hold circuits And an adder that receives the multiplication result held by each of the sample and hold circuits via the addition signal line, accumulates and adds the result as a correlation signal after a predetermined period of time. Wherein each of the sample-and-hold circuits is turned on at the timing of holding a signal. A first switch, an information holding capacitance for holding an analog signal of a multiplication result input via the first switch when the first switch is turned on, and the addition signal A second switch provided on a line and turned on at the timing of addition and transmitting a multiplication result held by the information holding capacitance to the adder. Sliding correlator. 2. A normal-phase / negative-phase generating amplifier for generating a normal-phase and a negative-phase signal from a CDMA-modulated analog input signal, and a PN code as a CDMA modulation spread code,
A PN code register that outputs each PN code for each chip timing; and a signal output from the positive-phase / negative-phase amplifier multiplied by an analog input signal and a PN code input from the PN code register. And a plurality of information holding capacitances, each of which is provided corresponding to a spreading factor and holds a multiplication result output by the multiplier, and which is turned on at a specific chip timing to output the multiplier. The first switch, which is an nMOS transistor that transmits the multiplication result to the information holding capacitance and holds the information holding capacitance, is turned on at the addition timing, and the information holding capacitance is turned on. NM that outputs the held multiplication result to an addition signal line, which is a signal line connected to the adder.
A sample and hold circuit including a second switch that is an OS transistor; and turning on the nMOS transistor to transmit a sufficient voltage signal to the nMOS transistor as the first switch of the sample and hold circuit. A first switch control circuit for amplifying and outputting a control signal and holding a multiplication result at a specific timing; and transmitting a sufficient voltage signal to the nMOS transistor as the second switch of the sample and hold circuit. A second switch control circuit that amplifies and outputs a control signal for turning on the nMOS transistor and outputs a held multiplication result, and is connected to each of the sample and hold circuits by the addition signal line. The multiplication result held by each of the sample and hold circuits is Cumulatively adds received by via a sliding correlator characterized by having an adder which outputs as a correlation signal. 3. The first switch control circuit or the second switch control circuit, wherein the amplifying means for amplifying a control signal includes first and second terminals having an input terminal, an output terminal, a power supply terminal, and a ground terminal. 2, a third inverter, an nMOS transistor having a source, a gate, and a drain terminal, and a capacitor having first and second terminals, a power supply terminal of the first and second inverters, nM
A power supply voltage is applied to the drain terminal of the OS transistor, the ground terminals of the first, second, and third inverters are grounded, and the output terminal of the first inverter is connected to the input terminal of the second inverter. A terminal, a gate terminal of the nMOS transistor, and an input terminal of the third inverter, an output terminal of the second inverter is connected to a first terminal of the capacitor, and a source of the nMOS transistor. The terminal is connected to a second terminal of the capacitor and a power terminal of the third inverter, and the first inverter is configured to output a high-level control signal or an OFF signal for instructing ON before amplification. From the input terminal, inverts the voltage level of the signal, and inputs the second inverter and the n
A first inverter that outputs to a MOS transistor and the third inverter, wherein the nMOS transistor is turned on when a voltage level of a voltage signal output by the first inverter is high, and the drain terminal And an nMOS transistor that conducts between the source terminals and supplies a power supply voltage to the second terminal of the capacitor, wherein the second inverter inverts a voltage level of a voltage signal output by the first inverter. When the voltage level of the voltage signal output by the first inverter increases, a low-level voltage signal obtained by inverting the voltage level to the capacitor is supplied to the first terminal, and the first inverter When the voltage level of the voltage signal output by the capacitor decreases, the voltage level of the first terminal of the capacitor is increased to a higher voltage. A second inverter in which the potential of the second terminal of the capacitor is boosted, wherein the third inverter inverts a signal output by the first inverter, When the voltage level of the signal output by the inverter decreases, a voltage signal of a high voltage level, which has been boosted to a voltage level that is the potential of the second terminal of the capacitor, is output as an amplified control signal. 3. A sliding correlator according to claim 2, wherein said amplifying means is a third inverter which outputs a signal from said second capacitor and discharges a charge held in a second terminal of said capacitor. 4. A multiplying unit for multiplying an input analog signal by a corresponding PN code, the plurality of analog signals being provided corresponding to a spreading factor,
A multiplier that outputs a result of the multiplication; a matrix sample-and-hold circuit that includes a plurality of basic correlator blocks each including a plurality of sample-and-hold circuits provided corresponding to each of the multipliers in accordance with a spreading factor; An adder for accumulatively adding signals input from the respective basic correlator blocks of the sample and hold circuit via an addition signal line and outputting as a correlation signal, the respective basic correlators of the matrix sample and hold circuit The blocks are shifted in phase one chip at a time,
The multiplication result output from the multiplier is held in each sample-hold circuit corresponding to the multiplier, and each sample-hold circuit sequentially holds one chip time from the basic correlator block in a state in which the multiplication result is held. A first switch that is turned on at a timing when each sample and hold circuit holds a signal, and a first switch that is turned on when each sample and hold circuit holds a signal. , And an information holding capacitance for holding an analog signal of a multiplication result input via the first switch, provided on the addition signal line, turned on at the timing of addition, and A second switch for transmitting a multiplication result held by the information holding capacitance to the adder; A matched filter characterized by the following. 5. A first and second switch control circuit, a plurality of multipliers provided corresponding to a spreading factor, multiplying an analog signal by a corresponding PN code, and outputting a result of multiplication; A matrix sample-and-hold circuit including a plurality of basic correlator blocks each including a plurality of sample-and-hold circuits provided in correspondence with a multiplier, the number of which corresponds to a spreading factor; and each of the basic correlator blocks of the matrix sample-and-hold circuit. Cumulative addition of input signals,
An adder for outputting as a correlation signal, wherein each of the basic correlator blocks of the matrix sample and hold circuit is sequentially shifted in phase by one chip,
The multiplication result output from the multiplier is held in each sample-hold circuit corresponding to the multiplier, and each sample-hold circuit sequentially holds one chip time from the basic correlator block in a state in which the multiplication result is held. A first correlator block that outputs a multiplication result held by each sample and hold circuit, wherein each of the sample and hold circuits is an nMOS transistor that is turned on at a timing of holding a signal; When the switch is turned on,
An information holding capacitance that holds an analog signal of a multiplication result input via a first switch; and an on-state at an addition timing, and the multiplication result held by the information holding capacitance is added to the addition result. And a second switch that is an nMOS transistor that transmits the signal to a sample and hold circuit. The first switch control circuit supplies a sufficient voltage signal to the nMOS transistor as a first switch of the sample and hold circuit. A first switch control circuit for amplifying and outputting a control signal for turning on the nMOS transistor to transmit the signal, wherein the second switch control circuit serves as a second switch of the sample-and-hold circuit. In order to transmit a sufficient voltage signal to the nMOS transistor, the nMOS transistor is turned on. Matched filter, which is a second switch control circuit that amplifies and outputs a control signal to.