JP2000078004A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation circuit supplying the clock of low skew/low jitter and in addition a high speed semiconductor integrated circuit by means of it in the logic circuit and the memory circuit of a micro processor and the like. SOLUTION: A first ring oscillation circuit (OSC11) where plural inventors 110 are connected in a ring form, a second ring oscillation circuit (OSC12) where plural inventors are connected in the ring form a and a conductive wiring are installed. The output of at least one inverter in the first ring oscillation circuit and the output of at least one inverter in the second ring oscillation circuit are connected to the conductive wiring. A switch circuit (SW1112) is arranged in the conductive wiring connecting the output of the first ring oscillation circuit and the output of the second ring oscillation circuit.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit and an oscillation circuit.
Low jitter and low skew clock distribution system
And a semiconductor integrated circuit device. [0002] A conventional PLL (Phase locked loop) is used.
The clock generation method used is, for example, IEE
ー, Journal of Solid State Circuit
Pp. 1599--1607, November 1992 (IEEE JOURNA
L OF SOLID-STATE CIRCUITS, VOL 27, NO 11, Novembe
r 1992) (hereinafter referred to as prior art A).
FIG. 2 shows the configuration of a clock generation unit using a conventional PLL.
ing. fext is a reference clock signal input from outside
is there. PFD is a phase frequency comparator, CP is a charge pump
LPF is a low-pass filter, VCO0 is a voltage controlled oscillator, D
IVN is 1 / N divider, DIV2 is 1/2 divider, N0 is clock
Figure 2 shows a network distribution network. Each detailed circuit
Is omitted. [0003] Reference clock fext and internal clock fint
Phase and frequency difference are compared by the phase frequency comparator PFD.
As a result, error signals UP and DN are output. This error signal
Converted to analog signal by dipump CP, low-pass
The high frequency component of the error signal is removed by the filter LPF.
After that, the oscillation frequency control signal VC is supplied to the voltage controlled oscillator VCO0.
Is entered. The oscillation output of the voltage controlled oscillator VCO0 is divided
DIV2, 50% duty ratio at half frequency
The frequency is divided by the oscillation output fint0 and the clock distribution network N
Entered as 0. Return signal fin from clock distribution system
t is frequency-divided by a 1 / N divider, and then phase-frequency comparator PFD
Entered as 0. The phase locked loop PLL0 provides a reference clock.
The clock fext and the internal clock fint synchronize in phase, and the
The wave number is N times fext. [0005] The frequency of the internal clock fint
Wave number is increasing year by year, and chip area is increasing
As a result, the area of the clock distribution network N0 is large
It has become to. Fast and stable clocks over a wide range
In order to supply, in the above-mentioned prior art,
Problems arise. (1) When the clock distribution network is delayed
The delay between fint0 and fint, compared to 1 / fint
Relatively large. This allows the clock distribution net
Skew of work is clock distribution network and PLL0
The performance of the combined clock distribution system is limited. In addition, a large number of clock supply ranges within a chip are required.
Independent PLL for each clock supply range
There is also a method to provide, but in this method, the following
There is such a problem. (2) Generally, PLL is a power supply noise and a board noise.
Weak against noise such as fint0
The vibration frequency and phase fluctuate (jitter). Chip
Providing a large number of PLLs in a loop means that each PLL
Needs to be considered to reduce noise
You. (3) The total area of a large number of PLLs is the entire chip surface
Affects the product. Considering issue (2), each P
The area of LL further increases. (4) Clocks between independent clock supply ranges
The skew is determined by the scan within the clock supply range.
To TskewL, PLL jitter to Tjitter, and PLL
If the skew of the quasi-clock is TskewG, TskewG + 2 * Tsk
It becomes ewL + 2 * Tjitter and becomes very large. [0011] The inventors of the present application have solved the above problems.
Focusing on this, as a solution,
Filed. In addition, as a result of further study,
According to the report, since many PLLs are provided,
I found the problem of increasing. Means for Solving the Problems (1) A plurality of inverters
At least two rings connected in a multistage ring
In the oscillation circuit consisting of the oscillation circuit and the conductive wiring,
Of at least one inverter in the
Connect the output to conductive wiring. (2) A plurality of inverters are connected in multiple stages
At least two delay lines and conductive wiring
In the delay line circuit, one of the delay lines
The output of at least one inverter to the conductive wiring
Connect to (3) Ring-shaped or meshed conductive wiring
It may be formed in the shape of a push. (4) Further, a ring oscillator / delay line
May be connected to the conductive wiring at equal intervals. (5) Ring oscillator / delay line
Is connected to the conductive wiring at least one of the intervals
It may be 50 μm or more. (6) As described above, the ring oscillator / data
The oscillating array lines oscillate at the same frequency. (7) Obtained by means of the above (1)-(6)
Clock distribution to conductive wiring of oscillation circuit / delay line
The system is connected and a voltage-controlled oscillation circuit is configured. (8) The voltage controlled oscillation circuit obtained by the means of (7)
Circuit, phase frequency comparator, charge pump circuit and low pass
Configure a PLL or DLL using filters. (9) PLL or DLL obtained by means of (8)
Logic circuits and memory circuits in semiconductor integrated circuits using
Supply lock. Low consumption when applied to portable information equipment, etc.
It is desirable to consider the power, in such a case
The following configuration is suitable. That is, multiple
First ring oscillation circuit in which barters are connected in a ring shape
And a second relay in which a plurality of inverters are connected in a ring.
A first ring oscillation circuit having a ring oscillation circuit and conductive wiring
An output of at least one inverter of the circuit and a second
The output of at least one inverter of the
Connected to the conductive wiring, and connected to the output of the first ring oscillation circuit.
In the conductive wiring connecting to the output of the second ring oscillation circuit,
It has a switch circuit. In this way, the equipment
Oscillation of the ring oscillation circuit unnecessary for operation can be stopped.
Power consumption can be reduced. A plurality of inverters are connected in a ring.
The first ring oscillator circuit and the plurality of inverters
A second ring oscillation circuit connected in a ring shape,
At least one of the first ring oscillator circuit
The output of the inverter and at least the second ring oscillator circuit
The output of one inverter is connected to conductive wiring and
The load drive capability of the inverter connected to the
Greater than the load drive capability of other inverters
So that it becomes In this way, an inverter that requires a driving force
Data with large priority and the other small
The overall power consumption can be reduced.
You. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
Examples will be described. FIG. 1 is a schematic diagram showing a connection configuration of an oscillator according to the present invention.
It is a reminder. OSC1 to OSCn are ring oscillators.
Ring oscillator is inverter 110 ~ 11m, 120 ~ 12m, 1n0 ~ 1
Consists of nm. Oscillation node of ring oscillator
Are connected to nodes 101 to 10n, respectively.
Nodes 101 to 10n that are adjacent to each other are connected in a ring
ing. Here, the distance between neighboring nodes (for example, node 1
(Distance between 01 and node 102) are all approximately equal distance l.
Inverters 110-11m, 120-12m, 1n0-1nm are not particularly limited
No, but a CMOS inverter may be used. Figure 1 below for simplicity
In the description, a CMOS inverter will be used. Oscillation of each ring oscillator OSC1 to OSCn
Because the nodes are connected, the ring oscillator OSC1
OSCn oscillates at the same phase / frequency. FIG. 3A shows a case where the number of ring oscillators is four.
4 shows a circuit simulation waveform. The horizontal axis is time, and the vertical axis is
In the figure, V (x) indicates the potential of node x.
Represent. The transistors used in the simulation are
CMOS with a length Lg of 0.25 μm, inverters 110 to 11 m, 120
~ 12m, 1n0 ~ 1nm are all the same inverter (PMOS gate width
Wp was 10 μm, and the NMOS gate width Wn was 5 μm). Power-supply voltage
Is 1.8 V, the distance l between nodes is 3 mm, and each node 101 at 0 ns.
~ 104 temporarily assume that different potentials are used as initial values.
Specified. Does it have a different phase at time 0ns?
However, in the steady state after a while from time 0ns, the ring
Oscillator OSC1 to OSC4 oscillate at the same phase / frequency
You can see that. With such a configuration, the distance l
Oscillating ring oscillators with the same phase / frequency
Can be. The distance l may be 1 μm or 10 mm.
There is an advantage that it does not depend on its length. In the above, the distance between adjacent nodes in FIG.
Equal distance l, but not always equal distance
You may not. In that case, in steady state, each ring
The oscillators have the same frequency but not the same phase.
Each ring oscillator is synchronized while maintaining the phases δ1 to δn.
Oscillate (the distance between neighboring nodes is all the same distance l
If so, δ1 = δ2 =. . . = δn). FIG. 3 shows the configuration of each ring oscillator.
Inverters 110 ~ 11m, 120 ~ 12m, 1n0 ~ 1nm are the same
Therefore, it is not always necessary to be the same.
Otherwise, in the steady state as before,
These ring oscillators have the same frequency but the same phase.
No. Each ring oscillator has phases δ1 to δn.
And oscillate synchronously. Conversely, the phases δ1 to δn
The type of inverter (load drive capability, etc.)
Can be changed. Utilizing this property,
Even if the distances between the
By adjusting the inverter type of the
It is possible to adjust the phases δ1 to δn of the
Wear. Generally, inverters 11m-1nm are connected to nodes 101-1
0n and the wiring connecting them must be driven
Therefore, relatively large load drive capability (for CMOS,
To increase the width). So, for example,
Inverters 110, 111,. . . Load driving capacity in the order of 11m
Increasing the value is effective in reducing power consumption. Further, in each ring oscillator, an inverter
The number of stages may not be the same. Natural oscillation of each ring oscillator
If the frequencies are somewhat the same, it is determined by the configuration of the present invention.
Under normal conditions, each ring oscillator has the same frequency and phase δ
It is possible to synchronize and oscillate while keeping 1 ~ δn
Next, the oscillator of the present invention is not affected by power supply voltage fluctuation and substrate voltage fluctuation.
Describe the characteristics when any noise is added. FIG. 3B shows that only the ring oscillator OSC1 has the other
Circuit oscillator when the power supply voltage differs from that of the
It is a simulation waveform. Power supply for ring oscillator OSC1
The pressure was 2.0 V, and the other conditions were the simulations in Fig. 3 (A).
It is the same as when Steady state after time 0ns
State, the ring oscillators OSC1 to OSC4 have almost the same phase / frequency
It can be seen that oscillation occurs by the number. The present invention comprising a number of ring oscillators
Power supply voltage of several ring oscillators
Operation, the phase / frequency of the entire oscillator hardly changes.
(In a steady state where there is no power supply voltage fluctuation or board voltage fluctuation,
Power supply if ring oscillator has phases δ1-δn
Function to maintain the phase against voltage fluctuation and substrate voltage fluctuation
). The power supply voltage fluctuation applied to the ring oscillator
So that it does not affect the power supply voltage of the ring oscillator.
The effect of the tobacco is greater. Generally occurs in integrated circuits
Power supply voltage fluctuations are local because
If the power is shared by the ring oscillators, the distance l
The longer the better. In addition, from each ring
What is necessary is just to avoid sharing power as much as possible with a shaker. Was
For example, separate power supply voltage generators for each ring oscillator
Alternatively, a power supply or power supply voltage stabilizer may be used. As described above, the effect of the present invention on power supply voltage fluctuation
The same applies to substrate voltage fluctuations.
Can be said. FIG. 4 shows the noise resistance of the present invention.
It is an example. Compared to FIG. 1, each ring oscillator OSC1 to OSC
n is a pair of two ring oscillators {OSC1a, OSC1b} to {OSCna,
The major difference lies in that it is composed of OSCnb #. Sa
Furthermore, the power supply of the ring oscillator pair is different power supply VDD1.
a to VDDna and VSS1a to VSSna and VDD1b to VDDnb and VSS
Connected to 1b to VSSnb. The power supplies VDD1a to VDDna and VSS1a to VSSna
The power supply voltage changes to the power supplies VDD1b to VDDnb and VSS1b to VSSnb simultaneously.
The probability that noise such as motion gets on is low due to the locality of noise.
In this case, noise caused by fluctuations in power supply voltage, substrate voltage, etc.
The fluctuations of the oscillation frequency and phase between 400 and 40n
be able to. The above-described effect is obtained by suppressing power supply voltage fluctuation.
A so-called bypass capacitor (bias capacitor)
Similar to the effect of The decap is noisy
Signal is a constant potential (potential called power supply voltage).
And works to maintain the potential when there is noise.
In contrast, the oscillator of the present invention has a steady state with no noise.
For signals whose state is a constant oscillation frequency / phase,
Works to maintain the frequency / phase when there is noise. In the examples of FIGS. 1 to 4, the single-ended
An input / output inverter is used.
Input / output differential inverters OSC1d to OSCnd (differential inverter
The detailed circuit example of the data is shown in Fig. Of Conventional Example A. Listed in 11
May be omitted). In this case, the differential input
In the case of a converter, the oscillation output is a positive logic output and a negative logic output.
1 correspond to nodes 101 to 10n in FIG.
Cards such as {501a, 501b} to {50na, 50nb}
Become In the examples of FIGS. 1 to 5, each ring
The oscillators are one of the oscillation nodes
Each ring oscillator is connected as shown in Fig. 6.
Using multiple oscillation nodes (having different phases)
You may. In FIG. 6, two nodes 601a to 60na and 601b to 60n
b are connected to each other. Comparison with the connection configuration of Fig. 1
The coupling between each ring oscillator increases
Increases the noise resistance. FIGS. 7 and 8 show different connections from the example of FIG.
It is an example of an embodiment. FIG. 7 shows a comparison with the example of FIG.
Direct connection between ring oscillator OSC1 and ring oscillator OSCn
The feature is that there is no wiring. In this case, nodes 101 to 10n
The distance l between adjacent nodes is the same, l
All the oscillators OSC1 to OSCn have the same characteristics.
Also, each ring oscillator OSC1 to OSCn has the same frequency
But do not have the same phase. Each ring oscillator is
Oscillates synchronously while maintaining the phases Δ1 to Δn. Phase δ1 ~ δn
To achieve the same, adjust the distance between neighboring nodes
But it is possible, but the type of each ring oscillator OSC1 to OSCn
It is also possible to adjust (such as load driving capability). For example, both ends
Ring oscillator OSC1 and OSCn load drive capability of other ring
What is necessary is just to make it half of an oscillator. FIG. 8 shows a ring oscillator in an n × q mesh shape.
This is an example of connection. Various other connection types are conceivable
However, the ring oscillators are synchronized regardless of the topology.
And oscillate. In short, multiple natural oscillation frequencies are almost the same.
Connected to the same oscillator, and the oscillators
If you connect the nodes of each ring oscillator so that
Good. The same effects as in the examples of FIGS. 1 to 4 can be obtained. Less than
In the following example, the present invention will be described using the embodiment of FIG. 1 for simplicity.
An embodiment using a shaker will be described. FIG. 9 shows a plurality of theories using the oscillator of the present invention.
This is an example in which a clock is supplied to a logical circuit. LOG1-LOGn
Is a logic circuit, and 711 to 71n are buffers. Compare with Figure 1
Then, nodes 701 to 70n corresponding to nodes 101 to 10n in FIG.
Are connected to buffers 711-71n, and their outputs 721-72n
It is supplied to each of the logic circuits LOG1 to LOGn. As aforementioned
Nodes 701 to 70n have the same frequency and phase (as described above).
In some cases, there are phases δ1 to δn.
Therefore, Fig. 7 shows that the condition is connected under the same phase.
Oscillate). Zero skew in logic circuits LOG1 to LOGn
Clock can be supplied. In addition,
Because it has noise resistance. Clock with low jitter
Can be supplied. Of course, buffers 711-71n
Needless to say, it is not necessary. Buffers 711-71n
Propagation of noise from logic circuits LOG1 to LOGn to oscillator
Can be suppressed. When there is noise, the nodes 701 to 70n
The skew is caused by the change in the node potential as can be seen from FIG.
It is smaller after some time has passed since the conversion. I
Therefore, buffers 711-71n connected to nodes 701-70n
It is better to use as Schmitt input. Buffer 711-71n
Output skew can be reduced. In the example of FIG. 9, the clock supplied to each logic circuit is
Adjust the delay time of each buffer 711-71n.
Clocks input to each of the logic circuits LOG1 to LOGn
The phases of 721 to 72n can be individually adjusted in the direction of delay. FIG. 10 further shows a clock supplied to each logic circuit.
In the example, it is possible to adjust the direction to advance the phase of 721 to 72n.
is there. Oscillation node 80 connecting each ring oscillator
The oscillation nodes {831a, 831b, 831c,. . . }
~ {81na, 83nb, 83nc,. . . } Select buffer 711
Connected to ~ 71n. For example, oscillation node 831a
Phase one stage earlier than the mode 801 (a ring oscillator
Are composed of the same inverter p stages, 360 / p
Phase will be earlier). Accordingly
From this oscillation node, the logic circuit L
If a clock is supplied to OG1, buffer from oscillation node 801
Faster than the logic circuit generating the clock through the
A phase clock can be obtained. FIG. 11 shows an oscillator according to the present invention using a PLL voltage-controlled oscillator.
This is an example used for a shaker (VCO). VCO1 to VCOn are voltage controlled
Oscillator, fint1 to fintn is its output. 901-90n is buff
And N1 to Nn are clock distribution networks. In FIG.
Compared with the embodiment, the ring oscillators OSC1 to OSCn are
Control oscillators VCO1 to VCOn, and their oscillation frequency control signal VC
Is controlled by a PLL structure to constitute PLL1. Also, buff
Global clocks 911 to 91n, which are the outputs of
It is connected to clock distribution networks N1-Nn. The connection form of the voltage controlled oscillators VCO1 to VCOn is simple.
For simplicity, the method of the example of FIG. 1 was used.
The method shown may be used. Also, the example of FIG. 11 is the same as that of FIG.
By comparison, the equivalent of the 1/2 frequency divider DIV2 has been omitted.
But if necessary, before the buffer 901 ~ 90n
May be connected to the subsequent stage. FIG. 12 shows a circuit example of VCO1 to VCOn. FIG.
(A) Inverter 1000-1 with single-ended input / output
This is an example in the case of a configuration of 00m. Each inverter
Delay time varies with the value of the oscillation frequency control signal VC.
The oscillation frequency of the oscillation output fint1 is controlled by the oscillation frequency
Varies depending on the value of the control signal VC.
The example of the road is Fig. Of Conventional Example A. Omitted because it is described in 4.
). On the other hand, Fig. 12 (B) shows a differential inverter with differential input / output.
This is an example in a case where the length is set to 101 to 101 m. Same as Fig. 12 (A)
The delay time of each differential inverter is controlled by the oscillation frequency.
Oscillation output fint is changed by the value of control signal VC.
1, the oscillation frequency of / fint1 becomes the value of the oscillation frequency control signal VC.
(The detailed circuit example of the differential inverter is
Fig. A of example A. It is omitted because it is described in 11). FIG. 13 shows the clock distribution network N1 of FIG.
FIG. 1100 to 110k are clock wiring, 1110
111111k is a local buffer. 1100 ~ 110k clock
The length of each wiring is equal to the global clock 911.
To local buffers 1110 to 111k
Are arranged on the chip layout so that the values are equal. I
Therefore, the characteristics of the local buffers 1110 to 111k are completely
The same (hereinafter referred to as matching), and
When there is no noise, local clock outputs out1 to ou
The skew of tk is zero. The voltage controlled oscillators VCO1 to VCOn have the same oscillation frequency.
Since the wave number control signal VC is supplied, as described above,
The oscillation outputs fint1 to fintn have the same frequency / same phase
(Some cases have phases δ1 to δn as described up to FIG. 8.
However, here, for simplicity, each of the voltage controlled oscillators VCO1 to VCOn
Are connected to the condition having the same phase).
Oscillate. Therefore, local clock outputs out1 to ou
tk oscillates at the same frequency and phase. Figure 10
Since the same noise resistance as the effect of the example in
Increase in skew / jitter due to voltage fluctuation and substrate voltage fluctuation
Is small. FIG. 14 is a circuit diagram showing the PLL of FIG.
Microprocessors with strict performance requirements for PLL
This is an example used for: Reference numeral 1200 denotes a microprocessor;
Is a logic circuit block, and 1211 to 1213 are clock distributions in FIG.
It is equivalent to a network. Logic circuit block
Is not particularly limited. Data path with built-in
Or a memory such as a cache
Controller. The global clocks 1231 to 1233 are output from PLL1.
Is output. Its global clocks 1231-1233 are
Each logical cycle by the clock distribution network 1211-1213
It is distributed to the local clock 1241 in the road block. Most
Later, the local clock 1241 is connected to a circuit such as the latch 1220.
It is supplied to the clock input unit. As in the example of FIG. 11, the local clock 1241
Skew / jitter due to power supply voltage fluctuations and board voltage fluctuations
Data increase is small. Also, the voltage controlled oscillator VCO1 in PLL1
~ Distribute VCOn in the chip and take charge of the logic circuit block
The voltage controlled oscillators VCO1 to VCOn
From the clock output of the
(See FIG. 14 for the global clock 123
1, clock distribution network 1211, local clock 1
241) can be shortened. Delay time between short paths
Skew and jitter generated on the path
Influence the overall performance of the clock distribution system.
it can. Divide the clock supply range in the chip into many
Independent PLLs are provided for each clock supply range
(Hereinafter referred to as the multi-PLL method)
Clock skew between the specified clock supply ranges
The skew within each clock supply range is reduced by TskewL and PLL.
Tjitter jitter, reference clock skew to each PLL
Is TskewG, TskewG + 2 * TskewL + 2 * Tjitter
You. In the method of the present invention, the global clock output from PLL1 is
TjitterN is the clock jitter, and the clock distribution network
If the skew of the clocks 1211-1213 is TskewLN, the clock
The skew is 2 * TskewLN + TjitterN. If TskewL =
As for TskewLN, the method of the present invention has a higher clock skew.
Can be reduced. Actually, as described above, the PLL of the present invention
TjitterN <Tjitter, so the method of the present invention
The queue can be greatly reduced. Further, a larger number of Vs than in the multi-PLL system
The method of the present invention that synchronizes by dispersing CO in the chip is better
Chip area can be reduced. In the above embodiment, the external clock is used by using the PLL method.
An example of synchronizing the lock and the internal clock has been described.
A raid locked loop (DLL) method may be used.
For example, place the ring oscillator in Fig. 1 with a delay line.
It is easy to apply the present invention by changing the configuration.
You. FIG. 15 shows an example. FIG. 16 further shows the delay of FIG.
A DLL with the delay line as the variable delay line.
Here is an example. Compared to FIG. 11, the variable delay delay line
The point that the reference clock fext is input to the VDL1 to VDLn
to differ greatly. In addition, the embodiment of FIG.
It is self-evident that it can be applied to the example shown. In the above embodiment, the book inside one chip
This is the case where the invention is applied.
The embodiment of the semiconductor integrated circuit device comprising
Is self-evident. For example, each logic circuit block in FIG.
And the voltage-controlled oscillator VCO responsible for it
Or each ring oscillator in Figure 1
Apply the present invention in a case where each chip is composed of different chips
It is easy. In the above embodiment, the power consumption is reduced.
So-called gated clock method
Although the embodiment is not shown, for example, buffers 711 to 7 in FIG.
The present invention is suitable for a case where 1n is changed to a gate circuit.
It is easy to use. There are various other methods
However, the method is not particularly limited. In the above example, a plurality of inverters are
Although a ring oscillator circuit connected in a ring shape was used,
The composition is not particularly limited. Also, even if it is not a ring oscillation circuit
Any oscillation circuit may be used. The oscillation frequency and
And the phase uses the oscillation output of the oscillation circuit as an input / output line.
And connect multiple oscillation circuits as described above.
Thus, a plurality of oscillation circuits may oscillate in synchronization. In the above example, a semiconductor device for realizing the present invention is used.
The body process and transistor structure are not specified.
No. CMOS process may be used, or SOI wafer using SOI wafer
A transistor may be used. Power supply voltage and its type
There is no particular limitation. In the example shown above, a plurality of transmitters are used.
In order to prepare, it is desirable to consider the reduction of current consumption.
You. In FIG. 1, inverters 11m-1nm are nodes 101-10n.
And the wires connecting them need to be driven
Therefore, a relatively large load drive capability (gate
(To increase the width). Therefore, Invar
11m to 1nm load drive capability and other inverters
If the data is kept small, it is effective to reduce power consumption. As another method in consideration of low power consumption,
Control so that only some of the transmitters operate
Can be considered. Next, many oscillations used in the present invention
FIG. 17 shows a method of operating only a part of the vessels. FIG. 17 is a diagram showing a ring emitted from an n × q mesh in FIG.
In this embodiment, the ring oscillators are connected to each other.
Switch is connected to the wiring. This switch
Although not particularly limited, for example, as shown in the lower side of FIG.
A CMOS switch is sufficient. When operating all ring oscillators
Makes all switches conductive. On the other hand, for example,
Operating only the oscillators OSC11, OSC12, OSC21, and OSC22.
Switch when you do not want to operate other ring oscillators.
Switch SW1213, SW2223, SW2232, and SW2131 to the non-conductive state.
You. Switches SW1213, SW2223, SW2232, SW2131 are non-conductive
The effect of the ring oscillator that is not operating
It affects the operation of the ring oscillators OSC11, OSC12, OSC21, and OSC22.
No more. For example, a clock only for some circuits
When it is desired to reduce power consumption by supplying
And control methods can be used. In the examples so far, the frequency of the ring oscillator is
This is controlled by the oscillation frequency control signal VC.
Has been assumed, but the clock input from outside
Therefore, an oscillator that is determined may be used. This is for example PL
This can be achieved by using an L structure. FIG. 18 shows an example in which this is applied to the example of FIG.
You. Each of PLL11 to PLLqn receives an external clock.
You. Compared to the example of FIG. 8, PLs are used instead of OSC11 to OSCqn.
L11 to PLLqn are used. In addition, the terminals of PLL11 to PLLqn
Has two terminals, an input terminal and an output terminal.
8, it is connected to the mesh conductor wiring. PLL1
1 to the mesh conductor connected to the output terminal of PLLqn
The lines match the phases of the output terminals of PLL11 to PLLqn as in FIG.
I use it to adjust. On the other hand, the input terminals of PLL11 to PLLqn
The mesh conductor wiring connected to the
It is for inputting a click. The reference clocks are PLL11 to PLLqn
In particular, the shape shown in FIG.
It is not limited to. Reference clock supplied to each of PLL11 to PLLqn
Is slightly different depending on the input terminal position of each of PLL11 to PLLqn.
Also, PLLs 11 to
The phase error at the output terminal of qn is small. In the embodiment of FIG.
Need to distribute the transmission frequency control signal VC chip to the whole
However, in the embodiment shown in FIG.
All you need to do is distribute the locks. Conventional distribution of reference clock
From the commonly used clock distribution method
The advantage is that it can be easily realized. This place
In this case, the main advantage of the present invention is that the reference with distributed phase error
From the clock, a clock with less error and noise
That it can generate FIG. 19 shows an example of each of PLLLPLL11 to PLLqn.
Since the symbols used in FIG. 19 are the same as those in FIG. 2,
Here, the description is omitted. As described above, according to the present invention, the mask
Low logic circuits such as microprocessors and memory circuits
Clock with low jitter and low jitter.
And thereby realizes a high-speed semiconductor integrated circuit device.
Can appear.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of the simplest inverter chain connection shown in the present invention. FIG. 2 is a block diagram showing a structure of a clock generation unit using a conventional PLL. FIG. 3 is a waveform diagram of a circuit simulation waveform of the oscillation circuit of the present invention. FIG. 4 is a block diagram showing an example in which a ring oscillator is connected to another power supply in the oscillator of the present invention. FIG. 5 is a block diagram showing a case where a differential inverter is used as a ring oscillator. FIG. 6 is a block diagram showing a connection form different from that of FIG. 1; FIG. 7 is a block diagram showing a connection form different from that of FIG. 1; FIG. 8 is a block diagram when ring oscillators are connected in an array. FIG. 9 is a block diagram in which a clock is supplied to a plurality of logic circuits using the oscillator of the present invention. FIG. 10 is a block diagram in which the phase of a clock to each logic circuit can be adjusted in the earlier direction in the invention of FIG. 9; FIG. 11 is a block diagram in which the oscillator of the present invention is used as a voltage controlled oscillator (variable frequency oscillator) to configure a PLL. FIG. 12 is a simple circuit diagram of a voltage controlled oscillator. FIG. 13 is a simple conceptual diagram showing a clock distribution network. FIG. 14 is a conceptual diagram of an embodiment of a microprocessor according to the present invention. FIG. 15 is a block diagram when the present invention is applied to a delay line. FIG. 16 is a block diagram illustrating a DLL using the delay line of FIG. 15 as a voltage control delay line (variable delay line). FIG. 17 is a block diagram when a switch is connected to the embodiment of FIG. 8; FIG. 18 is a block diagram when the ring oscillator of the embodiment of FIG. 8 is a PLL. FIG. 19 is a block diagram of the PLL in FIG. 18; [Description of Signs] 110, 111, 11m, 120, 121, 12m, 1n0, 1n1, 1nm ... Inverter, OSC1, OSC2, OSCn, OSC1a, OSC1b, OSC2a, OSC2b, OSCn
a, OSCnb ... Ring oscillator, OSC1d, OSC2d, OSCnd ... Ring oscillator using differential inverter, PFD ... Phase frequency comparator, CP ... Charge pump, LPF ... Low pass filter, VCO0 ... Voltage controlled oscillator , DIVN ... 1 / N divider, DIV2 ... 1/2 divider, N0, N1, N2, Mn, 1211, 1212, 1213 ... Clock distribution network, VDD1a, VDD2a, VDDna, VDD1b, VDD2b, VDDnb: Positive power supply voltage, VDD1a, VSS2a, VSSna, VSS1b, VSS2b, VSSnb: Negative power supply voltage, LOG1, LOG2, LOGn: Logic circuit, 711, 712, 71n, 901, 902, 90n, 1110, 1111, 111k ……
Buffer, VCO1, VCO2, VCOn …… Voltage controlled oscillator, 1000, 1001, 100m …… Single-ended voltage controlled inverter, 1010, 1011, 101m …… Differential voltage controlled inverter, VC …… Oscillation frequency control signal, 911, 912 , 91n, 1231, 1232, 1233 ... global clock, 1100, 1101, 110k ... clock wiring, out1 to outk, 1241 ... local clock, 1220 ... latch, 1200 ... microprocessor, DLY1, DLY2, DLYn ... delay line, VDL1, VDL2, VDLn ... variable delay line.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Koichiro Ishibashi             1-280 Higashi Koikebo, Kokubunji-shi, Tokyo             Central Research Laboratory, Hitachi, Ltd. F term (reference) 5B079 AA07 CC08 CC14 CC20 DD02                       DD06 DD08 DD13 DD20                 5J106 AA04 BB03 CC01 CC20 CC21                       CC38 CC41 CC52 DD09 DD32                       GG01 HH08 JJ01 KK02 KK25                       KK38 KK40 LL01

Claims (1)

Claims: 1. A first ring oscillation circuit in which a plurality of inverters are connected in a ring, a second ring oscillation circuit in which a plurality of inverters are connected in a ring, and conductive wiring. An output of at least one inverter of the first ring oscillation circuit and an output of at least one inverter of the second ring oscillation circuit are connected to the conductive wiring; 2. The semiconductor integrated circuit device according to claim 1, further comprising a switch circuit in a conductive wiring connecting an output of the circuit and an output of the second ring oscillation circuit. 2. The semiconductor integrated circuit device according to claim 1, wherein said conductive wiring is formed in a ring shape. 3. The semiconductor integrated circuit device according to claim 1, wherein the conductive wiring is formed in a mesh shape, and at least one connection between the conductive wiring and the output of the inverter is made at an intersection of the mesh. 4. The semiconductor integrated circuit device according to claim 1, wherein the connection between the conductive wiring and the output of the inverter is connected at equal intervals. 5. The semiconductor integrated circuit device according to claim 1, wherein at least one of the intervals at which the conductive wiring and the output of the inverter are connected is at least 50 μm. . 7. The semiconductor integrated circuit device according to claim 1, wherein said ring oscillator oscillates at an equal frequency. 8. A first amplifier comprising a plurality of amplifiers connected in a ring.
A ring oscillation circuit, a second ring oscillation circuit in which a plurality of amplifiers are connected in a ring, a wiring connecting the first ring oscillation circuit and the second ring oscillation circuit, and a switch circuit, A semiconductor integrated circuit, wherein the ring oscillation circuits are connected to each other when the switch circuit is in a conductive state, and the ring oscillation circuits are non-conductive to each other when the switch circuit is in a non-conductive state. Circuit device. 9. The semiconductor integrated circuit device according to claim 8, wherein the oscillation frequency of said ring oscillation circuit is controlled by a clock signal inputted from outside. 10. The above-mentioned ring oscillation circuit, comprising: an oscillator; an oscillation output of the oscillator or a signal obtained by dividing the oscillation output and a reference clock; and a phase frequency comparator for outputting a first error signal; And a low-pass filter that inputs the second error signal and outputs a third error signal. The oscillator includes a third error signal. 10. The semiconductor integrated circuit device according to claim 8, wherein a signal is input. 11. A first ring oscillation circuit having a plurality of inverters connected in a ring, a second ring oscillation circuit having a plurality of inverters connected in a ring, and a conductive wiring. An output of at least one inverter of one ring oscillation circuit and an output of at least one inverter of the second ring oscillation circuit are connected to the conductive wiring, and load driving of the inverter connected to the conductive wiring is performed. A semiconductor integrated circuit device having a capability greater than a load driving capability of another inverter of the ring oscillation circuit. 12. A semiconductor integrated circuit device, wherein a gate width of an inverter connected to the conductive wiring is larger than a gate width of another inverter of the ring oscillation circuit. 13. A plurality of inverters each having a plurality of ring oscillation circuits connected in a ring shape, a conductive wiring connecting the plurality of ring oscillation circuits, and being connected to the ring oscillation circuit or the conductive wiring. A semiconductor integrated circuit device comprising: a clock distribution system; and a switch circuit for interrupting connection of the plurality of inverters by the conductive wiring.