JP2000077259A - Stacked capacitor and its manufacture - Google Patents

Stacked capacitor and its manufacture

Info

Publication number
JP2000077259A
JP2000077259A JP10242960A JP24296098A JP2000077259A JP 2000077259 A JP2000077259 A JP 2000077259A JP 10242960 A JP10242960 A JP 10242960A JP 24296098 A JP24296098 A JP 24296098A JP 2000077259 A JP2000077259 A JP 2000077259A
Authority
JP
Japan
Prior art keywords
reducing agent
laminate
external electrode
semiconductor layer
internal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10242960A
Other languages
Japanese (ja)
Inventor
Toshiki Nishiyama
俊樹 西山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP10242960A priority Critical patent/JP2000077259A/en
Publication of JP2000077259A publication Critical patent/JP2000077259A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a stacked capacitor whose connection resistance between an external electrode and an internal electrode is low and stable, and its manu facturing method. SOLUTION: This stacked capacitor is comprised of a laminated body 6, which is formed by laminating a plurality of insulation sheets 4 in which internal electrodes 2 and 3 are formed, while cover sheets are arranged on the upper and lower sides thereof, and by sintering the whole body. The stacked body 6 is provided with semiconductor layers 12 on its both end faces. The internal electrodes 2 and 3 are electrically connected respectively with external electrodes 22 and 23 via the semiconductor layer 12. A reducing agent is applied to both end faces of the stacked body 6 and a plate for forming external electrodes is applied thereto, and then the stacked body 6 is heated at the same time so as to diffuse the reducing agent in the laminated body 6 as well as form external electrodes 22 and 23. A plated covering film is formed on the external electrodes 22 and 23.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、積層型コンデンサ
及びその製造方法に関する。
The present invention relates to a multilayer capacitor and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来より、この種の積層型コンデンサと
して、特開平2−277205号公報記載のものや、特
開平5−62859号公報記載のものが知られている。
特開平2−277205号公報記載の積層セラミックコ
ンデンサは、誘電体セラミックシートとPd等からなる
貴金属の内部電極とを積み重ねて積層体を構成し、さら
に、この積層体の両端面に半導体化剤ペーストを塗布す
る。この後、この積層体を空気中で焼成して積層体を磁
器化すると共に、半導体化剤を積層体内に熱拡散させて
積層体の両端部を還元し、半導体層を形成する。次に、
半導体層を形成した積層体の両端面に銀ペーストを塗布
し、空気中で焼き付けて外部電極を形成する。こうして
得られた積層セラミックコンデンサは、内部電極と外部
電極が半導体層を介して電気的に接続している。
2. Description of the Related Art Hitherto, as this type of multilayer capacitor, those described in Japanese Patent Application Laid-Open No. 2-277205 and those described in Japanese Patent Application Laid-Open No. 5-62859 have been known.
The multilayer ceramic capacitor described in Japanese Patent Application Laid-Open No. 2-277205 has a laminated structure in which a dielectric ceramic sheet and a noble metal internal electrode made of Pd or the like are stacked, and a semiconducting agent paste is provided on both end surfaces of the laminated body. Is applied. Thereafter, the laminate is fired in the air to make the laminate porcelain, and the semiconductor agent is thermally diffused into the laminate to reduce both ends of the laminate to form a semiconductor layer. next,
A silver paste is applied to both end surfaces of the stacked body on which the semiconductor layer is formed and baked in air to form external electrodes. In the multilayer ceramic capacitor thus obtained, the internal electrodes and the external electrodes are electrically connected via the semiconductor layer.

【0003】また、特開平5−62859号公報記載の
積層セラミックコンデンサは、誘電体セラミックシート
と内部電極とを積み重ねて積層体を構成した後、焼成す
る。さらに、この焼結積層体の両端面にZn等の卑金属
ペーストを塗布した後、卑金属ペーストを空気から隔離
するため銀ペーストを塗布し、これらを空気中で焼き付
けて外部電極を形成すると共に、積層体のセラミック素
体中に含まれている酸素が粒子間拡散によって卑金属ペ
ーストに取り込まれ、卑金属ペーストを酸化させる。こ
れにより、卑金属ペーストが塗布された積層セラミック
コンデンサの端面近傍のセラミック素体は還元され、半
導体層となる。こうして得られた積層セラミックコンデ
ンサは、内部電極と外部電極が半導体を介して電気的に
接続している。
In the multilayer ceramic capacitor disclosed in Japanese Patent Application Laid-Open No. 5-62859, a dielectric ceramic sheet and internal electrodes are stacked to form a laminate, which is then fired. Furthermore, after applying a base metal paste such as Zn to both end surfaces of the sintered laminate, a silver paste is applied to isolate the base metal paste from the air, and these are baked in air to form external electrodes, Oxygen contained in the ceramic body of the body is taken into the base metal paste by interparticle diffusion and oxidizes the base metal paste. Thereby, the ceramic body near the end face of the multilayer ceramic capacitor to which the base metal paste has been applied is reduced and becomes a semiconductor layer. In the multilayer ceramic capacitor thus obtained, the internal electrodes and the external electrodes are electrically connected via a semiconductor.

【0004】[0004]

【発明が解決しようとする課題】ところが、特開平2−
277205号公報記載のセラミックコンデンサ及び特
開平5−62859号公報記載のセラミックコンデンサ
は、半導体層の形成と外部電極の形成を別工程で行なっ
ているので、外部電極を空気中で焼き付ける際、半導体
層の一部が空気中の酸素によって再び酸化されてしま
い、半導体層の抵抗が上昇し、外部電極と内部電極の接
続抵抗が高くなるという問題があった。また、半導体層
は、外部電極形成時の加熱により半導体化剤や酸素の熱
拡散が再び促進され、半導体層の領域のコントロールが
困難であるという問題もあった。
SUMMARY OF THE INVENTION However, Japanese Patent Laid-Open No.
In the ceramic capacitor described in Japanese Patent No. 277205 and the ceramic capacitor described in Japanese Patent Application Laid-Open No. 5-62859, the formation of the semiconductor layer and the formation of the external electrode are performed in separate steps. Is oxidized again by oxygen in the air, and the resistance of the semiconductor layer increases, and the connection resistance between the external electrode and the internal electrode increases. Further, the semiconductor layer also has a problem that the heat diffusion during the formation of the external electrode promotes the thermal diffusion of the semiconducting agent and oxygen again, and it is difficult to control the region of the semiconductor layer.

【0005】そこで、本発明の目的は、外部電極と内部
電極の接続抵抗が低く安定している積層型コンデンサ及
びその製造方法を提供することにある。
It is an object of the present invention to provide a multilayer capacitor in which the connection resistance between an external electrode and an internal electrode is low and stable, and a method of manufacturing the same.

【0006】[0006]

【課題を解決するための手段】以上の目的を達成するた
め、本発明に係る積層型コンデンサは、(a)非還元性
材料からなる複数の絶縁性材料層と卑金属材料からなる
複数の内部電極とを積み重ねて構成した積層体と、
(b)前記積層体の端面に形成された半導体層と、
(c)前記積層体の端部に設けられ、前記半導体層を介
して前記内部電極に電気的に接続した外部電極と、を備
えたことを特徴とする。
In order to achieve the above object, a multilayer capacitor according to the present invention comprises (a) a plurality of insulating material layers made of a non-reducing material and a plurality of internal electrodes made of a base metal material. And a laminate formed by stacking
(B) a semiconductor layer formed on an end face of the laminate,
(C) an external electrode provided at an end of the stacked body and electrically connected to the internal electrode via the semiconductor layer.

【0007】また、本発明に係る積層型コンデンサの製
造方法は、(d)非還元性材料からなる絶縁性材料層
と、卑金属材料からなる複数の内部電極とを積み重ねた
後、焼成して焼結積層体を構成する工程と、(e)前記
焼結積層体の端面に還元剤を付与した後、該還元剤の上
に外部電極材料を付与する工程と、(f)前記還元剤と
前記外部電極材料とを同時に熱処理し、前記還元剤を前
記焼結積層体内に拡散させて半導体層を前記焼結積層体
の端面に形成すると共に、前記外部電極材料にて外部電
極を形成する工程と、を備えたことを特徴とする。
Further, the method for manufacturing a multilayer capacitor according to the present invention is characterized in that (d) an insulating material layer made of a non-reducing material and a plurality of internal electrodes made of a base metal material are stacked, fired and fired. (E) applying a reducing agent to an end face of the sintered laminate, and then applying an external electrode material on the reducing agent; (f) providing the reducing agent with the reducing agent; Simultaneously heat-treating the external electrode material and forming a semiconductor layer on the end face of the sintered laminate by diffusing the reducing agent into the sintered laminate, and forming an external electrode with the external electrode material; , Is provided.

【0008】この製造方法において、前記内部電極の外
部電極接続側端部が、前記絶縁性材料層の縁との間に所
定寸法のギャップを形成するように、前記内部電極と前
記絶縁性材料層とを積み重ねて積層体を構成してもよ
い。あるいは、前記絶縁性材料層と前記内部電極とを積
み重ねた後、焼成する際に、前記内部電極の収縮によっ
て前記内部電極の端部を前記焼結積層体の端面から引き
込み、前記内部電極が前記半導体層を介して前記外部電
極に電気的に接続するようにしてもよい。
In this manufacturing method, the internal electrode and the insulating material layer are formed such that an end of the internal electrode on the external electrode connection side forms a gap having a predetermined dimension between the edge of the insulating material layer. May be stacked to form a laminate. Alternatively, after stacking the insulating material layer and the internal electrode, when firing, the end of the internal electrode is pulled from the end face of the sintered laminate by shrinkage of the internal electrode, and the internal electrode is The external electrodes may be electrically connected via a semiconductor layer.

【0009】[0009]

【作用】絶縁性材料層が非還元性材料からなるため、外
部電極の焼付けと半導体層の形成を同時に行うことがで
きる。従って、半導体層は、外部電極の焼付けによる再
酸化や還元剤の再拡散の心配がない。
Since the insulating material layer is made of a non-reducing material, the baking of the external electrode and the formation of the semiconductor layer can be performed simultaneously. Therefore, the semiconductor layer does not have to worry about re-oxidation or re-diffusion of the reducing agent due to baking of the external electrode.

【0010】[0010]

【発明の実施の形態】以下、本発明に係る積層型コンデ
ンサ及びその製造方法の実施の形態について添付の図面
を参照して説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a multilayer capacitor according to the present invention and a method for manufacturing the same will be described below with reference to the accompanying drawings.

【0011】[第1実施形態、図1〜図4]図1に示す
ように、積層型コンデンサ1は、内部電極2,3をそれ
ぞれ表面に設けた複数の絶縁性シート4と、これらの絶
縁性シート4を積み重ねた上側及び下側に配設されたカ
バーシート5等にて構成されている。シート4,5の材
料としては、非還元性材料が使用され、本実施形態では
チタン酸バリウムを主成分とする非還元性誘電体材料を
使用した。内部電極2,3は、印刷、スパッタリング、
蒸着等の方法により絶縁性シート4上に形成されてい
る。内部電極2,3の材料としては、卑金属材料が使用
され本実施形態ではNi金属を含有する導電性材料を使
用した。
[First Embodiment, FIGS. 1 to 4] As shown in FIG. 1, a multilayer capacitor 1 includes a plurality of insulating sheets 4 having internal electrodes 2 and 3 provided on the surface thereof, respectively, And a cover sheet 5 disposed on the upper and lower sides of the stack of the functional sheets 4. As the material of the sheets 4 and 5, a non-reducing material is used. In the present embodiment, a non-reducing dielectric material containing barium titanate as a main component is used. Internal electrodes 2 and 3 are printed, sputtered,
It is formed on the insulating sheet 4 by a method such as vapor deposition. As a material for the internal electrodes 2 and 3, a base metal material is used, and in the present embodiment, a conductive material containing Ni metal is used.

【0012】内部電極2は、シート4上の左寄りの位置
に形成され、その左端部(以下、外部電極接続側端部と
する)2aとシート4の左辺4aとの間にギャップ距離
g1が確保され、かつ、右端部2bとシート4の右辺4
bとの間にギャップ距離g2が確保されている。同様
に、内部電極3はシート4上の右寄りの位置に形成さ
れ、その右端部(以下、外部電極接続側端部とする)3
aとシート4の右辺4bとの間にギャップ距離g1が確
保され、かつ、左端部3bとシート4の左辺4aとの間
にギャップ距離g2が確保されている。そして、内部電
極2と3は、シート4を間に挟んで対向し、静電容量を
形成する。
The internal electrode 2 is formed on the sheet 4 at a position closer to the left, and a gap distance g1 is secured between a left end (hereinafter, referred to as an external electrode connection side end) 2a and a left side 4a of the sheet 4. And the right end 2b and the right side 4 of the sheet 4
The gap distance g2 is ensured between the gap distance b and the gap distance b. Similarly, the internal electrode 3 is formed at a position on the right side of the sheet 4 and has a right end (hereinafter, referred to as an external electrode connection side end) 3.
a and a right side 4b of the sheet 4 are secured with a gap distance g1, and a gap distance g2 between the left end 3b and the left side 4a of the sheet 4 is secured. The internal electrodes 2 and 3 are opposed to each other with the sheet 4 interposed therebetween, and form a capacitance.

【0013】以上の絶縁性シート4とカバーシート5
は、積み重ねられた後、図2に示すように、積層体6と
される。次に、積層体6は、N2/H2/H2Oの混合ガ
スによる還元雰囲気中で焼成される。なお、焼成後の積
層体6は、通常、その後研磨されるが、内部電極2,3
と後述の外部電極22,23とが半導体層12を介して
接続されるため、この研磨工程を省略したり簡略化して
低コスト化を図ると好都合である。
The above-mentioned insulating sheet 4 and cover sheet 5
Are stacked to form a laminate 6 as shown in FIG. Next, the laminate 6 is fired in a reducing atmosphere with a mixed gas of N 2 / H 2 / H 2 O. The fired laminate 6 is usually polished thereafter, but the internal electrodes 2 and 3 are not polished.
And the external electrodes 22 and 23 to be described later are connected via the semiconductor layer 12, so that it is convenient to omit or simplify this polishing step to reduce the cost.

【0014】次に、図3に示すように、焼結された積層
体6の両端面に、還元剤10が塗布される。還元剤10
の材料としては、例えば、主成分の希土類元素にワニス
と溶剤を混練させたペーストが使用される。さらに、還
元剤10を覆うようにして、積層体6の両端部に外部電
極22,23が塗布される。これら外部電極22,23
の材料としては、Ag,Ag−Pd,Cu等の導電性ペ
ーストが使用される。
Next, as shown in FIG. 3, a reducing agent 10 is applied to both end surfaces of the sintered laminate 6. Reducing agent 10
For example, a paste in which a varnish and a solvent are kneaded with a rare earth element as a main component is used. Further, external electrodes 22 and 23 are applied to both ends of the laminate 6 so as to cover the reducing agent 10. These external electrodes 22, 23
As a material for the conductive paste, a conductive paste such as Ag, Ag-Pd, or Cu is used.

【0015】次に、この焼結積層体6を温度が800℃
の中性雰囲気中で20分間、熱処理を行なう。これによ
り、外部電極22,23が焼き付けられると共に、図4
に示すように、還元剤10が積層体6内に熱拡散して積
層体6の両端部に半導体層12を形成する。さらに、外
部電極22,23の銀喰われ防止や良好な半田付性を得
るために、外部電極22,23の表面にニッケル、銅、
半田等のようなめっき被膜を形成する。
Next, the sintered laminate 6 is heated at a temperature of 800.degree.
Heat treatment in a neutral atmosphere for 20 minutes. As a result, the external electrodes 22 and 23 are baked, and
As shown in (1), the reducing agent 10 is thermally diffused into the laminate 6 to form the semiconductor layers 12 at both ends of the laminate 6. Furthermore, in order to prevent silver erosion of the external electrodes 22 and 23 and obtain good solderability, nickel, copper,
A plating film such as solder is formed.

【0016】こうして得られた積層型コンデンサ1は、
外部電極22,23の焼付けと半導体層12の形成を同
時に行う。従って、半導体層12は、外部電極の焼付け
による再酸化や還元剤10の再拡散の心配がない。この
結果、還元剤10の拡散距離、言い換えると半導体層1
2の層厚T(図4参照)は略一定になり、内部電極2,
3と外部電極22,23との接続抵抗が低く安定すると
共に、内部電極2,3とこれに対向する半導体層12間
の絶縁抵抗の低下も抑えられる。
The multilayer capacitor 1 thus obtained is
The baking of the external electrodes 22 and 23 and the formation of the semiconductor layer 12 are performed simultaneously. Therefore, the semiconductor layer 12 does not have to worry about re-oxidation due to baking of the external electrode or re-diffusion of the reducing agent 10. As a result, the diffusion distance of the reducing agent 10, in other words, the semiconductor layer 1
2 has a substantially constant thickness T (see FIG. 4),
The connection resistance between the internal electrodes 2 and 3 and the external electrodes 22 and 23 is low and stable, and the decrease in insulation resistance between the internal electrodes 2 and 3 and the semiconductor layer 12 facing the internal electrodes 2 and 3 is also suppressed.

【0017】さらに、第1実施形態の積層型コンデンサ
1について、具体的に数値を用いてより詳細に説明す
る。
Further, the multilayer capacitor 1 of the first embodiment will be described in more detail using specific numerical values.

【0018】[評価]BaTiO3を主成分とする非
還元性誘電体シート(セラミックグリーンシート)4
と、Ni金属を含有する内部電極ペーストを準備し、周
知の積層コンデンサの製造方法に従い、図1に示すよう
な内部電極2,3をそれぞれ表面に設けた膜厚が8μm
のグリーンシート4を作成した。このグリーンシート4
を150枚積み重ねて積層体6を作成した。ここに、内
部電極2,3の外部電極接続側端部2a,3aは、積層
体6の端面に露出しないように、ギャップ距離g1を3
0μm(実施例1)、50μm(実施例2)、100μ
m(実施例3)、150μm(実施例4)、200μm
(実施例5)に設定した。一方、実施例1〜実施例5の
ギャップ距離g2は、すべて300μmに設定した。
[Evaluation] Non-reducing dielectric sheet (ceramic green sheet) 4 containing BaTiO 3 as a main component
And an internal electrode paste containing Ni metal is prepared, and the internal electrodes 2 and 3 as shown in FIG.
Green sheet 4 was prepared. This green sheet 4
Were stacked to form a laminate 6. Here, the gap distance g1 is set to 3 so that the external electrode connection side ends 2a and 3a of the internal electrodes 2 and 3 are not exposed to the end surface of the laminated body 6.
0 μm (Example 1), 50 μm (Example 2), 100 μm
m (Example 3), 150 μm (Example 4), 200 μm
(Example 5) was set. On the other hand, the gap distance g2 in Examples 1 to 5 was all set to 300 μm.

【0019】これら実施例1〜実施例5の積層型コンデ
ンサ1を前述の製造方法で製作した後、各種測定を行っ
た結果を表1に示す。表1には、比較のために、半導体
層12を形成しないで、内部電極と外部電極を直接に接
続する従来の積層型コンデンサの測定結果も併せて記載
している。なお、表1中の還元剤10の「拡散距離」
は、焼結された積層体6の端面の研磨面についてエネル
ギー分散型X線マイクロアナライザ(EDX)にて定量
分析した結果である。
After the multilayer capacitors 1 of Examples 1 to 5 were manufactured by the above-described manufacturing method, the results of various measurements are shown in Table 1. For comparison, Table 1 also shows the measurement results of a conventional multilayer capacitor in which the internal electrode and the external electrode are directly connected without forming the semiconductor layer 12. The “diffusion distance” of the reducing agent 10 in Table 1
Is the result of quantitative analysis of the polished surface of the end face of the sintered laminate 6 by an energy dispersive X-ray microanalyzer (EDX).

【0020】[0020]

【表1】 [Table 1]

【0021】表1から、実施例1〜実施例5の積層型コ
ンデンサ1は、従来の積層型コンデンサより、めっき液
による構造欠陥発生数が抑制されていることがわかる。
銀喰われや半田付け性改善のために、外部電極22,2
3の表面にニッケル、銅、半田等のようなめっき被膜を
形成する際、めっき液が外部電極22,23の微細な空
隙(ポーラス細孔)に侵入し、めっき液が内部電極とセ
ラミック素体の接合界面に達する。これにより、接合界
面の密着強度が低下し、接合界面で剥れ等が発生するこ
とがある。めっき液による構造欠陥とは、このようなめ
っき液の侵入によって発生した剥れ等をいう。
From Table 1, it can be seen that the number of occurrences of structural defects due to the plating solution in the multilayer capacitors 1 of Examples 1 to 5 is smaller than that of the conventional multilayer capacitor.
External electrodes 22 and 2 are used to improve silver erosion and solderability.
When a plating film such as nickel, copper, solder, or the like is formed on the surface of No. 3, the plating solution penetrates into fine voids (porous pores) of the external electrodes 22 and 23, and the plating solution passes through the internal electrodes and the ceramic body. Reaches the bonding interface. As a result, the adhesion strength at the bonding interface decreases, and peeling or the like may occur at the bonding interface. The structural defect caused by the plating solution refers to peeling or the like caused by the penetration of the plating solution.

【0022】また、半導体層12を介しての内部電極
2,3と外部電極22,23の接続抵抗値も、従来の内
部電極と外部電極を電気的に直接接合したときの接続抵
抗値と比較して、実用上問題はない。
The connection resistance between the internal electrodes 2 and 3 and the external electrodes 22 and 23 via the semiconductor layer 12 is also compared with the conventional connection resistance when the internal electrode and the external electrode are electrically connected directly. There is no practical problem.

【0023】ただし、内部電極2,3の焼成後のギャッ
プ距離g1が20μm未満である場合、従来の積層型コ
ンデンサと同様に構造欠陥が発生する。また、還元剤1
0の拡散距離が内部電極2,3に達しない場合、電気的
接続が得られない。従って、内部電極2,3の焼成後の
ギャップ距離g1が20μm以上になるように設定され
る。半導体層12の層厚Tは、積層体6の端面から内部
に少なくとも20μm以上に設定される。外部電極22
と内部電極2との電気的接続、及び外部電極23と内部
電極3との電気的接続を確実かつ安定して確保するため
である。
However, if the gap distance g1 after firing of the internal electrodes 2 and 3 is less than 20 μm, structural defects occur as in the conventional multilayer capacitor. Also, reducing agent 1
If the diffusion distance of 0 does not reach the internal electrodes 2 and 3, electrical connection cannot be obtained. Therefore, the gap distance g1 after firing of the internal electrodes 2 and 3 is set so as to be 20 μm or more. The layer thickness T of the semiconductor layer 12 is set to at least 20 μm or more inside from the end face of the stacked body 6. External electrode 22
This is for ensuring the electrical connection between the internal electrode 2 and the external electrode 23 and the internal electrode 3 reliably and stably.

【0024】[評価]次に、実施例6〜実施例10と
して、図1に示す内部電極2,3のギャップ距離g1を
100μm、ギャップ距離g2を300μmに設定し
て、評価1と同様にして積層体6を製作する。この積層
体6にペースト状の還元剤10と外部電極22,23用
導電性ペーストを付与した後、積層体6を温度が800
℃の中性雰囲中で、熱処理時間を15分間(実施例
6)、20分間(実施例7)、30分間(実施例8)、
40分間(実施例9)、50分間(実施例10)に設定
した。これにより、外部電極22,23が焼き付けられ
ると同時に、還元剤10が積層体6内に熱拡散して積層
体6の両端部に半導体層12を形成する。次に、これら
の実施例6〜実施例10の積層型コンデンサは、外部電
極22,23上にめっき被膜が形成される。
[Evaluation] Next, as Examples 6 to 10, the gap distance g1 of the internal electrodes 2 and 3 shown in FIG. 1 was set to 100 μm, and the gap distance g2 was set to 300 μm. The laminated body 6 is manufactured. After the paste-like reducing agent 10 and the conductive paste for the external electrodes 22 and 23 are applied to the laminate 6, the laminate 6 is heated at a temperature of 800.
In a neutral atmosphere of 15 ° C., the heat treatment time was 15 minutes (Example 6), 20 minutes (Example 7), 30 minutes (Example 8),
40 minutes (Example 9) and 50 minutes (Example 10) were set. As a result, the external electrodes 22 and 23 are baked, and at the same time, the reducing agent 10 is thermally diffused into the laminate 6 to form the semiconductor layers 12 at both ends of the laminate 6. Next, in the multilayer capacitors of Examples 6 to 10, a plating film is formed on the external electrodes 22 and 23.

【0025】表2には、こうして得られた実施例6〜実
施例10の積層型コンデンサ1の評価結果が示されてい
る。表2には、比較のため、従来の内部電極と外部電極
を直接に接続する構造の積層型コンデンサの評価結果も
併せて記載している。
Table 2 shows the evaluation results of the multilayer capacitors 1 of Examples 6 to 10 thus obtained. Table 2 also shows, for comparison, evaluation results of a conventional multilayer capacitor having a structure in which an internal electrode and an external electrode are directly connected.

【0026】[0026]

【表2】 [Table 2]

【0027】表2から、熱処理時間が30分以下の場合
には、本発明の効果が認められ、特性改善が明らかであ
る。しかし、熱処理時間が40分以上になると、還元剤
10の拡散距離が増大し、形成された半導体層に対向す
る内部電極2,3との絶縁距離が小さくなり、絶縁抵抗
の低下が認められるようになる。従って、還元剤10の
拡散距離はギャップ距離g2の2/3以内に設定するこ
とが望ましい。
From Table 2, when the heat treatment time is 30 minutes or less, the effect of the present invention is recognized, and the characteristics are clearly improved. However, when the heat treatment time is 40 minutes or longer, the diffusion distance of the reducing agent 10 increases, the insulation distance between the internal electrodes 2 and 3 facing the formed semiconductor layer decreases, and a decrease in insulation resistance is observed. become. Therefore, it is desirable that the diffusion distance of the reducing agent 10 be set within 2/3 of the gap distance g2.

【0028】なお、ここでは、熱処理時間を変化させる
ことにより、還元剤10の拡散距離を変化させたが、拡
散距離の制御は熱処理時間のみに限定されるものではな
く、高温の中性雰囲気の変更等、任意の手法を用いるこ
とが可能である。また、還元剤10の主成分である希土
類の種類は、LaないしPmのいわゆる軽希土類が望ま
しいが、Sm以降の重希土類でも熱処理条件の制御で拡
散可能である。また、希土類ペーストの仕様に関して
も、特に限定されるものではない。
Here, the diffusion distance of the reducing agent 10 is changed by changing the heat treatment time. However, the control of the diffusion distance is not limited to only the heat treatment time. Any method, such as a change, can be used. The kind of the rare earth element which is the main component of the reducing agent 10 is preferably a so-called light rare earth element of La or Pm, but heavy rare earth elements after Sm can be diffused by controlling the heat treatment conditions. Also, the specifications of the rare earth paste are not particularly limited.

【0029】[評価]次に、実施例11として、図1
に示す内部電極2,3のギャップ距離g1を200μ
m、ギャップ距離g2を300μmに設定して、評価1
と同様にして積層体6を製作する。この積層体6にペー
スト状の還元剤10と外部電極22,23用導電性ペー
ストを付与した後、積層体6を温度が800℃の中性雰
囲気中で15分間、熱処理を行う。これにより、外部電
極22,23が焼き付けされると同時に還元剤10が積
層体6内に熱拡散して積層体6の両端部に半導体層12
を形成する。
[Evaluation] Next, FIG.
The gap distance g1 between the internal electrodes 2 and 3 shown in FIG.
m, the gap distance g2 was set to 300 μm, and evaluation 1
The laminate 6 is manufactured in the same manner as described above. After applying the paste-like reducing agent 10 and the conductive paste for the external electrodes 22 and 23 to the laminate 6, the laminate 6 is subjected to a heat treatment in a neutral atmosphere at a temperature of 800 ° C. for 15 minutes. As a result, the external electrodes 22 and 23 are baked, and at the same time, the reducing agent 10 is thermally diffused into the laminate 6 and the semiconductor layer 12
To form

【0030】一方、比較例3として、図1に示す内部電
極2,3のギャップ距離g1を200μm、ギャップ距
離g2を300μmに設定して、評価1と同様にして積
層体6を製作する。次に、この積層体6にペースト状の
還元剤10を塗布した後、温度が800℃の中性雰囲気
中で15分間、熱処理を行う。これにより、還元剤10
を積層体6内に熱拡散させて積層体6の両端部に半導体
層12を形成する。その後、Cuの外部電極ペーストを
塗布し、再度、温度が800℃の中性雰囲気中で15分
間、熱処理を行なう。これにより、外部電極22,23
の焼き付けを行なった。
On the other hand, as Comparative Example 3, a laminate 6 is manufactured in the same manner as in Evaluation 1, except that the gap distance g1 of the internal electrodes 2 and 3 shown in FIG. 1 is set to 200 μm and the gap distance g2 is set to 300 μm. Next, after applying the paste-like reducing agent 10 to the laminate 6, heat treatment is performed for 15 minutes in a neutral atmosphere at a temperature of 800 ° C. Thereby, the reducing agent 10
Is thermally diffused into the laminate 6 to form the semiconductor layers 12 at both ends of the laminate 6. Thereafter, a Cu external electrode paste is applied, and heat treatment is performed again in a neutral atmosphere at a temperature of 800 ° C. for 15 minutes. Thereby, the external electrodes 22 and 23
Was baked.

【0031】次に、これらの実施例11と比較例3の積
層型コンデンサは、外部電極22,23上にめっき被膜
が形成される。表3には、こうして得られた実施例11
と比較例3の積層型コンデンサの評価結果が示されてい
る。
Next, in the multilayer capacitors of Example 11 and Comparative Example 3, plating films are formed on the external electrodes 22 and 23. Table 3 shows the results of Example 11 thus obtained.
And the evaluation results of the multilayer capacitor of Comparative Example 3 are shown.

【0032】[0032]

【表3】 [Table 3]

【0033】表3より、半導体層12の形成工程と外部
電極22,23の焼付け工程を別工程にすると、還元剤
10の拡散距離が増大、外部電極22,23と内部電極
2,3との接続抵抗等の電気特性に影響することがわか
った。すなわち、還元剤10の拡散距離は、高温の中性
雰囲気に晒される時間で決定され、熱処理を2度行なっ
た比較例3の積層型コンデンサは拡散が促進され過ぎて
いる。仮に、10分以内の短時間の熱処理を2度行なう
ことが可能であれば、半導体層12の形成と外部電極2
2,23の焼付けを別工程で実施できると考えられる。
しかしながら、10分以内の短時間の熱処理は実質的に
は不可能であり、また、工程数の増加にもなる。
As can be seen from Table 3, if the step of forming the semiconductor layer 12 and the step of baking the external electrodes 22 and 23 are separated, the diffusion distance of the reducing agent 10 is increased, and the distance between the external electrodes 22 and 23 and the internal electrodes 2 and 3 is increased. It was found that electrical characteristics such as connection resistance were affected. That is, the diffusion distance of the reducing agent 10 is determined by the time of exposure to the high-temperature neutral atmosphere, and the multilayer capacitor of Comparative Example 3 subjected to the heat treatment twice promotes the diffusion too much. If the short-time heat treatment within 10 minutes can be performed twice, the formation of the semiconductor layer 12 and the external electrode 2
It is believed that baking of 2,23 can be performed in a separate step.
However, heat treatment for a short time of 10 minutes or less is practically impossible, and also increases the number of steps.

【0034】[第2実施形態、図5〜図8]図5に示す
ように、積層型コンデンサ31は、内部電極32,33
をそれぞれ表面に設けた複数の絶縁性シート34と、こ
れらの絶縁性シート34を積み重ねた上側及び下側に配
設されたカバーシート35等にて構成されている。シー
ト34,35の材料としては、非還元性材料が使用さ
れ、本実施形態ではチタン酸バリウムを主成分とする非
還元性誘電体材料を使用した。内部電極32,33は、
印刷、スパッタリング、蒸着等の方法により絶縁性シー
ト34上に形成されている。内部電極32,33の材料
としては、卑金属材料が使用され本実施形態ではNi金
属を含有する導電性材料を使用した。
[Second Embodiment, FIGS. 5 to 8] As shown in FIG. 5, the multilayer capacitor 31 has internal electrodes 32 and 33
Are provided on the surface, and cover sheets 35 arranged on the upper and lower sides of the stack of these insulating sheets 34 and the like. As the material of the sheets 34 and 35, a non-reducing material is used. In the present embodiment, a non-reducing dielectric material containing barium titanate as a main component is used. The internal electrodes 32 and 33 are
It is formed on the insulating sheet 34 by a method such as printing, sputtering, or vapor deposition. As a material of the internal electrodes 32 and 33, a base metal material is used, and in this embodiment, a conductive material containing Ni metal is used.

【0035】内部電極32は、シート34上の左寄りの
位置に形成され、その左端部(以下、外部電極接続側端
部とする)32aはシート34の左辺34aに露出し、
かつ、右端部32bとシート34の右辺34bとの間に
ギャップ距離g2が確保されている。同様に、内部電極
33はシート34上の右寄りの位置に形成され、その右
端部(以下、外部電極接続側端部とする)33aはシー
ト34の右辺34bに露出し、かつ、左端部33bとシ
ート34の左辺34aとの間にギャップ距離g2が確保
されている。そして、内部電極32と33は、シート3
4を間に挟んで対向し、静電容量を形成する。
The internal electrode 32 is formed at a position on the left side of the sheet 34, and a left end (hereinafter, referred to as an external electrode connection side end) 32 a is exposed on a left side 34 a of the sheet 34.
Further, a gap distance g2 is secured between the right end 32b and the right side 34b of the sheet 34. Similarly, the internal electrode 33 is formed at a position on the right side of the sheet 34, and the right end (hereinafter, referred to as an external electrode connection side end) 33 a is exposed to the right side 34 b of the sheet 34, and is connected to the left end 33 b. A gap distance g2 is secured between the sheet 34 and the left side 34a. The internal electrodes 32 and 33 are
4 to face each other to form a capacitance.

【0036】以上の絶縁性シート34とカバーシート3
5は、積み重ねられた後、図6に示すように、積層体3
6とされる。次に、積層体36は、N2/H2/H2Oの
混合ガスによる還元雰囲気中で焼成される。このとき、
内部電極32,33は熱収縮して、外部電極接続側端部
32a,33aがそれぞれ積層体36の端面から内部に
距離g1引き込まれる。距離g1は、20μm以上で、
後述の半導体層42の層厚T未満に設定される(図8参
照)。この後、焼結された積層体36は、必要により湿
式バレルにより端面が研磨されるが、内部電極32,3
3は後述の半導体層42を介して外部電極52,53と
接続されるため、研磨工程を省略したり、簡略化したり
して、コストの低減を図ると好都合である。。
The above insulating sheet 34 and cover sheet 3
5, after being stacked, as shown in FIG.
6 is assumed. Next, the laminate 36 is fired in a reducing atmosphere with a mixed gas of N 2 / H 2 / H 2 O. At this time,
The internal electrodes 32 and 33 are thermally contracted, and the external electrode connection side ends 32a and 33a are respectively drawn in from the end surfaces of the laminate 36 by a distance g1. The distance g1 is 20 μm or more,
The thickness is set to be less than the layer thickness T of the semiconductor layer 42 described later (see FIG. 8). Thereafter, the end face of the sintered laminate 36 is polished by a wet barrel if necessary.
Since 3 is connected to the external electrodes 52 and 53 via the semiconductor layer 42 described later, it is convenient to omit or simplify the polishing step to reduce the cost. .

【0037】次に、図7に示すように、焼結された積層
体36の両端面に、還元剤40が塗布される。還元剤4
0の材料としては、例えば、主成分の希土類元素にワニ
スと溶剤を混練させたペーストが使用される。さらに、
還元剤40を覆うようにして、積層体6の両端部に外部
電極52,53用導電性ペーストが塗布される。次に、
この焼結積層体36を温度が800℃の中性雰囲気中で
20分間、熱処理を行なう。これにより、外部電極5
2,53が焼き付けられると共に、図8に示すように、
還元剤40が積層体36内に熱拡散して積層体36の両
端部に半導体層42を形成する。
Next, as shown in FIG. 7, a reducing agent 40 is applied to both end surfaces of the sintered laminate 36. Reducing agent 4
As the material of No. 0, for example, a paste in which a varnish and a solvent are kneaded with a rare earth element as a main component is used. further,
The conductive paste for the external electrodes 52 and 53 is applied to both ends of the laminate 6 so as to cover the reducing agent 40. next,
This sintered laminate 36 is subjected to a heat treatment in a neutral atmosphere at a temperature of 800 ° C. for 20 minutes. Thereby, the external electrode 5
2 and 53 are printed, and as shown in FIG.
The reducing agent 40 thermally diffuses into the stacked body 36 to form the semiconductor layers 42 at both ends of the stacked body 36.

【0038】こうして得られた積層型コンデンサ31
は、半導体層42を介して、内部電極32,33と外部
電極52,53とが電気的に接続される。このコンデン
サ31は、前記第1実施形態の積層型コンデンサ1と同
様の作用効果を奏する。
The multilayer capacitor 31 thus obtained
The internal electrodes 32 and 33 and the external electrodes 52 and 53 are electrically connected via the semiconductor layer 42. This capacitor 31 has the same operation and effect as the multilayer capacitor 1 of the first embodiment.

【0039】[他の実施形態]なお、本発明は、前記実
施形態に限定されるものではなく、その要旨の範囲内で
種々に変更することができる。
[Other Embodiments] The present invention is not limited to the above-described embodiment, but can be variously modified within the scope of the invention.

【0040】積層型コンデンサを製造する場合、内部電
極を表面に設けた絶縁性シート等を積み重ねた後、一体
的に焼成する工法に必ずしも限定されない。例えば、以
下に説明する工法によって積層型コンデンサを製造して
もよい。すなわち、印刷等の手段によりペースト状の絶
縁性材料にて絶縁層を形成した後、その絶縁層の表面に
ペースト状の導電性材料を塗布して内部電極を形成す
る。次にペースト状の絶縁性材料を前記内部電極の上か
ら塗布して内部電極が内蔵された絶縁層とする。同様に
して、順に重ね塗りをしながら、積層構造を有するコン
デンサが得られる。
When a multilayer capacitor is manufactured, the method is not necessarily limited to a method in which insulating sheets or the like having internal electrodes provided on the surface are stacked and then integrally fired. For example, a multilayer capacitor may be manufactured by a method described below. That is, after an insulating layer is formed from a paste-like insulating material by printing or the like, a paste-like conductive material is applied to the surface of the insulating layer to form internal electrodes. Next, a paste-like insulating material is applied from above the internal electrodes to form an insulating layer in which the internal electrodes are embedded. In the same manner, a capacitor having a laminated structure is obtained while successively coating.

【0041】[0041]

【発明の効果】以上の説明から明らかなように、本発明
によれば、外部電極の焼付けと半導体層の形成を同時に
行なうことができ、半導体層は外部電極の焼付けによる
再酸化や還元剤の再拡散の心配がない。この結果、還元
剤の拡散距離、言い換えると半導体層の層厚は略一定に
なり、内部電極と外部電極との接続抵抗が低く安定する
と共に、内部電極とこれに対向する半導体層間の絶縁抵
抗の低下も抑えられ、信頼性の高い積層型コンデンサを
得ることができる。
As is apparent from the above description, according to the present invention, the baking of the external electrode and the formation of the semiconductor layer can be performed at the same time. There is no worry about re-spread. As a result, the diffusion distance of the reducing agent, in other words, the thickness of the semiconductor layer becomes substantially constant, the connection resistance between the internal electrode and the external electrode becomes low and stable, and the insulation resistance between the internal electrode and the semiconductor layer facing the internal electrode decreases. The reduction is also suppressed, and a highly reliable multilayer capacitor can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る積層型コンデンサの第1実施形態
を示す分解斜視図。
FIG. 1 is an exploded perspective view showing a first embodiment of a multilayer capacitor according to the present invention.

【図2】図1に続く製造工程を示す一部断面斜視図。FIG. 2 is a partial cross-sectional perspective view showing a manufacturing step following FIG. 1;

【図3】図2に続く製造工程を示す一部断面斜視図。FIG. 3 is a partial cross-sectional perspective view showing a manufacturing process following FIG. 2;

【図4】図3に続く製造工程を示す一部断面斜視図。FIG. 4 is a partial cross-sectional perspective view showing a manufacturing step following FIG. 3;

【図5】本発明に係る積層型コンデンサの第2実施形態
を示す分解斜視図。
FIG. 5 is an exploded perspective view showing a second embodiment of the multilayer capacitor according to the present invention.

【図6】図5に続く製造工程を示す一部断面斜視図。FIG. 6 is a partial cross-sectional perspective view showing a manufacturing step following FIG. 5;

【図7】図6に続く製造工程を示す一部断面斜視図。FIG. 7 is a partial cross-sectional perspective view showing a manufacturing step following FIG. 6;

【図8】図7に続く製造工程を示す一部断面斜視図。FIG. 8 is a partial cross-sectional perspective view showing a manufacturing step following FIG. 7;

【符号の説明】[Explanation of symbols]

1,31…積層型コンデンサ 2,3,32,33…内部電極 4,34…絶縁性シート 5,35…カバーシート 6,36…積層体 10,40…還元剤 12,42…半導体層 22,23,52,53…外部電極 g1…ギャップ距離 1, 31 multilayer capacitor 2, 3, 32, 33 internal electrode 4, 34 insulating sheet 5, 35 cover sheet 6, 36 multilayer body 10, 40 reducing agent 12, 42 semiconductor layer 22, 23, 52, 53 ... external electrode g1 ... gap distance

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 非還元性材料からなる複数の絶縁性材料
層と卑金属材料からなる複数の内部電極とを積み重ねて
構成した積層体と、 前記積層体の端面に形成された半導体層と、 前記積層体の端部に設けられ、前記半導体層を介して前
記内部電極に電気的に接続した外部電極と、 を備えたことを特徴とする積層型コンデンサ。
A stacked body formed by stacking a plurality of insulating material layers made of a non-reducing material and a plurality of internal electrodes made of a base metal material; a semiconductor layer formed on an end face of the stacked body; An external electrode provided at an end of the multilayer body and electrically connected to the internal electrode via the semiconductor layer.
【請求項2】 非還元性材料からなる絶縁性材料層と、
卑金属材料からなる複数の内部電極とを積み重ねた後、
焼成して焼結積層体を構成する工程と、 前記焼結積層体の端面に還元剤を付与した後、該還元剤
の上に外部電極材料を付与する工程と、 前記還元剤と前記外部電極材料とを同時に熱処理し、前
記還元剤を前記焼結積層体内に拡散させて半導体層を前
記焼結積層体の端面に形成すると共に、前記外部電極材
料にて外部電極を形成する工程と、 を備えたことを特徴とする積層型コンデンサの製造方
法。
2. An insulating material layer comprising a non-reducing material,
After stacking multiple internal electrodes made of base metal material,
Baking to form a sintered laminate, applying a reducing agent to an end face of the sintered laminate, and then applying an external electrode material on the reducing agent; and the reducing agent and the external electrode Simultaneously heat-treating the material and diffusing the reducing agent into the sintered laminate to form a semiconductor layer on the end surface of the sintered laminate, and forming an external electrode with the external electrode material. A method for manufacturing a multilayer capacitor, comprising:
【請求項3】 前記内部電極の外部電極接続側端部が、
前記絶縁性材料層の縁との間に所定寸法のギャップを形
成するように、前記内部電極と前記絶縁性材料層とを積
み重ねて積層体を構成したことを特徴とする請求項2記
載の積層型コンデンサの製造方法。
3. The external electrode connection side end of the internal electrode,
3. The laminate according to claim 2, wherein the internal electrode and the insulating material layer are stacked so as to form a gap having a predetermined size between the edge of the insulating material layer. Manufacturing method of die capacitor.
【請求項4】 前記絶縁性材料層と前記内部電極とを積
み重ねた後、焼成する際に、前記内部電極の収縮によっ
て前記内部電極の端部を前記積層体の端面から引き込
み、前記内部電極が前記半導体層を介して前記外部電極
に電気的に接続するようにしたことを特徴とする請求項
2記載の積層型コンデンサの製造方法。
4. When the insulating material layer and the internal electrode are stacked and then fired, an end of the internal electrode is drawn from an end face of the laminate by shrinkage of the internal electrode when the internal electrode is fired. 3. The method for manufacturing a multilayer capacitor according to claim 2, wherein the external electrode is electrically connected to the external electrode via the semiconductor layer.
JP10242960A 1998-08-28 1998-08-28 Stacked capacitor and its manufacture Pending JP2000077259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10242960A JP2000077259A (en) 1998-08-28 1998-08-28 Stacked capacitor and its manufacture

Publications (1)

Publication Number Publication Date
JP2000077259A true JP2000077259A (en) 2000-03-14

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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010026825A1 (en) * 2008-09-04 2010-03-11 株式会社村田製作所 Stacked coil component and method for manufacturing the stacked coil component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010026825A1 (en) * 2008-09-04 2010-03-11 株式会社村田製作所 Stacked coil component and method for manufacturing the stacked coil component
JP5229323B2 (en) * 2008-09-04 2013-07-03 株式会社村田製作所 Multilayer coil component and manufacturing method thereof

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