JP2000076886A - Semiconductor apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently save a defect over consecutive two mats by storing a first information for designating one of memory mats related to a first defect, a second information for designating one of a plurality of column select lines related to the first defect and a third information for determining whether the memory mat designated by the first information is to be selected or non- selected. SOLUTION: A fuse-judging circuit FD of a mat selection signal-comparing circuit C8P0 outputs fuse judgment results FMS0-FMS2 indicating relief mat selection signals and respective complementary signals FMS0b-FMS2b. Meanwhile, a fuse-judging circuit FDt outputs a fuse judgment result FMSP indicating whether or not adjacent mats are to be saved simultaneously, fuse judgment results FMSU, FMSA indicating whether the mats are to be replaced in accordance with the comparison result, irrespective of the comparison result. The adjacent two mats can be processed as a unit, thus realizing block relief with a small number of fuses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a plurality of memory cells, and more particularly to a technique for repairing a defect by replacing a defective memory cell with a spare memory cell.

[0002]

2. Description of the Related Art High integration of semiconductor memories is progressing.
64 megabit dynamic random access
Memory (DRAM) has been mass-produced. Due to the miniaturization of elements and the increase in the number of elements accompanying the high integration, there is a problem that the yield is reduced due to defects. As a countermeasure, there is a so-called defect remedy technique in which a defective memory cell is repaired by replacing it with a spare memory cell provided in advance on a memory chip. Generally, DRAM
The number of word lines and data lines (bit lines) is increasing about twice for each generation in which the storage capacity of the memory becomes quadruple. As a DRAM defect rescue technique, a so-called column-based block remedy in which a data line divided into a plurality of memory mats is selected by a column select line and a column select line is replaced with a spare column select line in a unit of a mat is disclosed in Japanese Unexamined Patent Application Publication No. Hei. Known from 2-192100. This column-based block remedy is a powerful method because the number of defective memory cells can be replaced by a small number of spare column selection lines by reducing the replacement unit, and the probability that the replaced spare memory cell group has a failure is reduced. It is.

[0003]

In the column block repair, the replacement unit is a memory cell group selected by one column selection line for each mat. , Two replacement units must be replaced. This requires two fuse sets. Japanese Patent Application Laid-Open No. 2-192100 also discloses a technique in which some addresses are don't care, and it is possible to replace a column selection line regardless of a mat selected by the technique. Other defects cannot be repaired by the spare column selection line. Further, in a configuration of a DRAM generally used at present, a sense amplifier portion is shared by two mats (shared sense system). The sense amplifier must be laid out in accordance with the pitch of the bit lines, and has less regularity than the memory cells. Therefore, defects may increase with higher integration. Therefore, there is a demand for a method capable of efficiently relieving such defects.

[0004] That is, one of the objects of the present invention is to realize a semiconductor memory device having a defect rescue circuit that can efficiently remedy a defect extending over two consecutive mats.

[0005]

In order to achieve the above object, a typical configuration of the present invention is to provide a plurality of bit lines crossing a plurality of word lines and a plurality of memories provided at intersections of spare bit lines. A first memory mat, a second memory mat, and a third memory mat each having a cell, and the first memory mat, the second memory mat, and the third memory mat;
And a plurality of column selection lines provided corresponding to one of the plurality of bit lines of the first to third memory mats, and a plurality of column selection lines provided over the first to third memory mats, respectively.
To a spare column select line provided corresponding to a spare bit line of the third memory mat, and a defect rescue circuit coupled to the spare column select line, wherein the defect rescue circuit selects the spare column line. First information for designating one of the memory mats associated with the first defect among the first to third memory mats to be determined, and first information associated with the first defect among the plurality of column selection lines Second information for designating one of the plurality of column selection lines,
There is provided an area for storing third information for determining selection or non-selection of a memory mat adjacent to the memory mat specified by the first information in association with a defect.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. Although the circuit elements constituting each block of the embodiment are not particularly limited, they are formed on one semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as CMOS (complementary MOS transistor).
The circuit symbol of MOSFET is N-type without arrow.
P-type MO with OSFET (NMOS) and arrows
It is distinguished from SFET (PMOS).

<Embodiment 1> An embodiment relating to column block repair of a synchronous DRAM (SDRAM) according to the present invention will be described with reference to FIGS. First, SD
The configuration of the entire RAM will be described. Figure 2 shows the SDRAM
It is a principal part block diagram of. The indirect peripheral circuit of the SDRAM includes a clock buffer CLKB, a control signal buffer CB, a command decoder CD, an address buffer AB, a column address counter YCT, a row address predecoder XPD, a column address predecoder YPD, an input buffer DIB, and an output buffer DOB. . Further, a row-related defect rescue circuit XR, a row address driver XD, a column-related defect rescue circuit YR, a row address driver YD, a write buffer WB, a main amplifier MA, and the like are provided corresponding to the memory array MAR. The sectors SCT0 and SCT1 of these memory cores correspond to the number of memory arrays according to the specifications such as the memory capacity and the number of banks.
Here, only two are shown for simplicity.

Each circuit block plays the following role. The clock buffer CLKB distributes the external clock CLK as an internal clock CLKI to the command decoder CD and the like. The command decoder CD receives an external control signal CMD.
Generates a control signal for controlling the address buffer AB, the column address counter YCT, the input buffer DIB, the output buffer DOB, and the like. The address buffer AB takes in the external address ADR at a desired timing according to the external clock CLK, and sends the row address BX to the row address predecoder XPD. Row address predecoder X
The PD predecodes the row address BX and distributes the row predecode address CX to the sectors SCT0 and SCT1. The address buffer AB also sends the column address BY to the column address counter YCT. Column address counter YCT
Generates a column address for performing a burst operation using the column address BY as an initial value, predecodes the column address by a column address predecoder YPD, and distributes a column predecode address CY to the sectors SCT0 and SCT1. The input buffer DIB takes in the data of the input / output data DQ with the external device at a desired timing and outputs the write data GI.
On the other hand, the output buffer DOB outputs the read data GO to the input / output data DQ at a desired timing.

In the sector SCT0 or SCT1, the row-related defect rescue circuit XR applies the row predecode address CX
The presence / absence of the replacement is determined, and the row-related relief determination result RXH is output to the row address driver XD. Row address driver XD
Receives the row predecode address CX and the row-related repair determination result RXH, and outputs a desired mat select signal MS and a row address signal DX to the memory array MAR. On the other hand, the column-related defect relief circuit YR uses the column predecode address CY
And the presence or absence of replacement for the mat selection signal MS,
The column-based rescue judgment result RYH is used as the column address driver YD.
Output to The column address driver YD receives the column predecode address CY and the column-based rescue determination result RYH, and outputs a desired column address signal DY to the memory array MAR.
Output to The write buffer WB outputs the write data GI to the main input / output line MIO. Meanwhile, the main amplifier MA
Amplifies the signal of the main input / output line MIO and sets the read data G
Outputs O.

FIG. 3 shows an example of the timing of the read operation in the SDRAM configuration example shown in FIG. The operation of the SDRAM of FIG. 2 will be described with reference to this timing chart. At each rising edge of the external clock CLK, the command decoder CD determines the control signal CMD and, when the activate command A is given, fetches the row address X from the address ADR into the address buffer AB, and the row address predecoder XPD Outputs decode address CX. In response to this, a desired mat select signal MS and a row address signal DX are output in the sector SCT0 or SCT1, and a word line WL described later is selected in the memory array MAR. When a read command R is given to the control signal CMD, the column address Y is fetched from the address ADR into the address buffer AB, and the column address counter YC
T operates every clock cycle, and the column address predecoder YPD outputs a column predecode address CY corresponding to the burst operation. Within sector SCT0 or SCT1, mat select signal MS and column predecode address CY
In response, the column-related defect repair circuit YR operates, and a column address signal DY or a redundant column address signal RDY is output according to the result, and a column select line YS or a redundant column select line shown later in the memory array MAR. RYS is selected. As a result, a signal is read to the main input / output line MIO, the main amplifier MA outputs read data GO, and the output buffer DOB outputs data to the input / output data DQ at a timing according to the external clock CLK.

As described above, in the SDRAM, the column address Y is fetched a desired number of clock cycles after fetching the row address X. This is to reduce the number of address pins, and takes advantage of the fact that taking a column address after the row address does not affect the access time because the column operation is performed after the row operation is completed in the memory core. ing. Therefore, there is a time margin from when the mat select signal MS and the row address signal DX used for the row operation are output to when the column address signal DY is used for the column operation. As will be described later, in the present embodiment, this time allowance is used so that the delay due to the repair determination does not affect the access time.

FIG. 4 shows an example of the configuration of the column defect repair determination circuit YR in FIG. That is, as shown in FIG. 9 later, one memory bank (an aggregate of a plurality of memory mats)
, Four comparison determination circuits RYC40 to RYC43 are provided corresponding to four spare column selection lines (preliminary YS lines), and output comparison determination results RDY0 to RDY3, respectively. The four-input OR circuit OR4 calculates the logical sum of these comparison determination results RDY0 to RDY3, and outputs a column-based repair determination result RYH for controlling the operation of the normal column decoder. Comparison judgment circuit R
YC40 to RYC43 are mat selection signal comparison circuits C8P0 to C8P3 and mat selection signal comparison circuits C8, respectively, for comparing a rescue mat address (usually the upper bits of a column address).
The relief column address RC is determined by the outputs RM40 to RM43 of P0 to C8P3.
An address selection circuit CYS4 for selecting Y and an address comparison circuit CYCP for comparing the relief column address RCY with the column predecode address CY are provided.

This defect rescue circuit has a configuration corresponding to four spare column selection lines provided over eight memory mats. In order to make it possible to cope with four defects with one spare column selection line, C8P0 to C8P3 have areas for storing information (row-related repair addresses) of four memory mats related to the defect. Also, information on the column selection line (column repair address) related to the defect is stored in CYS4.
An area for storing the data is included. More specific configurations of these circuits are shown below.

FIG. 1 is a circuit diagram showing a mat selection signal comparison circuit shown in FIG.
4 shows a configuration example of C8P0. Six fuse judgment circuits FD
Alternatively, FDt and NMOS transistor groups MNIP8 and MNC8
And NMOS transistors MNU, MNA0, MNA1 and a level holding inverter LCI. Three fuse judgment circuits FD
Are fuse determination results FMS0 to FMS2 indicating the relief mat selection signal in binary, and their complementary signals FMS0b to FMS0
Outputs MS2b. On the other hand, the three fuse determination circuits FDt each have a fuse determination result FMSP indicating whether or not to repair adjacent mats at the same time, a fuse determination result FMSU indicating whether or not to perform replacement in accordance with the comparison result of the relief mats, A fuse determination result FMSA indicating whether to perform replacement regardless of the result of comparison of the relief mat is output. NMOS transistor group MN
IP8 is a 1 whose gate is connected to mat select signals MS0-MS7.
It consists of five NMOS transistors and seven NMOS transistors whose gates are connected to the fuse determination result FMSP. On the other hand, the NMOS transistor group MNC8 includes 14 NMOS transistors whose gates are connected to the fuse determination results FMS0 to FMS2 and FMS0b to FMS2b. The level holding inverter LCI includes a reset PMOS transistor MP
0, feedback PMOS transistor MP1, CMOS inverter
It is composed of INV0.

The mat selection signal comparison circuit C8P0 operates as follows. When performing a row operation, the reset signal RSTb is set to a high level, and the level holding inverter LCI
Turn off the PMOS transistor inside. Here, in the level holding inverter LCI, when a current path is formed between the input terminal and the ground, the input terminal goes low and the output RM40 goes high. Otherwise, the input is kept at the high level by the feedback PMOS transistor MP1 and keeps outputting the low level. The reason why the level holding inverter is used is to prevent erroneous determination due to noise or the like. Here, any one of the mat selection signals MS0 to MS7 becomes a high level from a state of a low level. Whether or not a current path is formed between the input terminal of the level holding inverter LCI and the ground is classified according to the result of the fuse determination as follows. First, FM
If SU and FMSA are low level, no current path is formed no matter which mat select signal is high level,
RM40 keeps low level. This is the case where no replacement is performed. If FMSU is at a high level and FMSP and FMSA are at a low level, a current path is formed for any of MS0 to MS7 according to FMS0 to FMS2 and FMS0b to FMS2b. For example, if FMS0 to FMS2 are low and FMS0b to FMS2b are high, a current path is formed when MS0 goes high, RM40 goes high, and RM40 remains high even if other mat select signals go high. Keep low level. This is a case where block relief is performed using one mat as a unit. FMSU and FMSP are high level, FM
If SA is at low level, FMS0 to FMS2 and FMS0b to FMS2b
, A current path is formed with respect to any two consecutive ones of MS0 to MS7. For example, if FMS0 to FMS2 are low and FMS0b to FMS2b are high, when MS0 or MS1 goes high, a current path is formed and RMS
Even if M40 becomes high level and other mat select signals become high level, RM40 keeps low level. This is a case where block repair is performed for two adjacent mats as a unit. If FMSA is high level, reset signal RSTb
Only goes to a high level, and the RM 40 goes to a high level regardless of which of MS0 to MS7 goes to a high level. This is a case where the column selection line is replaced regardless of the mat.

As described above, according to the fuse determination result FMSP,
Two adjacent mats can be used as a unit, and efficient block relief can be realized with a small number of fuses. Here, the mat select signal comparison circuit is configured with a small number of elements by using NMOS pass transistor logic. The level holding inverter LCI makes use of the fact that it outputs a low level when the input is open,
The pass transistor transmitting 0 is omitted, and the number of elements is reduced. Furthermore, two NMOs are provided by a wired OR.
Just by adding an S transistor, the mat select signal MS0
Regardless of ~ MS7, a function to set one of the comparison results to high level is added. Thereby, it is possible to cope with a defect such as disconnection of the column selection line. Although a large number of NMOS pass transistors serve as a signal path, the delay time does not matter because this circuit can prevent a critical path of access time.

The mat selection signal comparison circuits C8P1 to C8 in FIG.
P3 is also realized in the same manner as the mat selection signal comparison circuit C8P0 shown in FIG. However, since it is sufficient to determine whether or not to replace the column selection line for each redundant column selection line regardless of the mat selection signal, the mat selection signal comparison circuits C8P1 to C8
In P0, the fuse determination circuit FDt that generates the fuse determination result FMSA and the NMOS transistors MNA0 and MNA1 are unnecessary. By removing these, the number of elements can be further reduced.

FIG. 5 shows a configuration example of the fuse determination circuit FD in FIG. This fuse determination circuit
FUSE, NMOS transistor MN0, PMOS transistors MP0 and MP1, and CMOS inverter INV0. The fuse FUSE can be realized by a wiring layer or the like, and is selectively cut by a laser or the like. PMOS transistor
MP0, MP1, and the CMOS inverter INV0 function similarly to the level holding inverter in FIG.

This fuse determination circuit operates as follows. While the enable signal FE is low level, the NMOS
The transistor MN0 is turned off, the PMOS transistor MP0 is turned on, and the output FO is at a high level and FOb is at a low level regardless of the state of the fuse FUSE. When the enable signal FE becomes high level, the NMOS transistor
MN0 turns on and PMOS transistor MP0 turns off. If the fuse FUSE is not disconnected, the judgment result FO
Is low level and FOb is high level. On the other hand, when the fuse FUSE is cut, the PMOS transistor MP
The judgment result FO is kept at low level by 1 and the FOb is kept at high level by the inverter INV0.

In this fuse determination circuit, complementary outputs are obtained by using the CMOS inverter INV0 necessary to make the output full amplitude. Therefore, it is suitable for a configuration using complementary fuse determination results as shown in FIG. When only the determination result of the positive output is required, such as FDt in FIG. 1, only the output FO may be used.

FIG. 6 shows a configuration example of the address selection circuit CYS4. It has 28 fuse decision circuits FDt, and stores four sets of binary encoded relief column addresses. FAY00 ~ FAY60, FAY01 ~ FAY61, FAY02 ~ FAY
62, FAY03 to FAY63 are each one set. When any one of the outputs RM40 to RM43 of the mat select signal comparison circuits C8P0 to C8P3 becomes high level, the relief column addresses RCY20 to RCY2 corresponding to the column predecode address CY
7, RCY40 to RCY43 and RCY60 to RCY63 are output. The configuration consists of seven logic circuits AOR4 and a four-input OR circuit ORM4,
It comprises eight 4-input AND circuits AND4 each comprising a 4-input NAND gate and an inverter, and eight 3-input AND circuits AND3 each comprising a 3-input NAND gate and an inverter. Within the logic circuit AOR4, outputs RM40 to RM of the mat selection signal comparison circuit
An NMOS transistor whose one of 43 is connected to the gate and an NMOS transistor connected to one of the gates of the determination result of the fuse circuit are connected in series, and four of them are connected in parallel to the level holding inverter LCI. . The level holding inverter LCI can be configured as shown in FIG. Thus, for example, RM40 and FAY00, RM41
And the logical product of FAY01, RM42 and FAY02, and the logical product of RM43 and FAY03 are obtained at the output RBY0. Further, a complementary signal, for example, RBY0b is output by the CMOS inverter.
Thus, complementary binary relief column addresses RBY0 and RBY0b to RBY0 corresponding to column address BY in FIG.
6 and RBY6b are obtained. On the other hand, in the 4-input OR circuit ORM4, four NMOS transistors each having one of the outputs RM40 to RM43 of the address shifter connected to the gate are connected in parallel to the level holding inverter LCI, and the logical sum of RM40 to RM43 is output. Obtained by RMA. The RMA indicates whether or not there is a column address to be replaced for the input mat select signal MS. The AND circuits AND4 and AND3 take the logical product of this RMA and the desired combinations of the rescue column addresses RBY0 and RBY0b to RBY6b and RBY6b, so that the rescue column addresses RCY20 to RCY20 to RCY27, RCY40 to RCY43, and RCY60 to RCY63 are obtained. If there is no column address to be replaced with respect to the input mat select signal MS, these RCY20 to RCY2
7, RCY40 to RCY43 and RCY60 to RCY63 are all low level.

As described above, the judgment results FAY00 to FAY60, FAY01 to FAY61, FAY02 to FAY62, and FAY of the binary fuse circuit are obtained.
After the selection of Y03 to FAY63, predecoding is performed to generate a relief column address corresponding to the column predecode address, thereby reducing the circuit scale, occupying area and power consumption.

FIG. 7 shows a configuration example of the address comparison circuit CYCP for the relief column address in FIG. Inverter SINV with 16 switches, 3 PMOS transistors M
PA0, three CMOS inverters INV1, and a three-input AND circuit AND5. Inverter SINV with switch is CM
OS inverter INV4, INV5 and PMOS transistor MPSW
And an NMOS transistor MNSW. For example, an inverter SI with a switch to which a rescue column address RCY20 and a column predecode address CY20 are input.
In NV, when RCY20 is at a high level, the PMOS transistor MPSW and the NMOS transistor MNSW are turned on,
CY20 is inverted and output. On the other hand, when RCY20 is at the low level, the PMOS transistor MPSW and the NMOS transistor MNSW are turned off, and the output of SINV becomes high impedance. By inputting a plurality of outputs of the inverter SINV with the switch to the CMOS inverter INV1,
RCY20 and CY20,…, logical OR of RCY27 and CY27, RCY40 and CY40,…, logical OR of RCY43 and CY43, RCY60 and CY60,…, logical AND of RCY63 and CY63 Is obtained, and the logical product of these is obtained by a three-input AND circuit AND5, whereby a comparison result RDYi is output. The comparison result RDYi is a comparison result RDY0 to RDY3 output from each of the four comparison determination circuits RYC40 to RYC43. here,
The three PMOS transistors MPA0 have no column addresses to replace, and RCY20 to RCY27, RCY40 to RCY43, RCY60 to R
CMOS inverter when CY63 is all low level
The floating of the input of INV1 is prevented by setting RMA to low level as shown in FIG. 4, and RDYi is set to low level.

This circuit has a column predecode address
It operates after CY is input, and becomes a critical path that determines the access time from the read command R shown in FIG. Therefore, the delay time is reduced by using a CMOS circuit.

In order to explain the role of the column defect repair determination circuit YR specifically described above, the configuration of the circuit blocks in FIG. 2 related to the column operation will be specifically described below.

FIG. 8 shows a column address driver in FIG.
13 shows a configuration example of YD. As described above, the column address driver YD supplies the column address signals DY20 to DY27, DY40 to DY43, DY40 to DY43 to the column decoder in the memory array MAR of FIG.
Supply DY60 to DY63. The column-based defect remedy judgment circuit RYH by the column-based defect remedy judgment circuit is used as a CMOS inverter I
Received by NVH, its output and column predecode address C
The logical product of Y20 to CY27, CY40 to CY43, and CY60 to CY63 is N
2-input AN composed of AND gate and inverter
With the D circuit AND0, the column address signals DY20 to DY27,
DY40 to DY43 and DY60 to DY63 are output. That is, the column address signal outputs a low level if the column-related defect remedy determination result RYH is at a high level, and outputs the same value as the column predecode address if RYH is at a low level. This circuit stops the operation of the normal column selection line when replacing the normal column selection line with the redundant column selection line.

FIG. 9 shows an example of the configuration of the memory array MAR in FIG. Here, the memory cell array in which the memory cells are arranged in a matrix form corresponds to mats MCA0 to MCA7.
It is divided into pieces. Sense amplifiers SAB0 to SAB8 are provided on both sides of each mat. Also, mat MCA0 ~
Row decoders XDEC0 to XDEC7 correspond to MCA7, and sense amplifier control circuits SAC0 correspond to sense amplifiers SAB0 to SAB8.
~ SAC8 are provided. Here, the column decoder YDEC
Are common to the divided mats MCA0 to MCA7, and include 512 column selection lines YS0 to YS511 and four redundant column selection lines R
YS0 to RYS3 are selectively driven. The column defect repair circuit YR shown in FIGS. 4 to 7 and the column address driver YD shown in FIG. 8 correspond to such numbers of column select lines and redundant column select lines. For example, in FIG. 4, the number of comparison determination results is four because RDY0,.
This is because it corresponds to YS0,…, RYS3 on a one-to-one basis.

FIG. 10 shows a configuration example of the column decoder YDEC in FIG. For decoding for selecting the column selection lines YS0 to YS511, a large number of 2-input AND circuits AND1 and AND2 each including a NAND gate and an inverter are provided. Column address signals DY20 to DY27 predecoded with 3 bits of column address and column address signals DY40 to DY43, DY predecoded with 2 bits at a time
60 to DY63 are input. First, DY is obtained by AND circuit AND1.
The logical product of any of 60 to DY63 and any of DY40 to DY43 is taken, and further, AND circuit AND2 and AND circuit AND1
And the logical product of any of DY20 to DY27, 7-bit decoding is performed, and a desired one of 512 column selection lines YS0 to YS511 can be selected. Also, an inverter is required to drive the redundant column selection lines RYS0 to RYS3.
A buffer circuit BUF2 connected in two stages is also provided.

FIG. 11 shows a configuration example of the sense amplifier section SAB1 and the mat MCA1 in FIG. The mat MCA1 has a memory cell MC at the intersection of one of the bit line pairs BL0t and BL0b, BL0t and BL0b,... And the word line WL0, WL1,.
Are arranged in a well-known folded bit line configuration. The memory cell MC is a one-transistor, one-capacitor memory cell including one NMOS transistor and one storage capacitor. The sense amplifier section SAB1 has two mats MCA0
And shared gate SHL0, SH
L1, ... and SHR0, SHR1, ..., precharge circuits PC0, PC
1,…, sense amplifiers SA0, SA1,…, input / output gates IOG0,
It consists of IOG1,…. Precharge circuit PC0, PC
1,... Precharge the bit line pairs in the mats MCA0, MCA1 on both sides to the precharge voltage HVC. Shared gates SHL0, SHL1,… and SHR0, SHR1,… are mat MCA0,
The bit line pair in one of the MCA1 is connected to the sense amplifier, and the bit line pair in the other is separated. By selectively driving one of the word lines in the mat connected to the sense amplifier unit, a signal is read from the memory cell MC to each bit line pair BL0t and BL0b, BL0t and BL0b,.
Are amplified by the sense amplifiers SA0, SA1,. The input / output gates IOG0, IOG1,... Are selected by the column selection lines YS0, YS1,.
0b, connect to IO1t and IO1b. Here, an example is shown in which column selection lines are arranged for every two sense amplifiers in the sense amplifier section, that is, for every four pairs of bit lines in the mat. By replacing this column selection line with a redundant column selection line, it is possible to replace a sense amplifier that exchanges data from the input / output lines IO0t and IO0b and IO1t and IO1b, and to replace a defective memory cell with a redundant memory cell to rescue the memory. .

FIG. 12 shows an example of replacement of the column selection lines in the configuration described above. By replacing the column selection line with a redundant column selection line, the bit line of each mat is replaced with a redundant bit line, and the defective memory cell group is replaced with a redundant memory cell group. The hatched area with a diagonally upward slant pattern is replaced with a hatched area with a lattice pattern. In this example, the fuse determination result FMSA is set to 1 in the mat selection signal comparison circuit C8P0 of the comparison determination circuit RYC43, and the column selection line is replaced with the redundant column selection line RYS3 regardless of the mat selection signal. The other redundant column selection lines RYS0 to RYS2 replace the column selection lines at four locations for each of the eight mats. However, the case where one mat is used as a unit and the case where two continuous mats are used as a unit are mixed. For example, in the redundant column selection line RYS0, the mats MCA1 and MCA2 are commonly replaced. This allows
One fuse set can cope with a defect in the sense amplifier shared by two mats. As described above, the column-based rescue method of the present embodiment enables flexible rescue. That is, a small number of fuses causes a small increase in the chip area, a small number of blown blows reduces the cost required for blowing, a high relief efficiency leads to a high yield,
AM manufacturing costs can be reduced.

Here, the description has been made while showing specific numerical values such as two redundant column selection lines for 128 column selection lines, but it is needless to say that the present invention is also effective for other numbers. The configuration shown is such that one mat can be extended to two mats as a basic unit for block relief, but the same applies to a case where two or more mats, such as two mats, are used as the basic unit and multiple expansions are performed. Discussions hold. Also, SD
Although the RAM has been described as an example, the present embodiment relates to relieving defects of a memory array, and similar effects can be obtained with other DRAMs such as a high-speed page mode. Furthermore, DR
It can be applied to memories other than AM. The same applies to the following embodiments.

<Embodiment 2> Next, FIG. 13 shows another configuration example of the mat selection signal comparison circuit which is a main part of the block rescue judging circuit according to the present invention, which is a modification of the circuit of FIG. The feature is that the number of NMOS transistors that are connected in series and serve as a signal path is small. It realizes the same function as the mat selection signal comparison circuit shown in FIG. 1, and can be used as the mat selection signal comparison circuit C8P0 in FIG. This circuit consists of six fuse decision circuits FD and FDt, NMOS transistor groups MNUP8 and MNC8, and NMOS transistor M
It consists of NA0, MNA1, and a level holding inverter LCI. The three fuse determination circuits FD respectively output fuse determination results FMS0 to FMS2 indicating the relief mat selection signal in binary, and complementary signals FMS0b to FMS2b thereof. On the other hand, the three fuse determination circuits FDt each have a fuse determination result FMSP indicating whether to relieve adjacent mats at the same time, and a fuse determination result FMSU indicating whether to perform replacement in accordance with the comparison result of the relief mats, A fuse determination result FMSA indicating whether to perform replacement regardless of the result of comparison of the relief mat is output. N
The MOS transistor group MNUP8 has a configuration in which eight NMOS transistors whose gates are connected to the fuse determination result FMSU are added to the NMOS transistor group MNIP8 in FIG. 1, and includes a total of thirty NMOS transistors. On the other hand, the NMOS transistor group MNC8 has the same configuration as in FIG. The level holding inverter LCI is also configured as shown in FIG.

This mat select signal comparison circuit operates in the same manner as the circuit of FIG. That is, when performing the row-related operation, the level holding inverter LCI is activated. When a current path is formed between the input terminal and the ground according to the mat selection signal according to the fuse determination result, the output is
RM40 goes high. Otherwise, keep outputting low level. Even in this circuit, the fuse judgment result FMSP
Accordingly, two adjacent mats can be used as a unit, and efficient block relief can be realized with a small number of fuses.

In this circuit, the level holding inverter LCI
NMOS connected in series between input terminal and ground
The maximum number of transistors is five. In the mat selection signal comparison circuit shown in FIG. 1 that realizes the same function, the maximum number is six, and this circuit is smaller. Thereby, it is easy to realize a stable operation.

The mat selection signal comparison circuits C8P1 to C8 in FIG.
P3 is also realized in the same manner as the mat selection signal comparison circuit C8P0 shown in FIG. However, the mat selection signal comparison circuit C8P1
In C8P0, the fuse determination circuit FDt that generates the fuse determination result FMSA and the NMOS transistors MNA0 and MNA1 are unnecessary. By removing these, the number of elements can be reduced.

<Embodiment 3> Next, a modification of the fuse circuit will be described. FIG. 14 shows an example of the configuration of a fuse circuit sharing a PMOS transistor, and a plurality of fuse determination circuits FD or FDt in FIG. 1 can be used. In this circuit, a PMOS transistor MPC is connected to a node CSP common to a plurality of fuse circuit cells FCN.
Is provided. The fuse circuit cell is a fuse FUS
E, NMOS transistors MN4 and MN5, and CMOS inverter INV2.

This fuse circuit operates as follows. While the enable signal FEb is at the high level, the PMOS transistor MPC is turned off, and N is set in each fuse circuit cell FCN.
MOS transistor MN4 is on and fuse FUSE
FO0, FO1,… are high level, FO0
b, FO1b,… are at low level. When the enable signal FEb goes low, the PMOS transistor MPC
Is turned on, the node CSP goes high, and the NMOS transistor MN4 in each fuse circuit cell FCN is turned off. If the fuse FUSE is not cut, the result of the determination is inverted. On the other hand, when the fuse FUSE is cut, the same state is maintained by the NMOS transistor MN5.

In this fuse circuit, by sharing the PMOS transistor MPC with a plurality of fuse circuit cells FCN, the number of elements can be reduced as compared with the case where the fuse circuit is configured by the fuse determination circuit shown in FIG. Similar to the fuse determination circuit of FIG. 5, a complementary output is obtained using the CMOS inverter INV2 necessary to make the output full amplitude, and the complementary fuse determination result as shown in FIG. 1 is used. Suitable for configuration. In the fuse determination circuit shown in FIG. 5, the fuse FUSE is provided on the NMOS transistor side for the determination result output. On the other hand, in the fuse circuit cell FCN, the fuse FUSE is provided on the PMOS transistor side. You can also

<Embodiment 4> FIG. 15 shows an antifuse determining circuit. Such an antifuse determination circuit is described in, for example, US Pat. No. 5,631,862 (US Pat.
P5, 631, 862). This circuit can also be used as the fuse determination circuit FD or FDt in FIG. This anti-fuse determination circuit uses an anti-fuse
AFUSE, NMOS transistors MN6 and MN7, PMOS transistors MP3, MP4 and MP5, and a CMOS inverter INV3. The fuse AFUSE can be realized by a capacitor having the same insulating film as the storage capacity of the memory cell. While the fuse blows the conductive layer with a laser or the like,
The antifuse electrically blows the insulating film. For this reason, on the contrary to the fuse, conduction occurs by blowing in an open state during manufacture. Selectively disconnected.

When blowing the antifuse, the enable signal FE is set to high level, the PMOS transistor MP3 is turned off, the NMOS transistor MN6 is turned on, and a high voltage higher than the power supply voltage VCC is applied to the control signal CGND. Then, the blow control signal BLOW is set to the high level to turn on the NMOS transistor MN7. The output node FOb goes low, the output node FO goes high due to the inverter INV3, and the PMOS transistor MP
4 turns off. As a result, a high voltage is applied to the antifuse AFUSE, and the insulating film is broken to conduct.

In determining the antifuse, the enable signal FE is set to the low level, the output FOb is set to the high level, and the FO is set to the low level. When the enable signal FE becomes high level, the NMOS transistor MN6 turns on and the PMOS transistor MP3 turns off. When the antifuse AFUSE is blown, a current flows through the antifuse AFUSE and the PMOS transistor MP5
As a result, the load resistance becomes a large value, the determination result FO becomes high level, and FOb becomes low level. On the other hand, when the antifuse AFUSE is not blown, the determination result FO is kept at the low level by the PMOS transistor MP4, and FOb
Keep high level by inverter INV0.

By using an antifuse formed of a capacitor instead of a fuse, it is possible to electrically blow, so that there is no need to provide an opening for blowing with a laser, and the manufacturing process can be simplified. Further, in some cases, there is also an effect that it is possible to blow even after assembling into a package. However, such an antifuse determination circuit has a larger number of elements than a normal fuse determination circuit, and the transistors MN6 and MN7 serving as current paths during blowing have sufficiently low resistance, and a transistor MP5 that determines the load resistance at the time of determination. Since the transistor dimensions must be determined so that the resistance becomes sufficiently high, the area becomes large. The block remedy method of the present invention is suitable because efficient defect remedy can be realized with a small number of fuses and the problem of the area of the antifuse determination circuit can be reduced.

<Embodiment 5> Referring to FIG. 16 to FIG.
Another embodiment of the column block repair will be described. This embodiment is characterized in that a logical sum of mat selection signals of two mats is obtained in advance. SDRA shown in FIG.
The entire configuration of M, the column address driver YD of FIG. 8, and the configuration of the memory array MAR shown in FIGS.
From the method described with reference to FIG.

FIG. 16 shows another example of the configuration of the column-based rescue judging circuit. Like the rescue judging circuit shown in FIG.
Used as YR. The OR circuit MSP8 of the mat select signal outputs the mat select signals MSEP and MSOP obtained by taking the logical sum, and MEP is output to the comparison decision circuits RYC20 and RYC21, and MSOP is output to the RYC22 and RYC23.
Is entered. The comparison judgment circuits RYC20 to RYC23 output the comparison judgment results RDY0 to RDY3, respectively, and output the column-based rescue judgment result RYH by the 4-input OR circuit OR4. The comparison determination circuits RYC20 to RYC23 are mat selection signal comparison circuits C40 and C41 for comparing relief mat addresses, respectively, and an address selection circuit for selecting a relief column address RCY based on outputs RM20 and RM21 of the mat selection signal comparison circuits C40 and C41. CYS2 comprises an address comparison circuit CYCP for comparing the relief column address RCY with the column predecode address CY. The address comparison circuit CYCP is configured as shown in FIG. More specific configurations of other circuits are shown below.

FIG. 17 shows a configuration example of the OR circuit MSP8. Eight each consisting of a 2-input OR gate and an inverter
It is composed of a two-input OR circuit OR2. For the eight mat select signals MS (MS0 to MS7), the two-input OR circuit OR2 takes the logical sum of the mat select signals of two adjacent mats. In FIG. 16, among these outputs, MS01, MS2
3, MS45, MS67 for MSEP, MS12, MS34, MS56, MS70 for MSOP
As shown.

FIG. 18 shows a configuration example of the mat selection signal comparison circuit C40. Four fuse decision circuits FD or FDt, NMOS transistor groups MNI4 and MNC4, and N
It comprises MOS transistors MNU, MNA0, MNA1 and a level holding inverter LCI. Each of the two fuse determination circuits FD outputs a fuse determination result FMS0, FMS1 indicating a relief mat selection signal in binary, and complementary signals FMS0b, FMS1b thereof. On the other hand, the two fuse determination circuits FDt each have a fuse determination result FMSU indicating whether or not to perform replacement in accordance with the comparison result of the relief mat, and a fuse indicating whether or not to perform replacement regardless of the comparison result of the relief mat. Outputs the judgment result FMSA. The NMOS transistor group MNIP8 includes four NMOS transistors connected to mat selection signals MS01, MS23, MS45, and MS67 whose gates are ORed. On the other hand, the NMOS transistor group MNC4 includes six NMOS transistors whose gates are connected to the fuse determination results FMS0 and FMS1 and FMS0b and FMS1b. The level holding inverter LCI is configured as shown in FIG.

The mat selection signal comparison circuit C40 is the same as that shown in FIG.
As in the circuit shown in (1), the output is determined based on whether or not a current path is formed between the input terminal of the level holding inverter LCI and the ground. First, if FMSU and FMSA are low level, RM20 keeps low level. This is the case where no replacement is performed. FMSU is high level and FMSA
Is low level, any one of MS01, MS23, MS45, MS67 according to FMS0, FMS1 and FMS0b, FMS1b,
A current path is formed. That is, when the two fuse determination circuits FD match the addresses stored in binary, the RM20 goes high. For example, FMS0, FMS1
Is low and FMS0b and FMS1b are high, MS01
Becomes high level, a current path is formed and RM20 becomes high level, and RM20 keeps low level even if other mat selection signals become high level. If FMSA is at a high level, RM20 is at a high level regardless of which of MS0 to MS7 is at a high level. This is a case where the column selection line is replaced regardless of the mat.

The mat selection signal comparison circuit C41 in FIG.
This is also realized in the same manner as the mat selection signal comparison circuit C40 shown in FIG. However, MS12, MS34, MS56 and MS70 are input instead of MS01, MS23, MS45 and MS67. Further, the fuse determination circuit FDt that generates the fuse determination result FMSA and the NMOS transistors MNA0 and MNA1 are unnecessary.

FIG. 19 shows a configuration example of the address selection circuit CYS2. The address selection circuit CYS4 shown in FIG.
While this circuit selects one set from the set of relief column addresses, this circuit selects one set from two sets. Two sets of the relief column addresses encoded in binary by the 14 fuse determination circuits FDt are stored, and the outputs RM20 and RM21 of the mat selection signal comparison circuits C40 and C43 are stored.
, The relief column addresses RCY20 to RCY27, RCY40 to R
Outputs CY43, RCY60 to RCY63. The composition is CM
7 logic circuits AOR consisting of OS composite gate and inverter
2-input O consisting of 2- and 2-input NOR gate and inverter
It comprises an R circuit ORM2, eight 4-input AND circuits AND4 and eight 3-input AND circuits AND3. In the logic circuit AOR2, complementary binary relief column addresses RBY0 and RBY0b to RBY6 and RBY6b corresponding to the column address BY in FIG. 2 are obtained. For example, the logical sum of the logical product of RM20 and FAY00 and the logical product of RM21 and FAY01 is output to RBY0, and the complementary signal is output to RBY0b.
Is obtained. On the other hand, RM20 and R
An OR operation of M21 is performed to obtain an output RMA indicating whether or not there is a column address to be replaced. Then, like the address selection circuit CYS4 shown in FIG. 6, the RMA and the relief column addresses RBY0 and RBY0b to RBY6 are generated by AND circuits AND4 and AND3.
By taking the logical product with the desired combination of RBY6b, the relief column addresses RCY20 to RCY27, RCY40 to RCY43, RCY6 corresponding to the column predecode address CY in FIG.
0 to RCY63 are obtained.

In this address selection circuit CYS2, since the number of fuse sets to be selected is small, the logic circuit AOR2 is
It is configured using an S composite gate. As a result, FIG.
2, the number of elements can be reduced rather than using a level holding inverter.

FIG. 20 shows an example of replacing the column selection lines in the configuration described above. As in FIG.
The hatched area with a diagonally upward slant pattern is replaced with a hatched area with a lattice pattern. In this example, the fuse determination result FMSA is set to 1 in the mat selection signal comparison circuit C40 of the comparison determination circuit RYC23 in FIG.
The column selection line is replaced with 3 regardless of the mat selection signal. The other redundant column selection lines RYS0 to RYS2 replace the column selection lines at two locations with respect to eight mats in units of two continuous mats. Where RYS0, RY
In S1 and RYS2, the replacement unit is shifted by one mat. For example, in the redundant column selection line RYS1, mats MCA6 and MCA7 are commonly replaced, whereas in RYS2, mats MCA5 and MCA6 are commonly replaced. As described above, in the column-based rescue method of this embodiment, one fuse set can cope with a defect of the sense amplifier shared by the two mats. Moreover, it is not necessary to provide a fuse indicating whether or not two mats are used as a unit. In this embodiment, the number of fuses is smaller than the method described with reference to FIGS. 1 to 12, so the number of defective bit lines is relatively small, and when the number of defective sense amplifier units is large, efficient defect remedy can be achieved. Become.

<Embodiment 6> Next, there will be described a modification of the column block relief in which the OR of the mat selection signals of two mats is obtained in advance. FIG. 21 is another example of the configuration of the column-based relief determination circuit. Similarly to the column-based rescue judging circuit shown in FIG. 16, the OR circuit MSP8 of the mat selecting signal outputs the mat selecting signals MSEP and MSOP obtained by performing a logical sum, and the comparing and judging circuits RYC20 to RYC23 respectively perform the comparing and judging. Result RD
Y0 to RDY3 are output, and the column-based rescue determination result RYH is output by the 4-input OR circuit OR4. Comparison judgment circuits RY2P0 to RY2P3
Are mat selection signal comparison circuits C40 and C41 for comparing relief mat addresses and mat selection signal comparison circuit C4, respectively.
0, relief column address RCY by output RM20 and RM21 of C41
Select circuit CYS2 to select the relief column address
It comprises an address comparison circuit CYCP that compares RCY with the column predecode address CY. These circuits are configured in the same manner as in the embodiment described with reference to FIGS.
Here, CEP in RY2P0 to RY2P3 is MSEP, and C41 is MSOP.
Is a difference from the column-based rescue judging circuit shown in FIG.

FIG. 22 shows an example of replacing a column selection line when this column-based rescue judging circuit is used. FIG.
As in the case of FIG. 2 or FIG. 20, the hatched area with a diagonally upward slant pattern is replaced with a hatched area with a lattice pattern. In this example, the column selection line is replaced with the redundant column selection line RYS3 regardless of the mat selection signal. The other redundant column selection lines RYS0 to RYS2 replace the column selection lines at two locations with respect to eight mats in units of two continuous mats. However, each of RYS0 to RYS2
The two substitutions are shifted by one mat in the substitution unit. For example, mats MCA3, MCA4 and MC
A6 and MCA7 have the same substitution. As described above, in the column-based rescue method of this embodiment, one fuse set can cope with a defect of the sense amplifier shared by two mats, similarly to the replacement example shown in FIG. When this column-based rescue judging circuit is used, up to four defects in the same sense amplifier can be remedied.

As described above, the column-based rescue judging circuit shown in FIG. 21 can also realize the same function as the column-based remedy judging circuit shown in FIG. As described above, there can be various combinations of which of the mat selection signal comparison circuits the logic OR of the mat selection signal is input to. Here, there are 8 mats and 2 fuse sets for each redundant column selection line.
Although the simple example of the number is shown, when these numbers are large, there may be further various combinations. By selecting an appropriate column-based rescue judging circuit according to a combination of assumed failure probabilities, the rescue can be efficiently performed.

<Embodiment 7> FIG. 23 shows another example of the configuration of a column-based rescue judging circuit. FIG. 16 or FIG.
In the column-based rescue judging circuit shown in (1), the mat selection signals obtained by taking the logical sum of two mats are divided into two groups, and which of the mat selection signal groups is input for each fuse set is determined in advance. On the other hand, this column-based rescue judging circuit is characterized in that it is switched by a fuse. The OR circuit MSP8 of the mat select signal outputs the mat select signals MSEP and MSOP, which are ORed, and is input to the comparison determination circuits RY2Q0 to RY2Q3. Comparison judgment circuit RY2Q0-R
Y2Q3 outputs comparison determination results RDY0 to RDY3, respectively,
The input OR circuit OR4 outputs a column-based repair determination result RYH. The comparison determination circuits RY2Q0 to RY2Q3 are mat selection signal comparison circuits C80,
C81, mat selection signal comparison circuit C80, C81 output RM20, RM
An address selection circuit CYS2 for selecting the rescue column address RCY by 21 and an address comparison circuit CYCP for comparing the rescue column address RCY with the column predecode address CY. The OR circuit MSP8 is configured as shown in FIG. 17, the address selection circuit CYS2 is configured as shown in FIG. 19, and the address comparison circuit CYCP is configured as shown in FIG.

FIG. 24 shows a configuration example of the mat selection signal comparison circuit C80 in FIG. 5 fuse judgment circuits
FD or FDt, NMOS transistor group MNI8 and MNC
8, an NMOS transistor MNU, MNA0, MNA1, and a level holding inverter LCI. Three fuse judgment circuits FD
Are fuse determination results FMS0 to FMS2 indicating the relief mat selection signal in binary, and their complementary signals FMS0b to FMS0
Outputs MS2b. Here, the fuse determination result FMS2 indicates which one of the mat selection signals MSEP and MSOP, which is the logical sum in FIG. 23, is selected. On the other hand, the two fuse determination circuits FDt each have a fuse determination result FMSU indicating whether or not to perform replacement in accordance with the comparison result of the relief mat, and a fuse indicating whether or not to perform replacement regardless of the comparison result of the relief mat. Outputs the judgment result FMSA. NMOS transistor group MNIP8
Are mat selection signals MS01 to MS70 whose gates are ORed.
, And eight NMOS transistors connected to each other. On the other hand, the NMOS transistor group MNC8 includes 14 NMOS transistors whose gates are connected to the fuse determination results FMS0 to FMS2 and FMS0b to FMS2b. The level holding inverter LCI is configured as shown in FIG.

The mat selection signal comparison circuit C80 is the same as that shown in FIG.
Alternatively, as in the circuit shown in FIG. 18, the output is determined based on whether a current path is formed between the input terminal of the level holding inverter LCI and the ground. First, if FMSU and FMSA are low level, RM20 keeps low level. This is the case where no replacement is performed. If FMSU is at high level and FMSA is at low level, a current path is formed for any of MS01 to MS70 according to FMS0 to FMS2 and FMS0b to FMS2b. That is, when the three fuse determination circuits FD match the addresses stored in binary, the RM20 goes high. For example, FMS0 ~
If FMS2 is low and FMS0b to FMS2b are high,
When MS01 becomes high level, that is, MS0 in FIG.
Alternatively, a current path is formed when MS1 goes high, and RM20 goes high. If FMSA is at a high level, RM20 is at a high level regardless of which of MS0 to MS7 is at a high level. This is a case where the column selection line is replaced regardless of the mat.

The mat selection signal comparison circuit C81 in FIG.
This is also realized in the same manner as the mat selection signal comparison circuit C80 shown in FIG. However, the fuse determination circuit FDt that generates the fuse determination result FMSA and the NMOS transistor MNA0,
MNA1 is not required.

By using the column-based rescue judging circuit shown in FIG. 23, a defect remedy like the replacement example shown in FIGS. 20 and 22 can be realized. That is, since it is possible to switch to which fuse set the mat select signal obtained by taking the logical sum is assigned, the degree of freedom is greater and the defect is more efficiently provided as compared with the column-based rescue judging circuit shown in FIGS. Relief is possible.

<Embodiment 8> FIG. 25 shows still another example of the configuration of a column-based rescue judging circuit. In the column-based rescue judging circuits shown in FIGS. 4, 16, 21, and 23 described above, the rescue column address is selected by comparing the mat select signal with the rescue mat select signal. On the other hand, this column-based rescue judging circuit is characterized in that a fuse set of a rescue column address is provided for each of the mat select signals input to the comparing and judging circuit, and it is not necessary to compare the mat select signals. . A mat select signal obtained by ORing the OR circuit MSP8 of the mat select signal
MSEP and MSOP are output and the comparison judgment circuits RY4A0 and RY4A1
EP is input, and MSOP is input to RY4A2 and RY4A3. The comparison judgment circuits RY4A0 to RY4A3 output the comparison judgment results RDY0 to RDY3, respectively.
Outputs RYH. Each of the comparison determination circuits RY4A0 to RY4A3 includes an address selection circuit CYS4 for selecting a rescue column address RCY based on an input mat selection signal, and an address comparison circuit CYCP for comparing the rescue column address RCY with the column predecode address CY. Address selection circuit CYS4
Is configured as shown in FIG. However, instead of the comparison results RM40 to RM43 of the mat selection signals, a mat selection signal MSEP or MSOP obtained by performing an OR operation is input. on the other hand,
The address comparison circuit CYCP is configured as shown in FIG.

FIG. 26 shows an example of replacement of a column selection line in the configuration using the column-based rescue judging circuit of FIG. As in FIG. 12 and the like, the hatched area with a diagonally upward slant pattern is replaced with a hatched area with a lattice pattern. In this example, with two consecutive mats as units
The column selection lines are replaced at four locations for each of the eight mats. However, in RYS0, RYS1 and RYS2, RYS3, the replacement unit is shifted by one mat. For example, the redundant column selection line R
In YS1, the mats MCA6 and MCA7 are commonly replaced, whereas in RYS2, the mats MCA5 and MCA6 are commonly replaced.
Further, the comparison and decision circuit RY4A3 in FIG. 16 sets the four sets to the same relief column address, and replaces the column selection line with the redundant column selection line RYS3 regardless of the mat selection signal. As described above, in the column-based rescue method of this embodiment, a fuse set of the rescue column address for all mats is provided for every two mats, and one fuse set is provided for a defect of the sense amplifier section shared by the two mats. Can respond. Moreover,
The fuse for storing the rescue mat address and its comparison circuit are unnecessary, and a large number of defects can be rescued by a small area rescue judging circuit.

[0062]

In the block rescue, a defect extending between two blocks can be remedied by replacing it with one fuse set. For example, in a configuration in which a sense amplifier section is shared by two DRAM mats, a defect in the sense amplifier can be replaced by one fuse set by a column block repair. As a result, a semiconductor memory device having a defect relief circuit with a small area, high relief efficiency, and a short time for storing a defective address is realized, and the manufacturing cost of the semiconductor memory device can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a mat selection signal comparison circuit that can take a logical sum;

FIG. 2 is a block diagram of a main part of a synchronous DRAM.

FIG. 3 is a diagram showing operation timing.

FIG. 4 is a diagram showing a configuration example of a column-based defect remedy determination circuit.

FIG. 5 is a diagram illustrating a configuration example of a fuse determination circuit.

FIG. 6 is a diagram showing a configuration example of a relief column address selection circuit.

FIG. 7 is a diagram illustrating a configuration example of a column address comparison circuit.

FIG. 8 is a diagram showing a configuration example of a column address driver.

FIG. 9 is a diagram showing a configuration example of a memory array.

FIG. 10 illustrates a configuration example of a column decoder.

FIG. 11 is a diagram showing a configuration example of a memory cell array and a sense amplifier unit.

FIG. 12 is a diagram showing an example of replacement of a column selection line.

FIG. 13 is a diagram showing another configuration example of a mat selection signal comparison circuit that can take a logical sum;

FIG. 14 is a diagram showing another configuration example of the fuse determination circuit.

FIG. 15 is a diagram illustrating a configuration example of an antifuse determination circuit.

FIG. 16 is a diagram showing another configuration example of the column-related defect remedy determination circuit.

FIG. 17 is a diagram illustrating a configuration example of an OR circuit of a mat selection signal.

FIG. 18 is a diagram illustrating a configuration example of a mat selection signal comparison circuit.

FIG. 19 is a diagram showing a configuration example of a relief column address selection circuit.

FIG. 20 is a diagram showing a replacement example of a column selection line.

FIG. 21 is a diagram showing another configuration example of the column-related defect remedy determination circuit.

FIG. 22 is a diagram showing a replacement example of a column selection line.

FIG. 23 is a diagram showing another configuration example of the column-related defect remedy determination circuit.

FIG. 24 is a diagram showing a configuration example of a mat selection signal comparison circuit.

FIG. 25 is a diagram illustrating a configuration example of a column-related defect remedy determination circuit that does not compare a mat selection signal.

FIG. 26 is a diagram showing a replacement example of a column selection line.

[Explanation of symbols]

A: Activate command, AB: Address buffer, ADR: External address, AFUSE: Antifuse, AND0, AND1, AND2 ... 2-input AND circuit, AND3,
AND5 ... 3-input AND circuit, AND4 ... 4-input AND circuit,
AOR2: CMOS composite gate, AOR4: Logic circuit, BL
0t to BL7t, BL0b to BL7b ... bit line, BLOW ... antifuse blow control signal, BUF1, BUF2 ... buffer circuit,
BX: Row address, BY: Column address, C40, C
41, C80, C81, C8P0 to C8P3 ... Mat selection signal comparison circuit,
CB: Control signal buffer, CD: Command decoder,
CGND: Control signal for anti-fuse judgment circuit, CLK: External clock, CLKB: Clock buffer, CLKI: Internal clock, CMD: Control signal from outside, CSFP: Common node for fuse judgment circuit, CSN, CSP: Sense amplifier drive line , CX: Row predecode address, CY, CY20
CY27, CY40 to CY43, CY60 to CY63 ... column predecode address, CYCP ... column address comparison circuit, CYS2,
CYS4: relief column address selection circuit, DIB: input buffer, DOB: output buffer, DQ: external input / output data, DX: row address signal, DY, DY20 to DY27, DY
40 to DY43, DY60 to DY63 ... column address signal, FAY00
~ FAY03, FAY10 ~ FAY13, FAY20 ~ FAY23, FAY30 ~ FAY33,
FAY40 to FAY43, FAY50 to FAY53, FAY60 to FAY63: Fuse judgment result of column address, FCN: Fuse judgment circuit cell, FD, FDt: Fuse judgment circuit, FE, FEb: Enable signal of fuse judgment circuit, FMS0 to FMS2, FMS0b
~ FMS2b, FMSA, FMSP, FMSU, FO, FOb, FO0, FO0b, FO
1, FO1b… Fuse judgment result, FUSE… Fuse, GI…
Write data, GO… Read data, HVC… Bit line precharge voltage, INV0, INV1, INV2, INV3, INV
4, INV5, INVH… CMOS inverter, IO0t and IO0b, I
O1t and IO1b: I / O line pair, IOG0, IOG1: I / O gate, LCI: Level holding inverter, MA: Main amplifier, MAR: Memory array, MC: Memory cell, MCA0
~ MCA7: Memory cell array mat, MIO: Main input / output line, MN4, MN5, MN6, MN7, MNA0, MNA1, MNSW, MN
U… NMOS transistor, MNC4, MNC8, MNI4, MNI8,
MNIP8, MNUP8… NMOS transistor group, MP0, MP1,
MP3, MP4, MP5, MPA0, MPC, MPSW: PMOS transistor, MS, MS0 to MS7: mat select signal, MS01, MS12,
MS23, MS34, MS45, MS56, MS67, MS70, MSEP, MSOP… MAT select signal ORed, MSP8… Mat select signal OR circuit, OR2, ORM2… 2 input OR circuit, OR4, ORM
4… 4 input OR circuit, PC… Precharge circuit control signal, PC0, PC1… Precharge circuit, R… Read command, RBY0 to RBY6, RBY0b to RBY6b… Complementary relief column address, RCY, RCY20 to RCY27, RCY40 ~ RCY43, RCY60
~ RCY63 ... relief column address signal, RDY, RDY0 ~ RDY3,
RDYi: Comparison judgment result of column block relief, RM20,
RM21, RM40 to RM43… comparison result of mat select signal, RMA
… Response column address presence / absence signal, RSTb… Reset signal, RXH… Row related rescue judgment result, RY2P0 to RY2P
3, RY2Q0 ~ RY2Q3, RY4A0 ~ RY4A3, RYC20 ~ RYC23, RYC40
~ RYC43 ... column address comparison judgment circuit, RYH ... column system rescue judgment result, RYS0 ~ RYS3 ... redundant column selection line,
SA0, SA1 Sense amplifier, SAB0 to SAB8 Sense amplifier, SAC0 to SAC8 Sense amplifier control circuit, SCT0, SCT1
... Sector of memory core, SHL, SHR ... Shared gate control signal, SHL0, SHL1, SHR0, SHR1 ... Shared gate, SINV ... Switched inverter, VCC ... Power supply voltage, WB ... Write buffer, WL, WL0-WL255 ... Word Line, X: row address, XD: row address driver, XDEC0 to XDEC7: row decoder, XPD: row address predecoder, XR: row defect repair circuit, Y ...
Column address, YCT ... Column address counter, Y
D: column address driver, YDEC: column decoder, YPD: column address predecoder, YR: column-related defect relief circuit, YS, YS0 to YS127: column select lines.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mitsuo Takahashi 3-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Hiroya Nakamura 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Texa F-term (reference) in S & T Instruments Inc. 5B024 AA15 BA05 BA10 BA13 BA15 CA07 CA17 CA27 5L106 AA01 CC04 CC16 CC17 GG07

Claims (9)

[Claims] 1. A first memory mat, a second memory mat, and a third memory mat each having a plurality of bit lines crossing a plurality of word lines and a plurality of memory cells provided at intersections of spare bit lines. A plurality of column selection lines provided over the first to third memory mats and provided respectively corresponding to one of the plurality of bit lines of the first to third memory mats; And a spare column selection line provided corresponding to a spare bit line of the first to third memory mats, and a defect rescue circuit coupled to the spare column selection line. The defect rescue circuit includes a first memory mat for designating one of the first to third memory mats associated with a first defect for determining selection of the spare column line.
Information, second information for designating one of the plurality of column selection lines related to the first defect among the plurality of column selection lines, and the first information related to the first defect. A semiconductor device having an area for storing third information for determining selection or non-selection of a memory mat adjacent to a specified memory mat. 2. The memory device according to claim 1, wherein said first to third memory mats are arranged adjacent to each other, and said defect relief circuit operates said bit line in said first and second memory mats based on said third information. And a replacement of the bit line and the spare bit line in the third memory mat and prohibition of replacement of the bit line and the spare bit line in the third memory mat can be programmed. 3. The semiconductor device according to claim 1, wherein the semiconductor device comprises a plurality of first sense amplifiers disposed between the first and second memory mats, and a plurality of first sense amplifiers disposed between the second and third memory mats. A semiconductor device comprising a plurality of second sense amplifiers arranged. 4. The device according to claim 3, wherein the first defect is related to one defect of the plurality of first sense amplifiers shared by each of the plurality of bit lines of the first and second memory mats. A semiconductor device characterized by the above-mentioned. 5. The method according to claim 1, wherein the first information to the third information are programmable by a fuse circuit storing one-bit information by cutting and non-cutting, respectively. Semiconductor device. 6. The semiconductor device according to claim 1, wherein said third information is programmable by a 1-bit fuse circuit. 7. The semiconductor device according to claim 1, wherein the semiconductor device selects a desired one of the plurality of memory cells according to a row address and a column address, and the first information is the row address. Wherein the second information is related to a column address. 8. The defect repair circuit according to claim 1, wherein said defect relieving circuit ignores said first information and third information and selects said spare column selection line based only on said second information. The semiconductor device further comprises an area for storing fourth information for designating this by one bit. 9. The memory cell according to claim 1, wherein each of said plurality of memory cells includes one transistor.
A semiconductor device comprising a dynamic memory cell including a plurality of capacitors.