JP2000076863A - Circuit for preventing sinking of digit line for memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit for preventing a digit line for memory from sinking that can prevent a fault mode without allowing a steady feedthrough current to flow. SOLUTION: A circuit is composed of data transition detection circuits DTD 1-DTD8 in 8-bit configuration for generating a one-shot pulse signal for controlling a pull-up transistor PL2 that works out countermeasures against a fault mode provided in a digit line only at the time when writing is started or data changes and for outputting a one-shot pulse signal for data transition when the data of a data signal DIN changes, a WEOS circuit for outputting a one-shot pulse signal WEOS for controlling writing when a write control signal WEB changes to writing from reading, and a logical OR one-shot pulse signal OSDW circuit for outputting a write control and data transition logical OR one-shot pulse signal WE-DATA-OS where a pulse width is adjusted appropriately by calculating the logical OR of the pulse signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly controls a pull-up transistor for dealing with a failure mode in which a digit line in a cell array of a static random access memory (SRAM) sinks and data is destroyed in a cell. The present invention relates to a digit line sinking prevention circuit for a memory.

[0002]

2. Description of the Related Art Conventionally, for example, static random
It is known that a memory cell array of an access memory (SRAM) has a failure mode in which a digit line sinks due to an interline capacity of the digit line and data in the cell is destroyed.

FIG. 4 shows a conventional static random access memory.
1 shows a local portion of a cell array structure of an access memory (SRAM). FIG. 5 is a timing chart of each signal shown for explaining the operation processing (in the case of a failure mode) in this cell array structure.

In general, a cell array in a static random access memory (SRAM) has a structure in which m word lines, n digit line pairs, and m × n memory cells are arranged in a matrix. However, in the example shown in FIG. 4, digit line pairs A (by digit lines DB1 and DT1) and B (digit lines DB2 and
DT2) and four cells 1 to 4 arranged on the word lines WL1 and WL2. In addition, a load circuit 5 for applying a predetermined potential to the digit lines DB1, DT1, DB2, and DT2 for maintaining a data state in each of the cells 1 to 4 and a precharge circuit 6 (control probe signal PB is Is inputted), and a line capacitance C is provided between the digit lines DT1 and DT2.
L exists.

Here, cells 1 to 3 hold 1, 0 and 1 as initial data, respectively, and the cell HIGH node receives digit lines DT1, DB1. D
A write operation in which data is rewritten from 1 (same as the initial data) to 0 (reverse to the initial data) in cell 3 in the state connected to T2 will be described.

In this case, there are an address (ADD) change and a write (write), and the unselected word line W
L1 becomes GND, and the selected word line WL2 becomes HI.
GH. Thus, the selected cell 3 is in a state where writing is performed, and the unselected cell 2 connected to the same word line WL2 as the cell 3 also has the word line WL.
2 becomes HIGH, so that the data of the cell 2 is read out to the digit line pair A in a pseudo manner. Digit line DT2 in a state where data 0 is written to cell 3 is at reference potential VC.
C is the HIGH level. After a long time, the digit line DT1 connected to the non-selected cell 2 reads the initial data 0 from the cell 2 and the digit line DT1
Goes from the HIGH level of the reference potential VCC to the GND level. At this time, the input data signal DIN becomes HIGH (data 1) due to a data change (data change).
Becomes LOW (data 0), the digit line DT2
Also goes from HIGH to LOW, but the digit lines DT2 and D
The digit line DT1 also sinks due to the line capacitance CL of T1.

That is, the digit line DT1 which is not selected is
Since there is a GND level before the data change, the potential drops below the GND level due to the effect of the line capacitance CL when the digit line DT2 becomes GND when there is a data change. The sink of this potential is -V
T (where VT indicates the cell transfer threshold of cell 1) or less, the word line WL of unselected cell 1 connected to the same digit line pair A as cell 2
1 turns on. For this reason, the HIGH level of the cell 1 holding the data “1” drops to the digit line DT1 which is lower than the GND level, and the data of the cell 1 is destroyed. In this way, a failure mode occurs.

FIG. 6 shows a local portion of a cell array structure of a static random access memory (SRAM) having such a failure mode prevention function. FIG. 7 is a timing chart of each signal shown for explaining the operation processing (in the case of preventing a failure mode) in the cell array structure.

This cell array is also generally composed of m word lines, n digit line pairs, and m × n memory cells arranged in a matrix, as shown in FIG. For example, digit line pair A (digit line DB1, DT1), B (digit line DB2, digit line DB2)
DT2) and four cells 1 to 4 arranged on the word lines WL1 and WL2. In addition, a load circuit 5 and a precharge circuit 6 are connected to the digit lines DB1, DT1, DB2, and DT2, respectively, and a line capacitance CL is provided between the digit lines DT1 and DT2.
Exist and digit lines DB1, DT1, DT
2 and DB2 have Nch transistors NB1 and N
The drain sides of T1, NT2 and NB2 are connected, all of the gate side and the source side thereof are connected to the drain sides of pull-up transistors PL1 and PL2, and the source sides of pull-up transistors PL1 and PL2 are connected to the power supply voltage. The write control signal WEB is input to the gate of the pull-up transistor PL1, and the write control one-shot pulse signal WEOS is input to the gate of the pull-up transistor PL2. Note that the write control one-shot pulse signal WEOS
Indicates that the write control signal WEB is HI
When transitioning from GH to LOW (that is, from read to write), a one-shot pulse signal for write control (WEOS) is formed as a downwardly convex waveform adjusted to an appropriate pulse width.
Output from the circuit.

Here, cells 1 to 3 hold 1, 0 and 1, respectively, as initial data, and the cell HIGH node receives digit lines DT1, DB1.
A description will be given of a write operation in which data is rewritten from 1 (the same as the initial data) to 0 (the reverse of the initial data) of the cell 3 in the state of being connected to the DT2.

In this case, there are an address (ADD) change and a write (write), and the unselected word line W
L1 becomes GND, and the selected word line WL2 becomes HI.
GH. In addition, the write control signal WEB turns HIGH.
→ As a result of LOW (from read to write), the pull-up transistor PL1 is turned ON and the digit line DB is constantly
1, DT1, DT2, and DB2 are pulled up, and the pull-up transistor PL2 is turned ON only while the write control one-shot pulse signal WEOS is LOW to pull up the digit lines DB1, DT1, DT2, and DB2.

Then, the selected cell 3 enters a state in which writing is performed, and the unselected cell 2 connected to the same word line WL2 as the cell 3 also has the word line WL.
2 becomes HIGH, so that the data of the cell 2 is read out to the digit line pair A in a pseudo manner. Digit line DT2 in a state where data 0 is written to cell 3 is at reference potential VC.
C is the HIGH level. Initial data 0 is read from the cell 2 to the digit line DT1 connected to the non-selected cell 2. However, even after a long time, the digit line DT1 is constantly pulled up during the write period. Digit line DT1 does not fall from the HIGH level of reference potential VCC to the GND level. At this time, the input data signal DIN becomes HIGH (data 1) due to a data change.
Becomes LOW (data 0), the digit line DT2
Goes from HIGH to LOW, but the digit lines DT2, D
The digit line DT1 also sinks due to the line capacitance CL of T1.

However, since the digit line DT1 is at a level higher than the GND level before the data change, there is a digit line DT1 when the data change occurs.
2 becomes GND due to the influence of the line capacitance CL when GND becomes GND.
The potential sinks below the level, but the sink does not cause the potential to fall below -VT. Therefore, the unselected cell 1 connected to the same digit line pair A as the cell 2
The word line WL1 is not turned on, so that the data in the cell 1 does not escape and no data destruction occurs.

Incidentally, a memory having a cell array structure which suppresses the influence of coupling noise having such line capacitance, prevents data destruction of non-selected cells, and allows transition of write data during a write operation. As a well-known technique related to the above, there is, for example, a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 10-27474.

[0015]

In the case of the defect mode prevention function provided in the cell array structure of the static random access memory (SRAM) described above, the pull-up transistor PL1 is constantly turned on during a write (write) period. There is a problem that a steady through current flows due to turning on.

The present invention has been made to solve such a problem. The technical problem of the present invention is that a cell penetrates due to sinking of a digit line due to line capacitance without flowing a steady through current. Another object of the present invention is to provide a digit line sinking prevention circuit for a memory which can prevent a failure mode which causes data destruction.

[0017]

According to the present invention, a digit line is provided for a digit line in a cell array in order to take measures against a failure mode in which the digit line sinks due to an interline capacitance of the digit line and causes data destruction of a cell. Thus, a digit line sinking prevention circuit for a memory that generates a one-shot pulse signal for controlling the pull-up transistor only at the start of writing or at the time of data change can be obtained.

It is preferable that the memory digit line sinking prevention circuit includes a data transition detection circuit that generates a one-shot pulse signal when data changes.

Further, according to the present invention, in the above-mentioned memory digit line sinking prevention circuit, the data transition detection circuit outputs a data transition one-shot pulse signal as a one-shot pulse signal when the data of the input data signal changes. A digit line sinking prevention circuit for a memory to be output is obtained.

Further, according to the present invention, in the above-described memory digit line sinking prevention circuit, the write control one-shot pulse signal is used as the one-shot pulse signal when the write control signal input at the start of writing is changed from read to write. A digit line sinking prevention circuit for memory including a write control one-shot pulse signal circuit for outputting a signal is obtained.

In addition, according to the present invention, the memory digit line sinking prevention circuit calculates the logical sum of the data transition one-shot pulse signal and the write control one-shot pulse signal to start the write operation or the data control. It is possible to obtain a memory digit line sinking prevention circuit provided with a logical sum one-shot pulse signal circuit that outputs a write control and data transition logical one-shot pulse signal adjusted to an appropriate pulse width as a one-shot pulse signal at the time of change. .

On the other hand, according to the present invention, the above-mentioned digit line sinking prevention circuit for a memory is provided to prevent a failure mode in which the digit line sinks due to the capacitance between the digit lines in the cell array and data in the cell is destroyed. A static cell having a cell array structure connected to a pull-up transistor provided on the digit line.
A random access memory (SRAM) is obtained.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows a local portion of a cell array structure of a static random access memory (SRAM) to which a digit line sinking prevention circuit for a memory according to an embodiment of the present invention is applied. In the case of this cell array, m word lines, n digit line pairs, and m × n memory cells are generally arranged in a matrix on them, but in the case of FIG. Line pair A (by digit lines DB1, DT1), B
(With digit lines DB2 and DT2) and word line W
Only four cells 1 to 4 arranged at L1 and WL2 are shown. In addition, digit lines DB1, DT1,
A load circuit 5 and a precharge circuit 6 are connected to DB2 and DT2, respectively.
Between the line capacitance CL and the digit line D
The drain sides of Nch transistors NB1, NT1, NT2, and NB2 are connected to B1, DT1, DT2, and DB2, respectively, and all of the gate side and source side thereof are 1
It is connected to the drain side of the pull-up transistors PL2. The pull-up transistor PL here
The source side of 2 is connected to the power supply voltage, and the gate side is supplied with a write control and data transition OR one-shot pulse signal (WE-DATA-OS).

FIG. 2 is a circuit diagram for explaining a memory digit line sinking prevention circuit according to an embodiment applied to this cell array structure. FIG. 2A is a memory digit line sinking circuit. FIG. 4B relates to a circuit block diagram of the entire anti-intrusion circuit, FIG. 5B relates to a data transition detection circuit (DTD) in FIG. 5A, and FIG. One-shot pulse signal (WE
FIG. 2D relates to the logical sum one-shot pulse signal (OSDW) circuit in FIG.

The digit line sinking prevention circuit for memory uses digit lines DB1 and DB1 to prevent a failure mode.
A one-shot pulse signal for controlling the pull-up transistor PL2 provided in T1, DB2, and DT2 only at the start of writing or at the time of data change, is provided with an input / output (IO) terminal. Whether the signal DIN is LOW → HIGH or HIGH
→ Data transition detection of n-bit configuration (here, 8-bit configuration with n = 8) that outputs a one-shot pulse signal for data transition with a downwardly convex waveform when transitioning to LOW (that is, data change). (DTD1 to DTD8) circuit and the input write control signal WEB changes from HIGH to L
A write-control one-shot pulse signal (WEOS) circuit for outputting a write-control one-shot pulse signal (WEOS) with a downwardly convex waveform when transitioning to OW (that is, starting writing from read to write); The logical sum of the one-shot pulse signal for data transition and the one-shot pulse signal for write control (WEOS) is calculated, and the write control using a downwardly convex waveform adjusted to an appropriate pulse width at the time of inputting any of them is performed. And an OR one-shot pulse signal (OSDW) circuit for outputting a data transition OR one-shot pulse signal (WE-DATA-OS).

In the example shown in FIG. 2B, the data transition detection (DTD1 to DTD8) circuit having an 8-bit configuration includes two inverter gates disposed on the input side and the output side of the DELAY. And DELAY input side and DEL
A NAND gate connected to the output side of the inverter gate on the output side of AY, the output side of DELAY and the DELA
Another NAND gate connected to the input side of the inverter gate on the input side of Y, another NAND gate connected to the output side of these NAND gates, and another NAND gate
This configuration has another inverter gate connected to the output side of the gate, that is, a configuration in which three inverter gates, three NAND gates, and DELAY are combined.

In the example shown in FIG. 2C, the write control one-shot pulse signal (WEOS) circuit
An inverter gate disposed on the input side of the ELAY;
A NOR gate connected to the output side of the DELAY and the input side of the inverter gate, and another inverter gate connected to the output side of the NOR gate;
Two inverter gates, NOR gate, and DEL
AY is combined.

Further, a logical sum one-shot pulse signal (O
In the example shown in FIG. 2D, the SDW) circuit includes four NAND gates, each of which receives an output from data transition detection (DTD1 to DTD8) in ascending order, and a write control one-shot. One NAND gate to which a pulse signal (WEOS) is input, and five one-conductivity-type field-effect devices each having a gate connected to the output of these NAND gates on a one-to-one basis and having a source grounded. A transistor (FET); one reverse conductivity type field effect transistor (FET) having a drain connected to the drain side of the field effect transistor (FET) and a gate side grounded; and a field effect transistor (FET). ) Is connected to one input side to all drain sides, and the other input side is connected to a field effect transistor (F
ET), and a NOR gate connected to the output side of the DELAY connected to all the drain sides, ie, 5
NAND gates and six field effect transistors (F
ET), one NOR gate and DELAY are combined.

FIG. 3 is a timing chart of each signal shown for explaining the operation processing (in the case of preventing a failure mode) in the cell array structure shown in FIG. 1 by the memory digit line sinking prevention circuit. .

Here, cells 1 to 3 hold 1, 0 and 1, respectively, as initial data, and the cell HIGH node receives digit lines DT1, DB1.
A description will be given of a write operation in which data is rewritten from 1 (the same as the initial data) to 0 (the reverse of the initial data) of the cell 3 in the state of being connected to the DT2.

In this case, there are an address (ADD) change and a write (write), and the unselected word line W
L1 becomes GND, and the selected word line WL2 becomes HI.
GH. In addition, the selected cell 3 is in a state where writing is performed, and even in the non-selected cell 2 connected to the same word line WL2 as the cell 3, the word line WL2 becomes HIGH. , The data of cell 2 is read in a pseudo manner. Digit line DT2 in the state where 0 is written to cell 3 is at the high level of reference potential VCC.
Level. After a long time, 0 of the initial data is read from the cell 2 to the digit line DT1 connected to the non-selected cell 2, and the digit line DT1 is connected to the reference potential V.
The CC goes from the HIGH level to the GND level. At this time, the data signal changes the data signal DIN to HIGH.
When (data 1) changes to LOW (data 0), the pull-up transistor PL2 receives a one-shot pulse signal (WE-
DATA-OS) is input in a downwardly convex waveform as shown in the figure, and the digit line DT1 is pulled up only during that period. The digit line DT2 changes from HIGH to LOW, but the digit line DT1 also sinks due to the inter-line capacitance CL between the digit lines DT2 and DT1.

However, the non-selected digit line DT1
Is at the GND level before the data change, so that the digit line DT2
Becomes lower than the GND level due to the influence of the line capacitance CL when the potential becomes GND. At this time, the potential is pulled down by the pull-up transistor PL2. Cell transfer threshold of cell 1). Therefore,
The word line WL1 of the non-selected cell 1 connected to the same digit pair A as the cell 2 is not turned on, so that the data of the cell 1 is not lost and no data is destroyed.

That is, in the case of the digit line sinking prevention circuit for memory, the pull-up transistor PL2 is turned on.
The digit line DT1 is pulled up by the write control and data transition OR one-shot pulse signal (WE-) input from the gate of the pull-up transistor PL2.
DATA-OS) during a one-shot period in which a downwardly convex waveform is shown, and no steady through current flows.

[0035]

As described above, according to the digit line sinking prevention circuit for a memory of the present invention, the pull-up transistor provided on the digit line is used at the start of writing or when the data is written in order to take measures against the existing failure mode. Control is performed during a one-shot period that shows a downwardly convex waveform by a one-shot pulse signal generated only at the time of change, so that a digit line sinks due to line capacitance without flowing a steady through current. A failure mode that causes data destruction of a cell due to this can be properly prevented.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a static random access memory to which a digit line sinking prevention circuit for a memory according to an embodiment of the present invention is applied;
1 shows a local portion of a cell array structure of an access memory (SRAM).

FIGS. 2A and 2B are circuit diagrams illustrating a circuit for preventing digit line sinking for a memory according to an embodiment applied to the cell array structure shown in FIG. 1; FIG. (B) Data transition detection circuit (DTD) in (a)
(C) relates to the write control one-shot pulse signal (WEOS) circuit in (a),
(D) relates to the write control and data transition OR one-shot pulse signal (OSDW) circuit in (a).

3 is a timing chart of each signal shown to explain an operation process (in the case of preventing a failure mode) in the cell array structure shown in FIG. 1 by the memory digit line sinking prevention circuit described in FIG. 2;

FIG. 4 shows a local portion of a cell array structure of a conventional static random access memory (SRAM).

FIG. 5 is a timing chart of each signal shown for describing an operation process (in the case of a failure mode) in the cell array structure shown in FIG. 4;

FIG. 6 shows a local portion of a cell array structure of a conventional static random access memory (SRAM) having a function of preventing a failure mode.

FIG. 7 is a timing chart of each signal shown to explain an operation process (in the case of preventing a failure mode) in the cell array structure shown in FIG. 6;

[Explanation of symbols]

 1-4 cells 5 Load circuit 6 Precharge circuit A, B Digit line pair CL Line capacitance NB1, NT1, NT2, NB2 Nch transistor PL1, PL2 Pull-up transistor

Claims (6)

[Claims] In order to cope with a failure mode in which a digit line sinks due to the capacitance of a digit line in a cell array and data is destroyed in a cell, a pull-up transistor provided on the digit line is written at the start of writing or data. A digit line sinking prevention circuit for a memory, which generates a one-shot pulse signal for controlling only at the time of change. 2. The digit line sinking prevention circuit for a memory according to claim 1, further comprising a data transition detection circuit for generating said one-shot pulse signal when said data changes. circuit. 3. A digit line sinking prevention circuit for a memory according to claim 2, wherein said data transition detection circuit outputs a data transition one-shot pulse signal as said one-shot pulse signal when a data of an input data signal changes. A digit line sinking prevention circuit for memory characterized by outputting. 4. The write digit line sink prevention circuit for a memory according to claim 3, wherein the write control signal input as the start of writing is a one-shot pulse signal for write control as the one-shot pulse signal when writing from read to write. A digit line sinking prevention circuit for a memory, comprising a write control one-shot pulse signal circuit for outputting a signal. 5. The digit line sinking prevention circuit for memory according to claim 4, wherein a logical sum of said one-shot pulse signal for data transition and said one-shot pulse signal for write control is calculated to start said writing or said writing. A digit line for a memory, comprising: a write control signal adjusted to an appropriate pulse width as the one-shot pulse signal and a logical sum one-shot pulse signal circuit for outputting a data transition logical one-shot pulse signal when the data changes. Anti-subduction circuit. 6. A digit line sinking prevention circuit for a memory according to claim 5, wherein said digit line sinks due to an inter-line capacitance of the digit line in a cell array to prevent a failure mode in which data of a cell is destroyed. Having a cell array structure connected to a pull-up transistor provided on the line.
Access memory.