JP2000075848A - Interface circuit and display device using the circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interface circuit capable of outputting a data signal and clock signal that satisfy the set-up time and hold time of the data signal by making an adjustment so that the prescribed edge of the clock signal pulse corresponds to the prescribed position in the effective data area of the data signal and outputting the adjusted clock signal and data signal. SOLUTION: The device is equipped with an adjusting part for adjusting timing with a clock signal 6 and a data signal 7. Then, the clock signal 6 is shifted to the rear for a prescribed time, thereby securing the set-up time 8 and the hold time 9 as both stipulated by a driver IC. In the case where the set-up time 8 is unsatisfied, the function of the interface circuit is used, a function in which the clock signal 6 is shifted to the rear by a half cycle period of the clock signal 6, as is a function in which one is selected from the time quantities of plural stages and shifted to the rear for a prescribed time. As a result, the clock signal 6 is delayed for the optimal time length, satisfying the prescribed set-up time 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an interface circuit used for an output section for outputting a clock signal and a data signal to an external circuit, and a display device using the interface circuit.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a conventional display device. In the figure, 1 is a display screen such as a liquid crystal panel, 2 is a first driving circuit such as a scanning line driving circuit for driving the display screen 1, and 3 is a second driving circuit such as a signal line driving circuit for driving the display screen 1. The circuit 4 is a control circuit for generating input signals of the first drive circuit 2 and the second drive circuit 3, and the reference numeral 5 is for generating reference voltages of circuit systems such as the first drive circuit 2 and the second drive circuit 3. Power supply unit. In the electric circuit configuration of the conventional display device shown in FIG. 9, a clock signal and a data signal other than the clock signal are generated by the control circuit 4 and input to the first drive circuit 2 and the second drive circuit 3. used. Here, the clock signal means a clock signal used in each of the first drive circuit 2 and the second drive circuit 3, and the data signal other than the clock signal means the display data signal and the control signal other than the display data signal. Means At an input portion of the driver IC in the first drive circuit 2 and the second drive circuit 3 for generating a drive voltage for driving the display screen of the display device, an active edge of the clock signal output from the control circuit 4 When a data signal is input at a timing that satisfies the setup time and the hold time specified in the specifications of the driver IC,
The display operates normally.

FIG. 10 shows a driver IC of a conventional display device.
FIG. 4 is a voltage waveform diagram at the input of FIG. 5 when a data signal satisfies a setup time and a hold time defined with respect to an active edge of a clock signal. In the figure, 6 is a clock signal, 7 is a data signal,
Reference numeral 8 denotes a specified setup time, 9 denotes a specified hold time, 10 denotes an effective data area at a certain position (arrow of an edge in the figure) at an active edge (rising edge in the figure) of the clock signal, and 1CLK denotes a clock. This is the period of the signal. Arrows at the edges of the clock signal indicate active edges (rising edges in the figure) of the clock signal. The hatched portion of the data signal indicates an invalid data area. As can be seen, the setup time 8 and the hold time 9 fall within the valid data area 10.

[0004]

However, as the clock frequency increases with the increase in the screen size and the definition of the display device, the first drive circuit 2 and the second drive circuit 3 and the control circuit 4 become inconsistent with each other. E placed between the driver IC
Depending on the modulation effect of the intermediate circuit such as the MI filter, the wiring condition of the signal lines, and the use environment of the display device, the clock signal and the data signal are different in the input section of the driver IC from the output section of the control circuit 4 by different delay times. For example, the specified setup time or hold time is not satisfied, for example, as shown in FIG. 11 due to the occurrence of the effective data area, and a data sampling error occurs in the driver IC. There is a problem that the operation stops. This is particularly likely to occur in the second drive circuit 3 to which a high-frequency signal is input.

FIG. 11 shows a driver IC of a conventional display device.
FIG. 3 is a voltage waveform diagram at the input of FIG. 3 when the setup time and the hold time defined for the active edge of the clock signal are not satisfied. FIG. 11A shows a case where the setup time is not satisfied, and FIG. 11B shows a case where the hold time is not satisfied. Regardless of the display device, even in other devices to which a clock signal and a data signal are input, as the clock frequency increases with higher performance and the like, the circuit configuration of the external circuit and the interface between the interface circuit and the external circuit are increased. E placed on
Depending on the modulation effect of the intermediate circuit such as the MI filter, the wiring condition of the signal lines, and the usage environment of the device, the clock signal and the data signal are output from the input portion of the external circuit with different delay times to the output portion of the interface circuit. Due to the occurrence and the reduction of the effective data area, the setup time or the hold time defined in the same manner as in FIG. 11 is not satisfied, and the device does not operate normally due to the occurrence of a data sampling error in the external circuit. Problems arise.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an output destination circuit can output a data signal and a clock signal that satisfy a setup time and a hold time of a data signal. The primary purpose is to obtain an interface circuit that can be used. A second object is to obtain a display device using such an interface circuit.

[0007]

In the interface circuit according to the present invention, a clock signal formed by a periodic pulse and a data signal constituted by a valid data area are inputted, and a predetermined edge of the pulse of the clock signal is inputted. An adjustment unit that adjusts the data signal so as to correspond to a predetermined position in the effective data area and outputs the adjusted clock signal and data signal is provided. The adjusting unit includes a clock signal generating unit that generates a plurality of clock signals having different delay amounts from the input clock signal, and a clock in which a predetermined edge of the pulse corresponds to a predetermined position in the valid data area of the data signal. A selection circuit is provided for selecting and outputting one of the plurality of clock signals generated by the clock signal generation unit according to a selection signal formed to select a signal.

[0008] Further, there is provided a detection circuit for detecting a delay amount of a plurality of clock signals inputted to the selection circuit and generating a selection signal. Further, a detection circuit is provided for detecting a delay amount of the clock signal output by the selection circuit and generating the selection signal.

The adjustment of the adjusting unit is performed so as to shift the input clock signal forward or backward by a predetermined time. Further, the adjustment unit is configured to generate a plurality of data signals from the input data signal, and to select a data signal in which a predetermined edge of a pulse of the clock signal corresponds to a predetermined position in the valid data area. A selection circuit is provided for selecting and outputting one of the plurality of data signals generated by the data signal generation unit in accordance with the formed selection signal.

[0010] In addition, the adjustment of the adjustment unit is performed so as to shift the input data signal forward or backward for a predetermined time. The predetermined time is a half cycle of the input clock signal or a multiple of the half cycle. Also,
The predetermined time is to select one from a plurality of time amounts formed stepwise.

Further, in the display device according to the present invention, a control circuit for outputting a clock signal and a data signal via an interface circuit, and a drive signal in response to the clock signal and the data signal output from the control circuit And a display unit for displaying by a drive signal output from the drive circuit. The interface circuit is built in the control circuit.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to an interface circuit used for an output section for outputting a clock signal and a data signal to an external circuit (a driver IC in the case of a display device), such as a control circuit of a display device. It has an adjustment unit for adjusting the timing between the clock signal and the data signal. Hereinafter, an interface circuit used for a control circuit of a display device will be described.

Embodiment 1 FIG. FIG. 1 is a voltage waveform diagram at the input of the driver IC of the display device according to the first embodiment of the present invention. FIG. 1A shows a case where the clock signal of FIG. 11A is shifted backward by a half cycle of the clock signal by the interface circuit, and FIG. 1B shows a case where the clock signal is shifted backward by a predetermined time. In both cases, the setup time and the hold time specified by the driver IC are secured. In the figure, 6 to 10 are the same as those in FIG. In the display device according to the first embodiment, when the setup time of the driver IC is not satisfied, the function of the interface circuit that shifts the clock signal backward by a half cycle of the clock signal or one of a plurality of stages of time is selected. By using the function of shifting the clock signal backward by the predetermined time, it is possible to delay the clock signal by the optimum time and to reliably satisfy the specified setup time shown in FIGS. 1 (a) and 1 (b). Become. Therefore, a display device such as a high-quality liquid crystal display device can be obtained.

Next, a circuit configuration for delaying the clock signal will be described. FIG. 2 is a configuration diagram showing a functional block for shifting a signal of the display device according to the first and second embodiments of the present invention, and constitutes an adjustment unit of an interface circuit. FIG. 2A is a diagram in which the clock signal is shifted backward by a half cycle or a multiple of the half cycle of the clock signal, and FIG.
FIG. 4 is a diagram showing a configuration in which one is selected from a plurality of time amounts and shifted backward by a predetermined time.

In the figure, reference numeral 11 denotes an internal clock signal, 1
2 is a clock enable signal, 13 is a selection signal for selecting a clock signal so as to secure a setup time or a hold time, 14 is a clock signal output from an interface circuit of a control circuit in the display device, 1
Reference numeral 5 denotes a clock signal generator for generating a plurality of clock signals having different delay amounts shifted backward by a half cycle or a multiple of the half cycle of the clock signal, and 16 selects one from a plurality of stages of time and determines a predetermined amount. A clock signal generation unit that shifts backward by time and generates a plurality of clock signals having different delay amounts, even if the plurality of stages have the same difference,
Those having different differences may be used. Reference numeral 17 denotes a plurality of clock signals generated by the clock signal generation units 15 and 16, and 17a is a reference clock signal. 18
Is a selection circuit that selects a required clock signal from a plurality of clock signals according to the selection signal 13 and outputs one clock signal 14. Reference numeral 19 denotes a selection point for selecting one of the connections. Note that the plurality of selection signals 13 and clock signals 17 are 13a, 13b, 17a,
17b. NOT circuit 2 described later
0, latch circuit 21, AND circuit 22, and delay circuit 23 are the same.

In FIG. 2A, when the internal clock signal 11 is input to the clock signal generator 15, a different delay amount shifted backward by a half cycle or a multiple of a half cycle with respect to the internal clock signal 11 is shown. , A plurality of clock signals 17a,. . . , 17b are generated. At the same time, the clock enable signal 12 is a signal that determines the area of a clock change in the output signal,
It may be necessary to operate the circuit inside. This example will be described later with reference to FIG. Therefore, in the selection circuit 18, a plurality of clock signals 17a,. . . , 17b
Are set to select a signal that satisfies the setup time and the hold time defined as shown in FIG. . . , 13b. Thus, the plurality of clock signals 17a,. . . , 17b are output as the clock signal 14. Here, clock signals 17a,. . . , 17b include the internal clock signal 11, the dotted line at the selection point 19 is effective. In FIG. 2B, the clock signal generation unit 15 is different from the clock signal generation unit 16 in FIG. 2A except that the clock enable signal 12 is not input.
The only difference is that it has been replaced by That is, when the internal clock signal 11 is input to the clock signal generation unit 16, a plurality of clock signals 17a having different delay amounts shifted backward by a predetermined time from the time amounts of the plurality of stages with respect to the internal clock signal 11, . . . , 17b are generated, and the rest is the same as the operation of FIG. In the selection circuit 18, the setting for selecting a signal that satisfies the setup time and the hold time defined as shown in FIG. . . , 13b. Thereby, the plurality of clock signals 17
a,. . . , 17b are output as the clock signal 14. Here, the dotted line portion at the selection point 19 is the same as that in FIG.

FIG. 3 is a diagram showing a configuration of a circuit for shifting a clock signal of the display device according to the first and second embodiments of the present invention, and shows a specific circuit of FIG.
FIGS. 3A, 3B, and 3C show circuits that realize a function of shifting the clock signal backward by a half cycle of the clock signal. In the figure, 11 to 14, 1
7 to 19 are the same as those in FIG. 20
Is a NOT circuit, 21 is a latch circuit, and 22 is an AND circuit. 19 to 22 constitute the clock signal generation unit 15 of FIG. The function of shifting the clock signal shown in FIG. 3 backward is such that one of the plurality of clock signals 17 having different delay amounts is selected by the selection circuit 18 and output as the clock signal 14.

In FIG. 3A, when the lower dotted line portion at the selection point 19 is enabled, the clock signal 17a
(Reference signal) is the same signal as the internal clock signal 11. The internal clock signal 11 is output from the NOT circuit 20b.
, A clock signal 17b (a signal shifted backward by a half cycle) inverted from the internal clock signal 11 is generated. Therefore, the selection circuit 18
From among the clock signals 17a and 17b, FIG.
The setting for selecting a signal that satisfies the setup time and the hold time specified as shown in FIG. Thereby, the two clock signals 17a and 17b
Is output as the clock signal 14. Here, the case where the lower dotted line portion at the selection point 19 is enabled has been described, but when the upper dotted line portion at the selection point 19 is enabled, the inverted clock signal with respect to the internal clock signal 11 is used. 17a
The difference is that the internal clock signal 11 is the same signal as the clock signal 17b (the signal shifted backward by a half cycle) at the same time that the (reference signal) is generated. FIG. 3 (b)
Then, the clock enable signal 12 for determining the area of the clock change is inputted to the latch circuit 2 shown in FIG.
The difference between the first and second embodiments is that signals having different delay amounts shifted backward by a half cycle are controlled. That is, when the lower dotted line portion at the selection point 19 is enabled, the clock enable signal 12 is input to the latch circuit 21a, so that the voltage waveform shape is the same as that of the clock enable signal 12, and the internal clock signal 11 Is generated in synchronization with the falling edge of. From this, when the output signal of the latch circuit 21a and the internal clock signal 11 are input to the AND circuit 22a, a clock signal 17a (a reference signal) in which a certain clock change area exists is generated. When the output signal of the latch circuit 21a is input to the latch circuit 21b, the input signal has the same voltage waveform shape as the input signal, and a signal synchronized with the rising edge of the internal clock signal 11 (the output signal of the (A signal shifted backward by a half cycle). When the internal clock signal 11 is input to the NOT circuit 20b, a signal inverted from the internal clock signal 11 is generated.
From this, when the output signal of the latch circuit 21b and the output signal of the NOT circuit 20b are input to the AND circuit 22b, the clock signal 17b (the signal shifted backward by a half cycle) in which a certain clock change area exists is generated. Generated. Therefore, the selection circuit 18 inputs a setting for selecting a signal that satisfies the setup time and the hold time defined as shown in FIG. 1A from the two clock signals 17a and 17b by the selection signal 13. I do. As a result, the signal selected from the two clock signals 17a and 17b is output as the clock signal 14. Here, the case where the lower dotted line portion at the selection point 19 is enabled has been described, but when the upper dotted line portion at the selection point 19 is enabled, the internal clock signal 1
The difference is that an internal clock signal 11 is the same as a signal (a signal shifted backward by a half cycle) at the same time that an inverted signal (reference signal) is generated with respect to 1. In FIG. 3C, the operation when the lower dotted line portion at the selection point 19 is enabled in FIG. 3B corresponds to the case where the upper dotted line portion is enabled. This corresponds to the case where the lower dotted line is enabled when the upper dotted line is enabled. That is, the latch circuit 21a,
The circuit components used in the NOT circuit 21b and the NOT circuit 20b are different in polarity, and the rest is the same as the operation in FIG.

FIG. 4 is a diagram showing a configuration of a circuit for shifting a clock signal or a data signal of a display device according to a first embodiment of the present invention and a second embodiment to be described later, and shows a specific circuit of FIG. It is. FIG. 4 (a), FIG. 4 (b)
Shows a circuit configuration for realizing a function of shifting the clock signal backward by a predetermined time. In the figure, 11, 13,
14, 17, and 18 are the same as those in FIG. Reference numeral 23 denotes a delay circuit such as a delay cell, a buffer, or an inverter, which constitutes the clock signal generator 16 shown in FIG.

In FIG. 4A, the clock signal 17a (reference signal) is the same as the internal clock signal 11. Further, when the clock signal 17a is input to the delay circuit 23a, a signal having a certain delay amount (a signal shifted backward by a predetermined time) is generated. Similarly, delay circuits 23b,. . . , 23c to generate a plurality of clock signals 17b (signals shifted backward by a predetermined time) having a certain delay amount. Therefore, in the selection circuit 18, a plurality of clock signals 17a,. . . , 17b, FIG.
The setting for selecting a signal that satisfies the setup time and the hold time defined as shown in FIG.
a,. . . , 13b. Thus, the plurality of clock signals 17a,. . . , 17b are output as the clock signal 14. Here, the circuits 23a, 23b,. . . , 23c are not necessarily circuits having the same delay amount. FIG.
4B, the delay circuits 23a and 23
b, 23c, 23d,. . . , 23e and 23f, the circuit components used are different, and the rest is the same as the operation of FIG. That is, the delay circuits 23a, 23b, 23c,
23d,. . . , 23e and 23f, the amount of delay of the circuit is different, and the rest is the same as the operation of FIG.

In the first embodiment, the function of shifting the clock signal backward by a half cycle of the clock signal or a multiple of the half cycle as shown in FIG. 1 is used, or the clock signal is shifted backward by a predetermined time. By delaying the clock signal by the optimum time, it is possible to reliably satisfy the specified setup time, so that a high-quality display device such as a liquid crystal display device can be obtained.

The case where the clock signal is shifted has been described above. Next, the case where the data signal is shifted by the interface circuit will be described. FIG. 5 is a diagram showing a circuit configuration for shifting the data signal of the display device according to the first and second embodiments of the present invention, and is a specific example of FIG. FIGS. 5A and 5B show a circuit configuration for realizing a function of shifting a data signal forward by a half cycle of a clock signal. In the figure, 11, 13, 18-
Reference numeral 21 is the same as that in FIG. 121
Is an internal data signal, and 141 and 171 are data signals.

In FIG. 5A, when the lower dotted line portion at the selection point 19 is enabled, the internal data signal 121
Is input to the latch circuit 21a, the voltage waveform of the internal data signal 121 is the same as that of the internal data signal 121, and the data signal 171a (a signal shifted forward by a half cycle) synchronized with the falling edge of the internal clock signal 11 is generated. Generated. The output signal of the latch circuit 21a is
As a result, the data signal 171b (reference signal) having the same voltage waveform shape as the input signal and synchronized with the rising edge of the internal clock signal 11 is generated. Therefore, the selection circuit 18 inputs a setting for selecting a signal that satisfies the setup time and the hold time defined as shown in FIG. 1A from the two data signals 171a and 171b by the selection signal 13. I do. As a result, the signal selected from the two data signals 171a and 171b is output as the data signal 141. Here, the case where the lower dotted line portion at the selection point 19 is enabled has been described. However, when the upper dotted line portion at the selection point 19 is enabled, a signal inverted from the internal clock signal 11 is output. The difference is that a signal used as a clock input (a signal shifted forward by a half cycle) is generated, and at the same time, a signal (reference signal) using the internal clock signal 11 as a clock input is generated. In FIG. 5B, the operation when the lower dotted line portion at the selection point 19 is enabled in FIG. 5A corresponds to the case where the upper dotted line portion is enabled. The operation when the upper dotted line is enabled corresponds to the case where the lower dotted line is enabled. That is, the polarities of the circuit components used in the latch circuits 21a and 21b are different, and the rest is the same as the operation in FIG.

The function of shifting the data signal shown in FIG. 5 to the front is performed by selecting one of the plurality of data signals 171 having different delay amounts by the selection circuit 18 and outputting it as the data signal 141. Note that a circuit that realizes a function of shifting a data signal forward by a predetermined time can be realized by using the circuit in FIG. 4 and inputting a data signal instead of a clock signal. Instead of a clock signal,
Use the function to shift the data signal forward by a half cycle of the clock signal or a multiple of the half cycle, or use the function to select one of the time amounts of multiple stages and shift it forward by a predetermined time, Is advanced forward by the optimum time, and as a result, the same effect as delaying the clock signal by the optimum time can be obtained.

Embodiment 2 The second embodiment realizes a function of shifting a clock signal forward. FIG.
FIG. 8 is a voltage waveform diagram at the input of the driver IC of the display device according to the second embodiment of the present invention. In the figure, 6
10 to 10 are the same as those in FIG. FIG.
Is a voltage waveform diagram of a signal input to the driver IC through a function of an interface circuit for shifting a clock signal output by a control circuit of the display device forward by a half cycle of the clock signal or a function of shifting the clock signal forward by a predetermined time; Then, FIG. 6 (a)
FIG. 6B shows a case where the function of shifting the clock signal forward by a half cycle of the clock signal in the example where the hold time is not satisfied (FIG. 11B) is used, and FIG. Is selected, and the function of shifting forward by a predetermined time is used.

In an example in which the hold time is not satisfied, the clock signal is shifted forward by a half cycle or a multiple of the half cycle of the clock signal, or by using a function of shifting the clock signal forward by a predetermined time. 6A and 6B, it is possible to reliably satisfy the hold time specified by the driver IC as shown in FIG. 6A and FIG. Can be obtained. Also,
In the interface circuit, instead of advancing the clock signal, use the function to shift the data signal backward by a half cycle of the clock signal or a multiple of the half cycle, or select one from multiple stages of time and specify By delaying the data signal by the optimum time by using the function of shifting the clock signal backward by the time, the same effect as the advancement of the clock signal by the optimum time can be obtained as a result.

The circuit for realizing the function of shifting the clock signal forward according to the second embodiment can be obtained by the same circuit as that shown in FIGS. Here, in FIG. 2, the clock signal generation unit 15 generates a clock signal shifted forward by a half cycle or a multiple of a half cycle, and the clock signal generation unit 16 calculates One is selected to generate a clock signal shifted forward by a predetermined time. Further, a circuit for realizing the function of shifting the data signal backward according to the second embodiment can be obtained by a circuit similar to that shown in FIGS.

Embodiment 3 In the third embodiment, the interface circuit switches between shifting the clock signal forward or backward. FIG. 7 is a configuration diagram showing a functional block for shifting a clock signal of the display device according to the third embodiment of the present invention, and constitutes an adjustment unit of an interface circuit. FIG. 7A is configured to be shifted forward or backward by a half cycle or a multiple of the half cycle of the clock signal, and FIG. 7B is configured to be shifted forward or backward by a predetermined time. . In the figure, 11 to 19 are the same as those in FIG. 24 is a clock signal 14 for automatically selecting whether to shift the clock signal forward or backward.
And outputs the selection signal 13 to the selection circuit 18. Reference numeral 25 denotes a clock signal automatically selected by the detection circuit 24. FIG. 7 shows the selection circuit 1
8 is connected to the input of the detection circuit 24.

FIG. 8 is a block diagram showing a functional block for shifting a clock signal of a display device according to a third embodiment of the present invention, and constitutes an adjusting section of an interface circuit. FIG. 8A shows a configuration in which the clock signal is shifted forward or backward by a half cycle or a multiple of the half cycle.
FIG. 8B is configured to shift forward or backward by a predetermined time. In the figure, 11 to 19 are the same as those in FIG. A detection circuit 24 detects the amount of delay of the clock signal 17 in order to automatically select whether to shift the clock signal forward or backward, and outputs a selection signal 13 to the selection circuit 18. FIG.
Is a configuration in which the input unit of the detection circuit 24 is connected to the input unit of the selection circuit 18.

In the third embodiment, the interface circuit determines whether the clock signal is shifted forward or backward.
The detection circuit 24 detects the delay amount of the clock signal to form the selection signal 13 and automatically selects the selection signal 13, thereby automatically switching the function of advancing or delaying the clock signal by an optimum amount of time. As shown in FIG. 1 (a),
As shown in FIG. 1B, FIG. 6A, and FIG. 6B, it is possible to reliably satisfy the setup time and the hold time. Thus, a display device such as a high-quality liquid crystal display device can be obtained.

In the first to third embodiments,
Although the interface circuit used for the output unit of the control circuit of the display device has been described, the interface circuit is not limited to the display device and has an output unit that outputs a data signal and a clock signal to an external circuit. As long as the setup time and the hold time need to be ensured in the external circuit in the device, it can be applied and the same effect can be obtained.

[0032]

Since the present invention is configured as described above, it has the following effects. A clock signal formed with a periodic pulse and a data signal constituted by a valid data area are input, and the pulse is adjusted so that a predetermined edge of the pulse of the clock signal corresponds to a predetermined position in the valid data area of the data signal. Since the adjusting unit for outputting the adjusted clock signal and data signal is provided, the setup time and the hold time of the data signal can be secured. The adjusting unit includes a clock signal generating unit that generates a plurality of clock signals having different delay amounts from the input clock signal, and a clock in which a predetermined edge of the pulse corresponds to a predetermined position in the valid data area of the data signal. A selection circuit that selects and outputs one of the plurality of clock signals generated by the clock signal generation unit in accordance with the selection signal formed to select the signal, so that the setup time and the hold time of the data signal are provided. Can be secured.

Further, since the detection circuit for detecting the delay amount of the plurality of clock signals input to the selection circuit and generating the selection signal is provided, the delay control of the clock signal can be automatically performed. Furthermore, since a detection circuit for detecting the delay amount of the clock signal output by the selection circuit and generating the selection signal is provided, the delay control of the clock signal can be automatically performed.

Further, since the adjustment of the adjusting unit is performed such that the input clock signal is shifted forward or backward by a predetermined time, the clock signal is formed so that the setup time and the hold time of the data signal can be secured. be able to. Further, the adjustment unit is configured to generate a plurality of data signals from the input data signal, and to select a data signal in which a predetermined edge of a pulse of the clock signal corresponds to a predetermined position in the valid data area. Since there is a selection circuit for selecting and outputting one of the plurality of data signals generated by the data signal generation unit according to the formed selection signal, the setup time and the hold time of the data signal can be secured. .

In addition, since the adjustment of the adjustment unit is performed so as to shift the input data signal forward or backward by a predetermined time, the clock signal is formed so that the setup time and the hold time of the data signal can be secured. can do. Further, since the predetermined time is a half cycle or a multiple of a half cycle of the input clock signal, the clock signal can be formed so that the setup time and the hold time of the data signal can be secured. Also,
Since the predetermined time is selected from a plurality of time amounts formed stepwise, the clock signal can be formed so that the setup time and the hold time of the data signal can be secured.

A control circuit for outputting a clock signal and a data signal via an interface circuit;
A drive circuit that outputs a drive signal in accordance with a clock signal and a data signal output from the control circuit, and a display unit that performs display by the drive signal output from the drive circuit include a setup time for a data signal in the driver IC. And hold time can be secured. Further, the interface circuit can be built in the control circuit.

[Brief description of the drawings]

FIG. 1 is a voltage waveform diagram at an input of a driver IC of a display device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a functional block for shifting a clock signal of the display device according to the first embodiment and a second embodiment of the present invention;

FIG. 3 is a diagram showing a circuit configuration for shifting a clock signal of the display device according to the first and second embodiments of the present invention.

FIG. 4 is a diagram showing a circuit configuration for shifting a clock signal or a data signal of the display device according to the first and second embodiments of the present invention.

FIG. 5 is a diagram showing a circuit configuration for shifting a data signal of the display device according to the first and second embodiments of the present invention.

FIG. 6 is a voltage waveform diagram at the input of a driver IC of a display device according to a second embodiment of the present invention.

FIG. 7 is a configuration diagram showing a functional block for shifting a clock signal of a display device according to a third embodiment of the present invention.

FIG. 8 is a configuration diagram showing a functional block for shifting a clock signal of a display device according to a third embodiment of the present invention.

FIG. 9 is a configuration diagram showing a conventional display device.

FIG. 10 is a voltage waveform diagram at the input of a driver IC of a conventional display device.

FIG. 11 is a voltage waveform diagram at the input of a driver IC of a conventional display device.

[Explanation of symbols]

4 control circuit, 6, 14, 17, 25 clock signal, 7 data signal, 8 setup time, 9
Hold time, 11 internal clock signal, 12 clock enable signal, 13 selection signal, 15, 16 clock signal generator, 18 selection circuit, 20 NOT circuit, 21 latch circuit, 22 AND circuit, 23
Delay circuit, 24 detection circuit.

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Claims (11)

[Claims] 1. A clock signal formed by a periodic pulse and a data signal composed of a valid data area are inputted, and a predetermined edge of the pulse of the clock signal corresponds to a predetermined position in the valid data area of the data signal. An interface circuit comprising an adjustment unit that adjusts the clock signal and the data signal that have been adjusted as described above. 2. An adjusting unit, comprising: a clock signal generating unit configured to generate a plurality of clock signals having different delay amounts from an input clock signal, wherein a predetermined edge of a pulse corresponds to a predetermined position in a valid data area of the data signal. A selection circuit configured to select and output one of the plurality of clock signals generated by the clock signal generation unit according to a selection signal formed to select a clock signal to be output. 2. The interface circuit according to 1. 3. The interface circuit according to claim 2, further comprising a detection circuit that detects a delay amount of a plurality of clock signals input to the selection circuit and generates a selection signal. 4. The interface circuit according to claim 2, further comprising a detection circuit for detecting a delay amount of a clock signal output by the selection circuit and generating a selection signal. 5. The interface circuit according to claim 1, wherein the adjusting unit adjusts the input clock signal forward or backward by a predetermined time. 6. A data signal generating unit for generating a plurality of data signals from an input data signal, wherein the adjusting unit selects a data signal in which a predetermined edge of a pulse of a clock signal corresponds to a predetermined position in a valid data area. 2. The interface circuit according to claim 1, further comprising a selection circuit for selecting and outputting one of the plurality of data signals generated by the data signal generation unit according to the selection signal formed as described above. 7. The interface circuit according to claim 6, wherein the adjustment of the adjustment unit is performed so as to shift an input data signal forward or backward by a predetermined time. 8. The interface circuit according to claim 5, wherein the predetermined time is a half cycle of the input clock signal or a multiple of the half cycle. 9. The interface circuit according to claim 5, wherein the predetermined time is one selected from a plurality of time amounts formed stepwise. 10. A control circuit for outputting a clock signal and a data signal via the interface circuit according to claim 1, and a drive circuit according to the clock signal and the data signal output from the control circuit. A display device, comprising: a driving circuit that outputs a signal; and a display portion that performs display using the driving signal output by the driving circuit. 11. The display device according to claim 10, wherein the interface circuit is built in the control circuit.