JP2000075839A - Driving method of liquid crystal display device - Google Patents

Driving method of liquid crystal display device

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Publication number
JP2000075839A
JP2000075839A JP10244298A JP24429898A JP2000075839A JP 2000075839 A JP2000075839 A JP 2000075839A JP 10244298 A JP10244298 A JP 10244298A JP 24429898 A JP24429898 A JP 24429898A JP 2000075839 A JP2000075839 A JP 2000075839A
Authority
JP
Japan
Prior art keywords
liquid crystal
signal
correction pulse
scanning
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10244298A
Other languages
Japanese (ja)
Inventor
Masahito Hara
將人 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP10244298A priority Critical patent/JP2000075839A/en
Publication of JP2000075839A publication Critical patent/JP2000075839A/en
Pending legal-status Critical Current

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  • Liquid Crystal Display Device Control (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent crosstalk from occurring. SOLUTION: In the driving method of the liquid crystal display device, a liquid crystal panel of a simple matrix system where plural scanning electrodes and plural signal electrodes are intersected and the intersections are made to be pixels, is provided with a correction pulse impression means for impressing a correction pulse to make a selection pulse on the scanning electrode at the previous stage to be non-selective according to the difference between the number a of turned-on pixels on the scanning electrodes of the previous stage and the number b of turned-on pixels on the following scanning electrodes, and if a>b, the correction pulse is increased in width, while, if a<b, the correction pulse is decreased in width.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は単純マトリックス方
式の液晶パネルを備えた液晶表示装置の駆動方法に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a liquid crystal display device having a simple matrix type liquid crystal panel.

【0002】[0002]

【従来の技術】単純マトリックス方式の液晶表示装置に
おいては、走査用基板と信号用基板とを、それぞれに配
列された複数の透明電極が交差するように対向配設さ
せ、双方の基板間に液晶を封入し、これによって表示領
域となし、そして、走査側の透明電極(走査電極)と信
号側の透明電極(信号電極)に電圧平均化法でもって電
圧印加することで画像表示をおこなっている。
2. Description of the Related Art In a simple matrix type liquid crystal display device, a scanning substrate and a signal substrate are opposed to each other so that a plurality of transparent electrodes arranged therein intersect with each other. To form a display area, and an image is displayed by applying a voltage to the transparent electrode on the scanning side (scanning electrode) and the transparent electrode on the signal side (signal electrode) by a voltage averaging method. .

【0003】[0003]

【発明が解決しようとする課題】しかしながら、単純マ
トリクス方式の液晶表示パネルでは、走査電極と信号電
極との交差部である画素に容量を生じることで、それに
起因する電極のインピーダンスによりクロストークと呼
ばれる表示むらが発生していた。
However, in a liquid crystal display panel of a simple matrix system, a capacitance is generated in a pixel which is an intersection of a scanning electrode and a signal electrode. Display unevenness was occurring.

【0004】図6はクロストークの表示パターンの典型
例である。液晶表示パネルの全表示領域において、無地
(c)を背景にして、方形状の黒部分を表示した場合
に、画面全体のクロストークの発生状態を(a)と
(b)でもって示し、双方ともに走査電極1ライン分の
幅である。
FIG. 6 shows a typical example of a crosstalk display pattern. In the entire display area of the liquid crystal display panel, when a rectangular black portion is displayed against the plain (c) as a background, the occurrence of crosstalk on the entire screen is indicated by (a) and (b). Both are the width of one line of the scanning electrode.

【0005】走査電極側において、クロストークは白
(点灯)画素数が減少する境界(黒部分の上辺)に沿っ
て発生しており、点灯数の多い側の走査電極で構成され
る画素がより明るくなる。他方、白(点灯)画素数が増
加する境界(黒部分の下辺)に沿っても発生しており、
点灯数の少ない側の走査電極で構成される画素がより暗
くなる。すなわち、走査電極上の点灯画素の数が変化す
る場合、走査方向の流れからみて、変化前を前段の走査
電極、変化後を次段の走査電極とすると、前段の走査電
極の方が点灯数が多い場合には、前段の走査電極上の画
素は明るくなり、前段の走査電極の方が点灯数が少ない
と、前段の走査電極が暗くなる。
On the scanning electrode side, crosstalk occurs along the boundary (the upper side of the black portion) where the number of white (lighting) pixels decreases, and pixels constituted by the scanning electrodes on the side with the higher number of lightings are more likely. It becomes bright. On the other hand, it also occurs along the boundary where the number of white (lit) pixels increases (the lower side of the black portion)
Pixels formed by the scanning electrodes on the side with the smaller number of lightings become darker. That is, when the number of illuminated pixels on the scanning electrode changes, if the change in the scanning direction indicates that the pre-change scan electrode is the previous scan electrode and the post-change scan electrode is the next scan electrode, the previous scan electrode has a higher turn-on number. When there are many pixels, the pixels on the preceding scanning electrodes become brighter, and when the number of lightings of the preceding scanning electrodes is smaller, the preceding scanning electrodes become darker.

【0006】上記のようなクロストークは液晶駆動電圧
の波形の歪みによって発生するが、走査選択電圧パルス
の立ち上がり時、または立ち下がり時において同期して
信号電圧が変化することで、走査選択電圧パルスが静電
容量結合によって誘導され、そのために駆動電圧の波形
に歪みが生じてクロストークが発生する。
[0006] The crosstalk as described above is caused by the distortion of the waveform of the liquid crystal drive voltage. The signal voltage changes synchronously at the time of rising or falling of the scanning selection voltage pulse, and thus the scanning selection voltage pulse is changed. Is induced by capacitive coupling, which causes a distortion in the waveform of the drive voltage and causes crosstalk.

【0007】したがって本発明の目的はクロストークが
発生しないように、あるいはその影響を小さくすること
にある。
Accordingly, an object of the present invention is to prevent crosstalk from occurring or to reduce the influence thereof.

【0008】[0008]

【課題を解決するための手段】本発明の液晶表示装置の
駆動方法は、複数の走査電極と複数の信号電極とを交差
させ、その交差部を画素となした単純マトリクス方式の
液晶パネルに、前段の走査電極における画素の点灯数a
と次段の走査電極における画素の点灯数bとの差に応じ
て前段の走査電極での選択パルスに対し非選択とするた
めの補正パルスを印加する補正パルス印加手段を設け、
a>bでは補正パルスの幅を広げ、a<bでは補正パル
スの幅を狭めるようにしたことを特徴とする。
According to the driving method of the liquid crystal display device of the present invention, a simple matrix type liquid crystal panel in which a plurality of scanning electrodes and a plurality of signal electrodes are crossed and the crossing portions are pixels is provided. Lighting number a of pixels in the preceding scanning electrode a
And a correction pulse applying means for applying a correction pulse for deselecting a selection pulse in the previous scanning electrode according to a difference between the lighting number b of the pixel in the next scanning electrode and
When a> b, the width of the correction pulse is widened, and when a <b, the width of the correction pulse is narrowed.

【0009】[0009]

【発明の実施の形態】以下、本発明を図1〜図5により
詳述する。図1は液晶表示装置の概略構成を示し、図2
は信号波形のタイミングを示す。図3はDISP信号制
御回路の回路ブロックであり、図4はDISP信号制御
回路のタイミングチヤートを示す。図5は点灯表示の一
例を示す概略図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to FIGS. FIG. 1 shows a schematic configuration of a liquid crystal display device, and FIG.
Indicates the timing of the signal waveform. FIG. 3 is a circuit block diagram of the DISP signal control circuit, and FIG. 4 shows a timing chart of the DISP signal control circuit. FIG. 5 is a schematic diagram showing an example of the lighting display.

【0010】図1において、1は液晶パネル、2は信号
電極駆動回路、3は走査電極駆動回路であり、液晶パネ
ル1によれば、信号電極X1、X2・・・Xn−1、X
n・・・と走査電極Yl、Y2・・・Yn−1、Yn・
・・とがマトリクス状に直交して配設されている。信号
電極X1、X2・・・Xn−1、Xn・・・は信号電極
駆動回路2により駆動され、他方の走査電極Yl、Y2
・・・Yn−1、Yn・・・は走査電極駆動回路3によ
って駆動される。
In FIG. 1, reference numeral 1 denotes a liquid crystal panel, 2 denotes a signal electrode driving circuit, and 3 denotes a scanning electrode driving circuit. According to the liquid crystal panel 1, signal electrodes X1, X2,.
n and scanning electrodes Yl, Y2 ... Yn-1, Yn
Are arranged orthogonally in a matrix. The signal electrodes X1, X2,..., Xn-1, Xn are driven by the signal electrode driving circuit 2, and the other scanning electrodes Y1, Y2
,... Yn−1, Yn.

【0011】このような単純マトリックス型液晶表示装
置においては、走査用基板に配列された透明電極群(走
査電極Yl、Y2・・・Yn−1、Yn・・・)と、信
号用基板に配列された透明電極群(信号電極X1、X2
・・・Xn−1、Xn・・・)とを交差させ、さらに走
査用基板と信号用基板との間にTNまたはSTNの液晶
を封入し、表示領域となす。そして、信号電極駆動回路
2および走査電極駆動回路3とでもって電圧平均化法に
より電圧印加する。
In such a simple matrix type liquid crystal display device, a transparent electrode group (scanning electrodes Y1, Y2... Yn-1, Yn...) Arranged on a scanning substrate and a transparent electrode group arranged on a signal substrate are arranged. Transparent electrode group (signal electrodes X1, X2
.. Xn-1, Xn...), And TN or STN liquid crystal is sealed between the scanning substrate and the signal substrate to form a display area. Then, the signal electrode driving circuit 2 and the scanning electrode driving circuit 3 apply a voltage by a voltage averaging method.

【0012】また、走査電極Yl、Y2・・・Yn−
1、Yn・・・と信号電極X1、X2・・・Xn−1、
Xn・・・の交差部にて示す白丸と黒丸は液晶パネル1
の点灯状態を模式的に示すものであり、白丸は点灯、黒
丸は非点灯である。たとえば走査電極Ylで駆動される
ラインはすべて点灯、走査電極Y2で駆動されるライン
はすべて非点灯である。
The scanning electrodes Y1, Y2,...
1, Yn... And signal electrodes X1, X2.
The white and black circles shown at the intersections of Xn...
The white circles are lit, and the black circles are non-lighted. For example, all the lines driven by the scanning electrode Yl are turned on, and all the lines driven by the scanning electrode Y2 are not turned on.

【0013】信号電極駆動回路2には液晶表示データ信
号DATA、液晶表示データ信号DATAを内部シフト
レジスタに取り込むシフトクロックCP、シフトレジス
タのデータを出力回路にラツチする信号LOAD、表示
イネーブル信号DISPINを入力する。これらの信号
は液晶パネル制御回路(図示せず)より出力する。
The signal electrode drive circuit 2 receives a liquid crystal display data signal DATA, a shift clock CP for taking the liquid crystal display data signal DATA into an internal shift register, a signal LOAD for latching data of the shift register to an output circuit, and a display enable signal DISPIN. I do. These signals are output from a liquid crystal panel control circuit (not shown).

【0014】走査電極駆動回路3には走査電極Yl、Y
2・・・Yn−1、Yn・・・を選択するためのシフト
レジスタの入カデータ信号FRAMと、シフトレジスタ
のシフトクロックLOADとを液晶パネル制御回路(図
示せず)より入力する。なお、走査電極駆動回路3と信
号電極駆動回路2に入力するLOADは同一の信号であ
る。
The scanning electrode driving circuit 3 has scanning electrodes Yl, Y
The input data signal FRAM of the shift register and the shift clock LOAD of the shift register for selecting 2 ... Yn-1, Yn ... are input from a liquid crystal panel control circuit (not shown). Note that LOAD input to the scan electrode drive circuit 3 and the signal electrode drive circuit 2 are the same signal.

【0015】また、走査電極駆動回路3にはDISP信
号制御回路5からDISPOUT信号を入力する。DI
SP信号制御回路5には発振回路4よりクロックCLK
を入力する。さらにDISP信号制御回路5には液晶パ
ネル制御回路(図示せず)よりDISPIN信号を入力
する。なお、液晶パネル制御回路5と信号電極駆動回路
2に入力するDISPIN信号は同一である。
The scan electrode drive circuit 3 receives a DISPOUT signal from the DISP signal control circuit 5. DI
The clock signal CLK from the oscillation circuit 4 is supplied to the SP signal control circuit 5.
Enter Further, the DISP signal control circuit 5 receives a DISPIN signal from a liquid crystal panel control circuit (not shown). Note that the DISPIN signal input to the liquid crystal panel control circuit 5 and the signal electrode drive circuit 2 is the same.

【0016】つぎに上記構成の液晶表示装置における信
号波形のタイミングを図2に示す。走査電極の選択パル
スは非選択期間の間において、電圧V2であり、選択期
間のLOADの立ち下がりから立ち下がりの間にて電圧
V0となる。信号電極については、ラッチしたDATA
信号がハイ(H)のとき、その出力は電圧V3となり、
ラツチしたDATA信号がロー(L)のとき、その出力
はVlの電圧レベルとなる。
FIG. 2 shows timings of signal waveforms in the liquid crystal display device having the above configuration. The selection pulse of the scan electrode is at the voltage V2 during the non-selection period, and becomes the voltage V0 between the fall and the fall of LOAD during the selection period. For the signal electrode, the latched DATA
When the signal is high (H), its output is at voltage V3,
When the latched DATA signal is low (L), its output is at the voltage level Vl.

【0017】そして、選択期間に液晶に実際に印加され
る電圧に関し、ラッチしたDATA信号がLのとき、V
0−V3で点灯し、V0−V1で非点灯となる。たとえ
ば、図1においてYlで選択されるラインはすべて点灯
状態なので、Y1が選択されている期間、信号電極X
1、X2・・・Xn−1、Xn・・・は、すべて電圧V
3を出力し、Y2で選択されるラインはすべて非点灯状
態なので、Y2が選択されている期間、信号電極X1、
X2・・・Xn−1、Xn・・・は、すべて電圧V1を
出力する。また、Yn−1が選択される期間、信号電極
X1、X2はVlを出力し、信号電極Xn−1、Xnは
V0を出力する。
With respect to the voltage actually applied to the liquid crystal during the selection period, when the latched DATA signal is L, V
It turns on at 0-V3 and turns off at V0-V1. For example, since all the lines selected by Y1 in FIG.
1, X2... Xn-1, Xn.
3 is output and all the lines selected by Y2 are in the non-lighting state.
Xn... Xn-1, Xn... All output the voltage V1. Also, during the period when Yn-1 is selected, the signal electrodes X1 and X2 output Vl, and the signal electrodes Xn-1 and Xn output V0.

【0018】図3はDISP信号制御回路の回路ブロッ
クを示す。累積加算回路ブロックは、入力されたDAT
A信号をCP信号の立ち下がりでラッチし、ラツチされ
たDATA信号のLレベルのみの加算をおこなう。つぎ
のCPの立ち下がりでも同様にDATA信号のラツチと
Lレベルのみの加算をおこなう。それを同時に前のCP
の立ち下がりでの加算結果に加える。これを繰り返し1
ライン分のLデーダの累積加算をおこなう。1ライン分
の累積加算結果は、ラッチ回路1に格納される。このラ
ッチ回路1へのラッチクロックはCP信号をカウンタで
1ライン分カウントして生成したパルスを使う。このラ
ツチ回路1の結果は、つぎのLOAD信号の立ち下がり
でラツチ回路2にラッチされる。ラッチ回路1に累積加
算回路の1ライン分の結果がラツチされた時点で、ラツ
チ回路1の出力とラッチ回路2の出力とが、比較回路で
比較される。この比較はラツチ回路1の出力からラッチ
回路2の出力を減算することでおこない、比較回路から
の出力は正負の極性信号と絶対値の出力からなる。そし
て、比較した結果をデコーダ回路によって補正パルス幅
のクロック数にデコードする。
FIG. 3 shows a circuit block of the DISP signal control circuit. The accumulator circuit block receives the input DAT
The A signal is latched at the falling edge of the CP signal, and only the L level of the latched DATA signal is added. Similarly, only the latch of the DATA signal and the L level are added at the fall of the next CP. At the same time, the previous CP
Is added to the addition result at the falling edge of. Repeat this 1
Cumulative addition of L data for the line is performed. The cumulative addition result for one line is stored in the latch circuit 1. As a latch clock to the latch circuit 1, a pulse generated by counting the CP signal for one line by a counter is used. The result of the latch circuit 1 is latched by the latch circuit 2 at the next fall of the LOAD signal. When the result of one line of the accumulating circuit is latched in the latch circuit 1, the output of the latch circuit 1 and the output of the latch circuit 2 are compared by a comparison circuit. This comparison is performed by subtracting the output of the latch circuit 2 from the output of the latch circuit 1. The output from the comparison circuit is composed of positive and negative polarity signals and an absolute value output. Then, the result of the comparison is decoded by the decoder circuit to the number of clocks of the correction pulse width.

【0019】前記補正パルス印加手段としてのDISP
パルスタイミング回路(DISP補正パルス制御回路)
には、発振回路で生成されたクロックCLKが入力され
る。また、ラッチ回路1のラッチクロックを基準にクロ
ックCLKのカウントを開始するカウンタがあり、その
カウント値とデコード回路の出力結果を比較して、デコ
ード回路の出力結果の期間の幅をもつパルスを生成す
る。このパルスと通常のDISP信号を重畳し、デコー
ド回路の出力結果の期間DISP信号をLレベルにす
る。
DISP as the correction pulse applying means
Pulse timing circuit (DISP correction pulse control circuit)
Is supplied with a clock CLK generated by the oscillation circuit. Also, there is a counter which starts counting the clock CLK based on the latch clock of the latch circuit 1, and compares the count value with the output result of the decode circuit to generate a pulse having the width of the output result period of the decode circuit. I do. This pulse and a normal DISP signal are superimposed, and the DISP signal is set to L level during the period of the output result of the decoding circuit.

【0020】図4はDISP信号制御回路のタイミング
チヤートを示し、Yn−1で駆動されるDATAのLレ
ベルが累漬加算され、Ynのデータ入力期間の終了とと
もにラッチされる。つぎにYnのデータ入力期間で、Y
nで駆動されるDATAのLレベルが累積加算され、Y
nのデータ入力期間の終了と共にラッチされる。同時
に、Yn−1のLレベルデータの累積加算結果とYnの
Lレベルデータの累積加算結果が比較され、その結果、
適当なクロック数の幅のパルスが補正パルスとして、Y
nのデータ入力期間の直後にDISPOUT信号に重畳
される。
FIG. 4 shows a timing chart of the DISP signal control circuit. The L level of DATA driven by Yn-1 is added and latched at the end of the data input period of Yn. Next, in the data input period of Yn, Y
L level of DATA driven by n is cumulatively added, and Y
Latched at the end of the n data input period. At the same time, the cumulative addition result of the Yn-1 L level data and the cumulative addition result of the Yn L level data are compared, and as a result,
A pulse having a width of an appropriate number of clocks is used as a correction pulse,
Immediately after the n data input period, it is superimposed on the DISPOUT signal.

【0021】上記構成の駆動方法によれば、走査電極Y
n−1の選択パルスは、補正パルスの期間においてV2
レベルを選択し、液晶に印加される実効電圧をさげる方
向に作用するが、この補正パルスの幅を点灯数の変化に
応じて、調節することにより、すなわち図5に示すよう
に走査電極における画素の点灯数aと次段の走査電極に
おける画素の点灯数bとの関係において、a>bでは補
正パルスの幅を広くし、a<bでは補正パルスの幅を狭
くすることで、液晶に印加される実効電圧を制御するこ
とができ、その結果、クロストークのない良好な表示を
得られた。
According to the driving method having the above structure, the scanning electrode Y
The n-1 selection pulse is V2 during the period of the correction pulse.
The level is selected and acts in the direction of decreasing the effective voltage applied to the liquid crystal. By adjusting the width of this correction pulse in accordance with the change in the number of lightings, that is, as shown in FIG. In the relationship between the lighting number a of the pixel and the lighting number b of the pixel in the next scanning electrode, the width of the correction pulse is increased when a> b, and the width of the correction pulse is narrowed when a <b. As a result, a good display without crosstalk was obtained.

【0022】[0022]

【発明の効果】以上のとおり、本発明の液晶表示装置の
駆動方法によれば、単純マトリクス方式の液晶パネル
に、前段の走査電極における画素の点灯数aと次段の走
査電極における画素の点灯数bとの差に応じて前段の走
査電極での選択パルスに対し非選択とするための補正パ
ルスを印加する補正パルス印加手段を設け、a>bでは
補正パルスの幅を広げ、a<bでは補正パルスの幅を狭
めるようにしたことで、液晶に印加される実効電圧を制
御することができ、その結果、クロストークのない良好
な表示を得られた。
As described above, according to the driving method of the liquid crystal display device of the present invention, the lighting number a of the pixel in the preceding scanning electrode and the lighting of the pixel in the next scanning electrode are provided in the simple matrix type liquid crystal panel. Correction pulse applying means for applying a correction pulse for making the selection pulse in the preceding scanning electrode non-selective according to the difference from the number b is provided. When a> b, the width of the correction pulse is increased, and a <b By narrowing the width of the correction pulse, the effective voltage applied to the liquid crystal could be controlled, and as a result, a favorable display without crosstalk was obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】液晶表示装置の概略を示す説明図である。FIG. 1 is an explanatory view schematically showing a liquid crystal display device.

【図2】信号波形のタイミングチャート図である。FIG. 2 is a timing chart of a signal waveform.

【図3】DISP信号制御回路の回路ブロック図であ
る。
FIG. 3 is a circuit block diagram of a DISP signal control circuit.

【図4】DISP信号制御回路のタイミングチヤート図
である。
FIG. 4 is a timing chart of a DISP signal control circuit.

【図5】液晶表示装置の点灯表示の一例および補正パル
スを示す概略図である。
FIG. 5 is a schematic diagram showing an example of a lighting display of the liquid crystal display device and a correction pulse.

【図6】クロストークの発生を示す概略図である。FIG. 6 is a schematic diagram illustrating occurrence of crosstalk.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】複数の走査電極と複数の信号電極とを交差
させ、その交差部を画素となした単純マトリクス方式の
液晶パネルに、前段の走査電極における画素の点灯数a
と次段の走査電極における画素の点灯数bとの差に応じ
て前段の走査電極での選択パルスに対し非選択とするた
めの補正パルスを印加する補正パルス印加手段を設け、
a>bでは補正パルスの幅を広げ、a<bでは補正パル
スの幅を狭めるようにした液晶表示装置の駆動方法。
1. A simple matrix type liquid crystal panel in which a plurality of scanning electrodes and a plurality of signal electrodes intersect and the intersections are pixels, the number of pixels a of the preceding scanning electrodes is lit.
And a correction pulse applying means for applying a correction pulse for deselecting a selection pulse in the previous scanning electrode according to a difference between the lighting number b of the pixel in the next scanning electrode and
A driving method of a liquid crystal display device in which the width of the correction pulse is increased when a> b, and the width of the correction pulse is narrowed when a <b.
JP10244298A 1998-08-31 1998-08-31 Driving method of liquid crystal display device Pending JP2000075839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10244298A JP2000075839A (en) 1998-08-31 1998-08-31 Driving method of liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10244298A JP2000075839A (en) 1998-08-31 1998-08-31 Driving method of liquid crystal display device

Publications (1)

Publication Number Publication Date
JP2000075839A true JP2000075839A (en) 2000-03-14

Family

ID=17116666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10244298A Pending JP2000075839A (en) 1998-08-31 1998-08-31 Driving method of liquid crystal display device

Country Status (1)

Country Link
JP (1) JP2000075839A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011113080A (en) * 2009-11-26 2011-06-09 Chunghwa Picture Tubes Ltd Liquid crystal display device with adaptive charging/discharging time and related driving method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011113080A (en) * 2009-11-26 2011-06-09 Chunghwa Picture Tubes Ltd Liquid crystal display device with adaptive charging/discharging time and related driving method
US8325123B2 (en) 2009-11-26 2012-12-04 Chunghwa Picture Tubes, Ltd. Liquid crystal display device with adaptive charging/discharging time and related driving method
TWI406254B (en) * 2009-11-26 2013-08-21 Chunghwa Picture Tubes Ltd Liquid crystal display device providing adaptive charging/discharging time and related driving method

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