JP2000068973A - Preamble generating method for ofdm and modulation circuit for ofdm - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an orthogonal frequency division multiplex(OFDM) preamble generating method and an OFDM modulation circuit that prevent deterioration in an error rate and detect a symbol timing at a high speed even when preamble signal for AGC is in use. SOLUTION: In the OFDM preamble generating method that generates a burst signal including at least one automatic gain control preamble signal being an OFDM signal used for orthogonal frequency multiplex communication and two synchronizing signals in succession to the preamble signal, the preamble signal and the synchronizing signals are generated based on the same predetermined fixed pattern and a prescribed phase change is given to each latter half of either the preamble signal or the synchronizing signal so as to generate a phase difference of about 180 degrees between the phase of the preamble signal for the latter half area and the phase of a plurality of the synchronizing signals for each latter half area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an orthogonal frequency division multiplexing (OFDM).
The present invention relates to an OFDM preamble generation method and an OFDM modulation circuit applied to a transmission side of a communication system that performs digital wireless communication using a signal.

[0002]

2. Description of the Related Art In communication using OFDM signals,
Information is transmitted using a plurality of carriers (subcarriers) having an orthogonal relationship. Actually, for example, QPSK (Quadrature Phase S)
modulation such as hift keying). Further, the modulated output is subjected to an inverse discrete Fourier transform (IDFT: Inverse Disc).
reate Fourier Transform) to generate an OFDM signal.

[0003] In communication using an OFDM signal, data is usually repeatedly transmitted in a section called a guard interval provided for each OFDM symbol in order to remove the influence of a delayed wave. On the receiving side that demodulates an OFDM signal, synchronization such as detection of DFT (discrete Fourier transform) window timing is required. For the detection of the synchronization, a method utilizing peak detection of a correlation value in a repetitive signal section of a guard interval is generally used.

On the other hand, packet transmission is a method of dividing data into short packet signals and transmitting the divided signal. In packet transmission, when many terminals randomly generate data, information transmission with higher efficiency is possible as compared with the circuit switching type. However, it is necessary to establish synchronization for each packet signal. Usually, a preamble signal arranged at the head of a packet signal is used to establish synchronization. In packet transmission, it is desirable to use a preamble signal that is as short as possible from the viewpoint of transmission efficiency.

Further, if the delay required for establishing the synchronization is too large, the throughput is reduced. Therefore, it is required to perform signal processing as fast as possible in the physical layer, and high-speed symbol timing detection is required for establishing the synchronization. . Conventional OFDM shown in literature (Onishi, et al., “Study on Synchronous System of OFDM Modulation Method for High-Speed Wireless LAN”, IEICE, IEICE Technical Report, RCS97-210)
FIG. 11 shows the configuration of the modulation circuit.

[0006] The circuit shown in FIG.
Shows an OFDM modulation circuit for generating 48 OFDM signals. In this example, DQPSK (Differential Quadrature Ph
ase Shift Keying).

Hereinafter, the OFDM modulation circuit shown in FIG. 11 will be described. The input signal a1 is input to the serial / parallel conversion circuit 1 and divided for each subcarrier. Forty-eight sets of signals output from the serial-parallel conversion circuit 1 are D signals for each subcarrier.
The signal is input to the QPSK modulation circuit 2. Forty-eight sets of signals modulated by the DQPSK modulation circuit 2 are input to the IDFT circuit 3 and subjected to inverse discrete Fourier transform. That is, the signal is converted from a frequency domain to a time domain signal. The 64 sets of signals output from the IDFT circuit 3 are input to the parallel / serial conversion circuit 4.

The 64 sets of signals are output from the parallel / serial conversion circuit 4 as serial signals in order. The arrangement order of the signals output from the parallel-to-serial conversion circuit 4 is determined by the order stored in the read order storage circuit 5 in advance. When transmitting the synchronization signal, the signal output of 64 subcarriers output from the IDFT circuit 3 is read twice and output from the parallel / serial conversion circuit 4 as a synchronization signal. The OFDM signal output from the parallel / serial conversion circuit 4 is D / A
The signal is converted into an analog signal by the conversion circuit 6 and output as a modulated baseband signal.

[0009] The synchronization signal included in the OFDM signal can also serve as a start symbol signal. When a normal data signal is transmitted, a guard interval (GI) is added by operating the reading order of the parallel / serial conversion circuit 4. FIG. 12 shows a configuration example of a signal format for synchronization of a signal transmitted by a conventional OFDM modulation circuit. In the signal format of FIG. 12, an AGC preamble signal is arranged before a synchronization signal. However, no special consideration is given to the relationship between the AGC preamble signal and the synchronization signal.

FIG. 10 shows the configuration of the OFDM demodulation circuit disclosed in the above document. In this OFDM demodulation circuit,
Delay detection is used for signal demodulation. Hereinafter, O in FIG.
The FDM demodulation circuit will be described.

A received signal (OFDM signal) a 301 input to the OFDM demodulation circuit is input to a Tw delay circuit 301. The Tw delay circuit 301 delays an input signal by a predetermined time Tw. The time Tw is the inverse Fourier transform (IDFT) used for modulation and demodulation of the OFDM signal.
And the time width of the Fourier transform (DFT) window.

The signal output from the Tw delay circuit 301 is input to a conjugate complex signal generation circuit 302. Multiplication circuit 30
3 outputs the result of complex multiplication of the conjugate complex signal a303 output from the conjugate complex signal generation circuit 302 and the reception signal a301. The moving average filter 304 includes the multiplication circuit 30
The moving average of Tw time is calculated for the signal output from No.3. The result is input to the square operation circuit 305.
The signal a306 output from the square operation circuit 305 corresponds to a correlation value C between the received signal a301 and the delayed signal a302. The correlation value C is expressed by the following equation (1).

(Equation 1) However, (integer indicating the d sampling points) r _d reception signal, N represents a number of DFT points. * Indicates a conjugate complex. Also, the square operation circuit 306 receives the received signal a301
And outputs a signal indicating the power. Moving average filter 307
Calculates the moving average of the signal output from the square operation circuit 306 for the Tw time. The calculation result is the squared circuit 3
08 to the peak detection circuit 309.

The peak detection circuit 309 includes a square operation circuit 3
Signal peak detection is performed based on the signal output from the signal generator 05 and the signal output from the squaring circuit 308. At the timing of the peak position of the detected signal, the peak detection circuit 30
9 outputs a symbol timing signal a310.
Further, based on the signal output from the moving average filter 304, carrier frequency error detection is performed. The arc tangent circuit 311 calculates the arc tangent (arc tangent) of the input signal and outputs it as a frequency error signal.

The frequency dividing circuit 312 frequency-divides the signal output from the arc tangent circuit 311 by (1 / N). Where N is DFT
The number of points. The conjugate complex signal generation circuit 313 generates a conjugate complex signal of the signal output from the frequency dividing circuit 312. This conjugate complex signal is supplied to a sample-and-hold circuit 314.
Is input to The sample and hold circuit 314 samples and holds the input conjugate complex signal when synchronization is established.

On the other hand, during the detection of the symbol timing and the detection of the frequency error by the above circuit, the reception signal a301
Is delayed by a time Tw by a Tw delay circuit 315, and further delayed by a delay circuit 316 by a time required for signal peak detection. By processing the signal output from the delay circuit 316, it is possible to correct the carrier frequency error at the start symbol start portion for the samples required for peak detection.

The multiplying circuit 317 multiplies the output signal of the sample and hold circuit 314 by the output signal of the delay circuit 316. The DFT window timing control circuit 310
Window timing control is performed based on the symbol timing signal a310, and the control signal a318 is input to the serial / parallel conversion circuit 318. The serial / parallel conversion circuit 318
The serial signal input from the multiplication circuit 317 is converted into a parallel signal. Here, the signal read timing is controlled to remove the repeated component of the guard interval (GI).

The parallel signal output from the serial / parallel conversion circuit 318 is input to a DFT circuit 319, and is converted from an OFDM code into a DQPSK modulated signal for each subcarrier. The DQPSK modulated signal for each subcarrier output from the DFT circuit 319 is
, And input to the parallel-to-serial conversion circuit 321. The parallel / serial conversion circuit 321 converts an input parallel signal into a serial signal.

As described above, the OFDM demodulation circuit detects the symbol timing using the correlation value peak of the synchronization signal transmitted repeatedly.

[0019]

In a wireless communication system, an AGC (Automatic Gain Control) amplifier must be used to receive packets from users having different reception levels. In order to pull in the AGC amplifier, a preamble signal for AGC is added to the head of each packet as shown in FIG.

In the prior art, the symbol timing of the received signal is detected based on the peak value of the correlation value C (formula (1)) of the synchronization signal transmitted twice after the AGC preamble signal. You. However, in the case of a received signal having a format as shown in FIG. 12, the correlation value C between the AGC preamble signal and the synchronization signal does not become zero. Therefore, the 2D signal detected in the OFDM demodulation circuit is
Since the waveform of the correlation value between the two synchronization signals is distorted and the symbol timing detection position fluctuates, the bit error rate (BER) characteristic is degraded.

Further, in the detection based on the peak value using only the synchronization signal, the rise of the correlation value waveform is not sufficiently steep, so that there is a problem that the BER is deteriorated. further,
As described above, since the correlation value waveform is distorted, a hold time for searching for a peak value is required, and there is also a problem that it takes time to detect symbol timing. The present invention solves these problems and provides an OFDM preamble generation method and an OFDM modulation circuit capable of preventing the deterioration of an error rate even when an AGC preamble signal is used and capable of detecting a symbol timing at high speed. The purpose is to do.

[0022]

A first aspect of the present invention is an OFDM signal used in orthogonal frequency division multiplexing communication, wherein the burst signal includes at least one preamble signal for automatic gain control and two succeeding synchronization signals. O to generate
In the FDM preamble generation method, the preamble signal and the synchronization signal are generated based on the same predetermined fixed pattern, and the second half of each of the preamble signal and the synchronization signal is generated. Giving a predetermined phase change to the region, and forming a phase difference of approximately 180 degrees between the phase of the latter half region of the preamble signal and the phase of the latter half region of each of the plurality of synchronization signals. Features.

In the conventional configuration, when the preamble signal for AGC is used, the correlation generated between the preamble signal for AGC and the synchronization signal causes the peak waveform of the correlation detection to be distorted and the error rate to be degraded. The problem was that it took time. Therefore, in the invention of claim 1, this problem is solved by improving the generation of the preamble signal. That is, for one of the preamble signal and the synchronizing signal, a predetermined phase change is applied to the latter half region, and the phase of the latter half region of the preamble signal and the latter half of each of the plurality of synchronization signals are changed. And a phase difference of about 180 degrees is formed between the phase and the phase of the region.

For example, when the synchronizing signal Sync.B (i) is generated on the transmitting side, the phase of the latter half of the AGC preamble signal Sync.A (i) is changed based on the following equation (2). Rotate 180 degrees (π [rad]) to generate synchronization signal Sync.B (i)
Alternatively, if the phase of the latter half of the synchronization signal Sync.B (i) is rotated by 180 degrees based on the following equation (3) to generate the AGC preamble signal Sync.A (i), the AGC preamble signal A phase difference of 180 degrees can be formed between Sync.A (i) and synchronization signal Sync.B (i).

(Equation 2) Here, i is the output point number of the inverse discrete Fourier transform (IDFT) used for the OFDM modulation circuit.
Assume a 4-point IDFT. Actually, both the preamble signal and the synchronization signal can be generated based on the same predetermined fixed pattern, so that the AGC preamble signal Sync.A (i) and the synchronization signal Sync.B (i ) Is generated, it is not necessary to refer to each other's signals, and it is sufficient to simply change the phase of at least one of the signals.

Based on the above equations (2) and (3), AG
C. Preamble signal Sync.A (i) and synchronization signal Sync.B
When (i) is generated, the correlation values of the OFDM signal processed by the OFDM demodulation circuit on the receiving side are respectively shown in FIGS.
Shown in That is, the signals shown in FIGS. 1 and 2 correspond to, for example, the received signal a301 shown in FIG. 12 and the signal a302 delayed by the time Tw. The correlation values shown in FIGS. 1 and 2 correspond to the signal a306 in FIG. Here, Tw is one DFT symbol time.

In the case of the prior art using an arbitrary AGC preamble signal and an arbitrary synchronization signal, the influence of the correlation value C between the AGC preamble signal and the synchronization signal causes
The rise of the correlation value peak becomes gentle, a symbol timing detection error occurs, the BER deteriorates, and a symbol timing detection time is required. In the first aspect, since a phase difference of 180 degrees appears in the second half region of the AGC preamble signal and the synchronization signal, the correlation value between the AGC preamble signal and the synchronization signal that appears at the time difference Tw is very small. Become.

That is, with respect to the correlation values a and b in each integration section shown in FIGS. 1 and 2, the correlation value C can be ideally suppressed to (a = b = 0) by this operation. Can be (C = 1). Accordingly, as shown in FIGS. 1 and 2, the rising edge of the peak waveform of the correlation value used for symbol detection becomes sharp, and high-speed symbol detection becomes possible. In addition, since the correlation values of a and b are suppressed, the influence on the correlation value waveform is reduced, and BER deterioration is reduced.

[0028] The serial-parallel conversion means for performing serial-parallel conversion processing on the input data, the modulation means for modulating the output signal of the serial-parallel conversion means, and the output signal of the modulation means. Which performs inverse discrete Fourier transform on
DFT means, parallel-serial conversion means for performing parallel-to-serial conversion on the output signal of the IDFT means and outputting a time-domain signal, and a guard in which signal repetition occurs for the time-domain signal output from the parallel-serial conversion means A guard interval adding unit for adding an interval section, a preamble signal generating unit for generating a preamble signal having a predetermined time waveform, and an output of the parallel / serial conversion unit so as to follow the preamble signal output by the preamble signal generating unit Output switching means for outputting a signal
In an FDM modulation circuit, OFDM is performed by inverse discrete Fourier transform based on a predetermined fixed pattern in a frequency domain.
A repetition output means for generating a DM signal and repeatedly outputting the OFDM signal over a period of time three times as long as one period of a discrete Fourier transform corresponding to the length of one OFDM signal; For the latter half area of each of the three OFDM signals sequentially output from the output means, the first OFDM signal and the second and third ODM signals are output.
A phase calculating means for providing a phase difference of about 180 degrees with an FDM signal;

According to a second aspect of the present invention, the repetitive output means provided in the preamble signal generation means generates an OFDM signal by inverse discrete Fourier transform based on a predetermined fixed pattern in a frequency domain, and generates one OFDM signal.
The OF is transmitted for at least three times the time of one cycle of the discrete Fourier transform corresponding to the length of the FDM signal.
The DM signal is output repeatedly.

Further, the phase calculating means is provided between the first OFDM signal and the second and third OFDM signals for the latter half area of each of the three OFDM signals sequentially output from the repetitive output means. A phase difference of about 180 degrees is provided. Therefore, when an OFDM signal output from the OFDM modulation circuit of claim 2 is received, the correlation value between the AGC preamble signal and the synchronization signal becomes small, as in the case of claim 1.

A serial-parallel conversion means for performing a serial-parallel conversion process on input data, a modulation means for performing differential encoding on an output signal of the serial-parallel conversion means based on a start symbol, IDFT means for performing an inverse discrete Fourier transform on the output signal of the modulation means,
A parallel-to-serial conversion unit that performs parallel-to-serial conversion on the output signal of the DFT unit and outputs a time-domain signal, and a guard interval section in which signal repetition occurs in the time-domain signal output by the parallel-to-serial conversion unit is added. Guard interval addition means, preamble signal generation means for generating a preamble signal of a predetermined time waveform,
An output switching means for outputting an output signal of the parallel / serial conversion means so as to follow the preamble signal output by the preamble signal generation means, wherein the preamble signal generation means has a predetermined frequency domain. OFDM signal is generated by inverse discrete Fourier transform based on the fixed pattern of
Repetitive output means for repeatedly outputting the OFDM signal over a period of time twice as long as one cycle of the discrete Fourier transform corresponding to the length of the M signal, and a second output from the repetitive output means Phase calculating means for giving a phase change of about 180 degrees in the latter half of one OFDM signal, and a first series for performing serial-to-parallel conversion only for one OFDM signal including the area which has undergone the phase change by the phase calculating means Parallel conversion means, first discrete Fourier transform means for performing a discrete Fourier transform on the output signal of the first serial / parallel conversion means, and null points for unused subcarrier components of the signal output by the first discrete Fourier transform means. Null point insertion means to be inserted, and a signal output by the null point insertion means, a plurality of regions of the phase space determined according to the modulation means A signal point mapping unit arranged to approximate to one of the points of a plurality of signal points representing Re respectively,
Storage means for storing an output signal of the signal point mapping means as the start symbol; first inverse discrete Fourier transform means for performing an inverse discrete Fourier transform of the output signal of the signal point mapping means; and the first inverse discrete Fourier transform means A first parallel-to-serial conversion means for performing parallel-to-serial conversion on the output signal of
Output signal control means for outputting over a time period twice as long as one cycle of the discrete Fourier transform corresponding to the length of one OFDM signal; and first output to the output of the repetitive output means Following one OFDM signal, a preamble generating circuit for outputting an output signal of the output signal control means as a preamble signal is provided.

In the case of claim 3, the synchronization signal is a start symbol (SS) used in differential encoding. In such a case, a modulated signal is required for each subcarrier included in the OFDM signal. Therefore, the signal whose phase has been changed by the phase calculation means cannot be used as a start symbol as it is. Therefore, the first serial-parallel conversion means of the third aspect performs serial-parallel conversion only for one OFDM signal including a region that has undergone a phase change by the phase calculation means. Further, the first discrete Fourier transform unit performs a discrete Fourier transform on the time domain signal output from the first serial / parallel converter to generate a frequency domain signal.

Further, the null point insertion means inserts a null point for an unnecessary subcarrier component which is not used in the signal output from the first discrete Fourier transform means. The signal point mapping means arranges the signal output by the null point insertion means so as to approximate one of a plurality of signal points respectively representing a plurality of regions of a phase space determined according to the modulation means.

For example, when DQPSK modulation is performed as differential coding, the signal point mapping means uses four reference signal points (representing each of four divided phase planes as shown in FIG. 6). Output signal points) R1, R2, R
3 or R4, one of the points closest to the input signal point
Output the result of approximation and rearrangement of one reference signal point.
The storage means stores the output signal of the signal point mapping means as a start symbol in the frequency domain. The first inverse discrete Fourier transform unit performs an inverse discrete Fourier transform on the frequency domain signal output from the signal point mapping unit to generate a time domain signal.

The first parallel / serial converter converts the output signal of the first inverse discrete Fourier transformer into a parallel / serial converter. The output signal control means outputs the signal output from the first parallel-to-serial conversion means over a time period twice as long as one period of the discrete Fourier transform corresponding to the length of one OFDM signal. I do. The preamble generation circuit outputs the output signal of the output signal control means as a preamble signal following one OFDM signal output first from the output of the repetition output means.

That is, according to the third aspect, the frequency domain start symbol signal is generated from the time domain synchronization signal by the procedure shown in FIG. The conversion of the start symbol signal stored in the storage means into the time domain is based on the IDFT.
This is done by means of the inverse discrete Fourier transform of the means. The time waveform of the time domain start symbol is degraded by operations such as mapping in the generation process. However, the correlation value C between the AGC preamble signal and the start symbol can be suppressed, as in the case of providing a phase difference between the two signals.

A serial / parallel converter for performing serial / parallel conversion processing on input data, a modulator for performing differential encoding on an output signal of the serial / parallel converter based on a start symbol, IDFT means for performing an inverse discrete Fourier transform on the output signal of the modulation means,
A parallel-to-serial conversion unit that performs parallel-to-serial conversion on the output signal of the DFT unit and outputs a time-domain signal, and a guard interval section in which signal repetition occurs in the time-domain signal output by the parallel-to-serial conversion unit is added. Guard interval addition means, preamble signal generation means for generating a preamble signal of a predetermined time waveform,
An output switching means for outputting an output signal of the parallel-to-serial conversion means so as to follow the preamble signal output by the preamble signal generation means, wherein the preamble signal generation means has a predetermined start signal. Waveform storage means for storing one OFDM signal corresponding to the time of one cycle of the discrete Fourier transform obtained by inverse discrete Fourier transform of the symbol, and one cycle length of the discrete Fourier transform corresponding to the start symbol Phase calculation means for giving a phase change of about 180 degrees to one OFDM signal, first serial-parallel conversion means for performing serial-parallel conversion on an output signal of the phase calculation means,
A first discrete Fourier transform transforming means for transforming an output signal of the first serial-parallel transforming means into a discrete Fourier transform;
Null point insertion means for inserting a null point for an unused subcarrier component of the signal output by the discrete Fourier transform conversion means, and a signal output by the null point insertion means, a plurality of phase spaces determined according to the modulation means. Signal point mapping means arranged to approximate to any one of a plurality of signal points representing the respective areas, and first inverse discrete Fourier transform means for performing an inverse discrete Fourier transform on an output signal of the signal point mapping means, First parallel-to-serial conversion means for performing parallel-to-serial conversion on an output signal of the first inverse discrete Fourier transform means;
Output signal control means for repeatedly outputting a signal output from the waveform storage means twice over a period of two cycles of discrete Fourier transform, and output signals of the first parallel / serial conversion means; A preamble generating circuit for outputting an output signal of the signal control means as a preamble signal.

According to a fourth aspect, the waveform storage means stores one OFDM signal corresponding to one cycle time of a discrete Fourier transform obtained by performing an inverse discrete Fourier transform on a predetermined start symbol. The phase calculation means gives a phase change of substantially 180 degrees to one OFDM signal having a length of one cycle of the discrete Fourier transform corresponding to the start symbol.

The first serial / parallel conversion means performs serial / parallel conversion on the output signal of the phase calculation means. The first discrete Fourier transform transform unit performs a discrete Fourier transform on the time domain signal output from the first serial-parallel transform unit to generate a frequency domain signal. The null point insertion means may be a first point.
Null points are inserted for unused subcarrier components of the signal output by the discrete Fourier transform converter. The signal point mapping means arranges the signal output by the null point insertion means so as to approximate one of a plurality of signal points respectively representing a plurality of regions of a phase space determined according to the modulation means.

The first inverse discrete Fourier transform means performs an inverse discrete Fourier transform on the output signal of the signal point mapping means to generate a signal in the time domain. The first parallel-serial conversion means includes:
The output signal of the first inverse discrete Fourier transform means is parallel-to-serial converted.

The output signal control means repeatedly outputs the signal output from the waveform storage means twice over a period of two cycles of the discrete Fourier transform. The preamble generation circuit outputs the output signal of the output signal control means as a preamble signal following the output signal of the first parallel-serial conversion means. In other words, in the fourth aspect, as shown in FIG.
A GC preamble signal is generated.

The waveform storage means can be realized by using a ROM or the like in which a preamble code for the time domain AGC is stored in advance. As described above, claims 1 to 4 are described.
In either case, the correlation value waveform can be sharpened by performing the phase rotation operation of the AGC preamble signal and / or the synchronization signal, so that the BER characteristic is improved and the symbol timing can be detected at high speed. Further, since the correlation value waveform becomes sharp, the complicated algorithm shown in the above-mentioned reference is not required for peak detection, and the symbol timing can be detected only by the threshold value.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 5 shows the configuration of an OFDM modulation circuit embodying the present invention. This embodiment corresponds to claims 1 and 2. In this embodiment, the serial-parallel conversion means, the modulation means, the IDFT
Means, parallel / serial conversion means, guard interval addition means, preamble signal generation means, output switching means, repetition output means, and phase calculation means are respectively an S / P conversion circuit 101, a QPSK modulation circuit 102, and an IDFT circuit 10.
3, a P / S conversion circuit 104, a GI addition circuit 105, a preamble signal generation means 100, a switching circuit 111, a repetition output circuit 108, and a phase calculation circuit 110.

This embodiment shows an example in which the number of subcarriers included in the generated OFDM signal is 48. OFD in FIG.
The serial input signal a101 input to the M modulation circuit is
48 sets of parallel signals a10 which are serial / parallel converted by the S / P conversion circuit 101 and correspond to the number of subcarriers
Output as 2. The 48 sets of parallel signals a102 are QPSK-modulated by the QPSK modulation circuit 102, respectively.
Each of the 48 sets of modulated parallel signals a103 output from the QPSK modulation circuit 102 is a complex signal composed of an in-phase component (Ich) and a quadrature component (Qch), and is input to the IDFT circuit 103, respectively. You.

Signal a1 input to IDFT circuit 103
03 is a signal in the frequency domain for each subcarrier. ID
The FT circuit 103 performs a discrete Fourier transform on the signal a103 to generate a time-domain signal a104. In this example, since the IDFT circuit 103 performs a 64-point discrete Fourier transform, the signal a104 output from the IDFT circuit 103 is 64 sets.

The P / S conversion circuit 104 is an IDFT circuit 1
The parallel / serial conversion is performed on the 64 sets of signals a104 output by the output unit 03, and the signals are arranged in chronological order in a predetermined order. The GI addition circuit 105 controls the P / S conversion circuit 104 to add a guard interval (repeated signal section) to the OFDM signal. Therefore,
The signal a106 output from the P / S conversion circuit 104 includes a predetermined guard interval. The guard interval amount is set by the GI addition circuit 105.

On the other hand, in the preamble signal generating means 100, a fixed pattern signal a
107 is applied to the S / P conversion circuit 106. The fixed pattern signal a107 is a serial signal having a length (48) necessary for generating one OFDM symbol (preamble). The S / P conversion circuit 106 performs serial / parallel conversion on the input fixed pattern signal a107, and outputs as 48 sets of parallel signals a108 corresponding to the number of subcarriers. I
The DFT circuit 107 performs an inverse discrete Fourier transform to convert the 48 sets of parallel signals a108 in the frequency domain input to the signals a109 in the time domain.

In this example, since the number of points of the IDFT circuit 107 is 64, the signal a109 output from it is 64.
A set of parallel signals. The repetitive output circuit 108 performs a parallel / serial conversion to convert the 64 sets of parallel signals output from the IDFT circuit 107 into a serial signal, and repeats the signal for a time three times the OFDM symbol period. Output.

That is, the signal a110 output from the repetitive output circuit 108 corresponds to three OFDM symbols, and specifically, the first AGC preamble signal, the second synchronization signal, This corresponds to the third synchronization signal. The counter circuit 109 counts the clock signal a111 having a constant cycle in order to detect the timing at which the calculation of the above-described equation (2) is performed. When the count value of the counter circuit 109 reaches the set value, the counter circuit 10
9 outputs a signal a112, and the arithmetic processing of the phase operation circuit 110 is started by the signal a112.

The phase operation circuit 110 performs the operation of the equation (2) on the signal a110. That is, based on the AGC preamble signal Sync.A (i), the synchronization signal Sync.B (i)
Is generated, and the latter half of the synchronization signal Sync.B (i) (i = 32 to 6
Regarding 3), a phase difference of 180 degrees is formed with respect to the AGC preamble signal Sync.A (i). Actually, one AGC preamble signal Sync.A (i) and two synchronization signals Sync.B are based on the same fixed pattern signal a107.
Since (i) is generated, the phase calculation circuit 110 performs a phase rotation of 180 degrees only in the latter half area of the second and third symbols of the three symbols that appear continuously. . The result is output as signal a113.

The switching circuit 111 performs signal switching control based on the signal a112 output from the counter circuit 109, and performs a time domain preamble signal (a11
Subsequent to the output of 3), switching is performed so as to output the time domain signal a106 to which the guard interval is added.

However, the signal a in the phase calculation circuit 110
The timing of the control of 112 and the timing of the signal a112 in the switching circuit 111 are different from each other. Switching circuit 1
A signal a114 sequentially output by 11 is an OFDM transmission signal. In this signal, an AGC preamble signal and two synchronization signals as shown in FIG. 1 appear, followed by a modulated data signal.

Note that the preamble waveform is stored in ROM
(A read-only memory), and the data can be read to generate a waveform. Further, one of the two S / P conversion circuits 101 and 106 shown in FIG.
The other circuit can be omitted if it is commonly used for the processing of 07. Similarly, one of the two IDFT circuits 103 and 107 can be commonly used for processing of the input signal a101 and processing of the fixed pattern signal a107, and the other circuit can be omitted.

(Second Embodiment) This embodiment is a modification of the first embodiment, and the modulation circuit for OFDM shown in FIG. 5 except that the operation of the phase calculation circuit 110 is changed as follows. Is the same as That is, in the first embodiment, the rotation of the phase of the signal is performed based on the above equation (2), but in this embodiment, the rotation of the phase of the signal is performed based on the above equation (3). carry out.

In this embodiment, the phase calculation circuit 110 shown in FIG.
Generates the AGC preamble signal Sync.A (i) based on the synchronization signal Sync.B (i), and performs the AGC preamble signal Sync. In the latter half (i = 32 to 63) of .A (i), a phase difference of 180 degrees is formed with respect to the synchronization signal Sync.B (i). Actually, one AGC preamble signal Sync.A (i) and two synchronization signals Sync.B (i) are generated based on the same fixed pattern signal a107. Out of the signal of three symbols appearing consecutively, only in the latter half area of the first symbol,
A phase rotation of 80 degrees is performed. The result is output as signal a113.

(Third Embodiment) OFDM of this embodiment
FIG. 7 shows the configuration of the modulation circuit for use. This embodiment corresponds to claim 3. In this embodiment, the serial / parallel conversion means, the modulation means, the IDFT means, the parallel / serial conversion means, the guard interval addition means, the preamble signal generation means,
Output switching means, repetitive output means, phase calculation means, first
The serial-parallel conversion means, the first discrete Fourier transform means, the null point insertion means, the signal point mapping means, the storage means, the first inverse discrete Fourier transform means, the first parallel-serial conversion means, the output signal control means, and the preamble generation circuit S / P respectively
Conversion circuit 401, DQPSK modulation circuit 402, IDFT
Circuit 403, P / S conversion circuit 404, GI addition circuit 40
5, preamble signal generating means 400, switching circuit 42
2. Repetitive output circuit 409, phase operation circuit 411, S
/ P conversion circuit 412, DFT circuit 413, null signal insertion circuit 414, signal point mapping circuit 415, start symbol storage circuit 417, IDFT circuit 418, P / S conversion circuit 419, output control circuit 420, and preamble generation circuit 421 I do.

In this embodiment, a differential coding modulation system is used for modulation of the subcarrier. The number of subcarriers is 48. The serial input signal a401 input to the OFDM modulation circuit in FIG. 7 is subjected to serial / parallel conversion by the S / P conversion circuit 401, and is output as 48 sets of parallel signals a402 corresponding to the number of subcarriers. Forty-eight sets of parallel signals a402 are provided by the DQPSK modulation circuit 4 respectively.
02 based on the start symbol a 423 stored in the start symbol storage circuit 417
It is SK modulated.

Each of the 48 sets of modulated parallel signals a403 output from the DQPSK modulation circuit 402 is a complex signal composed of an in-phase component (Ich) and a quadrature component (Qch). Is input to The IDFT circuit 403 performs an inverse discrete Fourier transform to convert the input frequency domain signal a403 into a time domain signal a404. Since the number of points of the inverse discrete Fourier transform in the IDFT circuit 403 is 64,
The DFT circuit 403 outputs 64 sets of signals a404 as parallel signals.

The P / S conversion circuit 404 performs a parallel / serial conversion to convert the 64 sets of parallel signals a404 into serial signals a.
406 is generated. The P / S conversion circuit 404 adds a guard interval to the signal a 406 according to the control signal a 405 output from the GI addition circuit 405. on the other hand,
In the preamble signal generating means 400, a fixed pattern signal a407 in a predetermined frequency domain is input to the S / P conversion circuit 407. Fixed pattern signal a407
Is a serial signal having a length corresponding to a signal of 48 subcarriers.

The S / P conversion circuit 407 performs serial / parallel conversion, and performs 48 sets of parallel signals a corresponding to the number of subcarriers.
408 is output. The IDFT circuit 408 performs an inverse discrete Fourier transform to generate a time domain signal a409 from the frequency domain signal a408. The number of points of the inverse discrete Fourier transform of the IDFT circuit 408 is 64,
The signal a409 output from the circuit 408 is 64 sets of parallel signals.

The repetitive output circuit 409 converts the signal a409 input in parallel into a serial signal and outputs the same, and also repeatedly outputs the same signal a410 over two OFDM symbols. The counter circuit 410 uses a clock signal a4 having a constant cycle to determine the control timing.
22 is counted. When the count value of the counter circuit 410 reaches a predetermined value, the signal a411 is applied to the phase calculation circuit 411. Using the signal a411 as a trigger, the phase calculation circuit 4
Numeral 11 starts the operation of the above-mentioned equation (2). The result of the operation is output as signal a412.

The signal a 412 is an AGC signal in the time domain.
Corresponding to the preamble signal and the synchronization signal. First O
The signal a412 output at the timing of the FDM signal is
It is output from the preamble generation circuit 421 as an AGC preamble signal as it is. On the other hand, the signal output from the phase operation circuit 411 at the timing of the second OFDM signal as the signal a 412 includes the S / P conversion circuit 412
Is input to The S / P conversion circuit 412 performs serial / parallel conversion and outputs a parallel signal a413.

The DFT circuit 413 performs a discrete Fourier transform on the parallel signal a 413 in the time domain to obtain a signal a in the frequency domain.
414 is output. In this example, since the number of points in the discrete Fourier transform of the DFT circuit 413 is 64, the signal a413 input thereto and the output signal a414 are 64 sets of parallel signals. The null signal insertion circuit 414 replaces unused subcarrier signals with null point signals. In this example, the DFT circuit 413 has 64 points,
Since the number of subcarriers of the OFDM signal is 48, the null signal insertion circuit 41 is added to the remaining 16 subcarriers that are not used.
At 4, a null signal is input.

That is, the signal value of the unused subcarrier signal component is forcibly changed to null. An actual null is a signal (0, j) in which both the in-phase component and the quadrature component are 0.
0). The signal point mapping circuit 415 maps the value of the input signal a415 to a signal point corresponding to the modulation format of the subcarrier.

For example, when using QPSK modulation, it is necessary to arrange signal points at any one of the four points R1 to R4 in the phase space shown in FIG. Therefore, the signal point mapping circuit 415 replaces the value of the input signal with, for example, the value of the point closest to the point of the input signal among the output signal points R1 to R4 shown in FIG.

The P / S conversion circuit 416 performs parallel / serial conversion on the signal a 416 output from the signal point mapping circuit 415, and applies the converted signal a 424 to the start symbol storage circuit 417. The signal a424 is stored in the start symbol storage circuit 417 as a start symbol signal. The signal a 416 output from the signal point mapping circuit 415 is input to the IDFT circuit 418.
The IDFT circuit 418 performs an inverse discrete Fourier transform to generate a time domain signal a417 from the input frequency domain signal a416. This signal a417 is P /
The parallel / serial conversion is performed by the S conversion circuit 419, and the serial signal a
418 is input to the output control circuit 420.

The output control circuit 420 controls the same signal a418 to be repeatedly output twice over a period of two symbols of the OFDM signal. The preamble generation circuit 421 outputs the first signal a412 output from the phase calculation circuit 411 as the signal a420, and subsequently outputs the signal a419 output from the output control circuit 420 as the signal a420.

The signal a 420 is output as a preamble signal via the switching circuit 422. Switching circuit 422
Outputs the preamble signal (a420) output from the preamble signal generation means 400 first, and then sequentially sends out the signal a406 from the P / S conversion circuit 404. Preamble signal generating means 400 of this form
The signal generation procedure in FIG.
become that way.

The preamble waveform is stored in ROM
(A read-only memory), and the data can be read to generate a waveform. In the OFDM modulation circuit shown in FIG. 7, an S / P conversion circuit 401 for processing an input signal a401 and an IDFT circuit 403
If the circuits such as the S / P conversion circuit 407 and the IDFT circuit 408 of the preamble signal generation means 400 are shared, the circuit configuration can be simplified.

(Fourth Embodiment) OFDM of this embodiment
FIG. 8 shows a configuration of the modulation circuit for use. This embodiment corresponds to claim 4. In this embodiment, the serial / parallel conversion means, the modulation means, the IDFT means, the parallel / serial conversion means, the guard interval addition means, the preamble signal generation means,
Output switching means, waveform storage means, phase calculation means, first serial / parallel conversion means, first discrete Fourier transform conversion means, null point insertion means, signal point mapping means, first inverse discrete Fourier transform means, first parallel / serial conversion Means, an output signal control means, and a preamble generation circuit,
01, DQPSK modulation circuit 502, IDFT circuit 50
3, P / S conversion circuit 504, GI addition circuit 505, preamble signal generation means 500, switching circuit 523, waveform storage circuit 520, phase calculation circuit 511, S / P conversion circuit 5
12, DFT circuit 513, null signal insertion circuit 514, signal point mapping circuit 515, IDFT circuit 518, P /
It corresponds to the S conversion circuit 519, the output control circuit 521, and the preamble generation circuit 522.

In this embodiment, a differential coding modulation system is used for subcarrier modulation. The number of subcarriers is 48. The serial input signal a501 input to the OFDM modulation circuit of FIG. 8 is subjected to serial / parallel conversion by the S / P conversion circuit 501, and is output as 48 sets of parallel signals a502 corresponding to the number of subcarriers. DQP
In the SK modulation circuit 502, the start symbol storage circuit 517 stores the signal a502 output from the S / P conversion circuit.
The DQPSK modulation is performed based on the start symbol a 523 stored in advance.

Each of the 48 sets of modulated parallel signals a503 output from the DQPSK modulation circuit 502 is a complex number signal composed of an in-phase component (Ich) and a quadrature component (Qch). Is input to The IDFT circuit 503 performs an inverse discrete Fourier transform to convert the input frequency domain signal a503 into a time domain signal a504. Since the number of points of the inverse discrete Fourier transform in the IDFT circuit 503 is 64,
The DFT circuit 503 outputs 64 sets of signals a504 as parallel signals.

The P / S conversion circuit 504 performs parallel / serial conversion to convert the 64 sets of parallel signals a 504 into serial signals a.
506 is generated. Also, in accordance with the control signal a505 output from the GI addition circuit 505, the P / S conversion circuit 504 adds a guard interval to the signal a506. on the other hand,
In the preamble signal generation means 500, the start symbol signal a 523 stored in the start symbol storage circuit 517 is input to the S / P conversion circuit 507.
The S / P conversion circuit 507 performs a serial / parallel conversion and outputs a parallel signal a508.

The IDFT circuit 508 performs an inverse discrete Fourier transform on the input signal a 508 in the frequency domain to generate a signal a 509 in the time domain. P / S conversion circuit 509
Performs a parallel / serial conversion to generate a serial signal a510 from the input parallel signal a509. Signal a5
Reference numeral 10 denotes a preamble time waveform. This signal a51
0 is applied to the phase calculation circuit 511 and the waveform storage circuit 520. Signal a519 output from waveform storage circuit 520
Is applied to the preamble generation circuit 522 as a signal a520 through the output control circuit 521. The output control circuit 521 repeatedly outputs the same signal a520 twice over two symbols of the OFDM signal in order to generate two synchronization signals.

The counter circuit 510 counts the clock signal a524 having a constant cycle to determine the control timing. When the count value of the counter circuit 510 reaches a predetermined value, a signal a511 is output. With this signal a511 as a trigger, the phase rotation calculation of the phase calculation circuit 511 is started. The phase calculation circuit 511 receives the signal a510 and performs a process corresponding to the calculation of the above-described equation (3). The result is output as signal a512. Signal a512
Corresponds to the preamble signal for AGC in the time domain shown in FIG.

The S / P conversion circuit 512 performs serial / parallel conversion and generates a parallel signal a513 from the input serial signal a512. The DFT circuit 513 performs a discrete Fourier transform on the parallel signal a513 in the time domain, and outputs a signal a514 in the frequency domain. In this example, since the number of points of the discrete Fourier transform of the DFT circuit 513 is 64,
The signal a513 input thereto and the output signal a514
Are 64 sets of parallel signals.

The null signal insertion circuit 514 replaces unused subcarrier signals with null point signals. In this example, the number of points of the DFT circuit 513 is 64,
Since the number of subcarriers of the DM signal is 48, a null signal is inputted to the remaining 16 subcarriers by the null signal insertion circuit 514. That is, the signal value of the unused subcarrier signal component is forcibly changed to null. The actual null is that both the in-phase and quadrature components are zero.
(0, j0).

The signal point mapping circuit 515 maps the value of the input signal a 515 to a signal point corresponding to the subcarrier modulation format. For example, when using QPSK modulation, it is necessary to arrange signal points at any one of four points R1 to R4 in the phase space shown in FIG.
Accordingly, the signal point mapping circuit 515 replaces the value of the input signal with, for example, the value of the point closest to the point of the input signal among the output signal points R1 to R4 shown in FIG.

The signal a 516 output from the signal point mapping circuit 515 is input to the IDFT circuit 518. ID
The FT circuit 518 performs an inverse discrete Fourier transform to generate a time-domain signal a517 from the input frequency-domain signal a516. This signal a517 is converted in parallel / serial by the P / S conversion circuit 519, and the serial signal a518
Is input to the preamble generation circuit 522.

The preamble generation circuit 522 outputs the signal a520 from the output control circuit 521 as the signal a521, and subsequently outputs the signal a518 from the P / S conversion circuit 519 as the signal a521. Switching circuit 5
23 is a signal a51 output from the counter circuit 510.
1, the preamble generation circuit 5
22 is output as a signal a522.
Subsequently, the signal a506 from the P / S conversion circuit 504 is output as a signal a522.

The preamble signal generating means 50 of this embodiment
The outline of the signal generation procedure at 0 is shown in FIG. In the OFDM modulation circuit shown in FIG. 8, the S / P conversion circuit 501 for processing the input signal a501 and the ID
If the FT circuit 503 and the circuits such as the S / P conversion circuit 507 and the IDFT circuit 508 of the preamble signal generation means 500 are shared, the overall circuit configuration can be simplified.

Computer simulation was performed on the OFDM modulation circuit of the third embodiment. The result is shown in FIG. In this simulation, the modulation scheme of the subcarrier was DQPSK. In this simulation, the carrier frequency error 50
kHz, Eb / N0 (signal energy per bit versus energy density per unit frequency) = 40 dB, 2
A four-wave Rayleigh fading environment (delay spread (rms) 100 ns) was assumed.

Further, it is assumed that the same demodulation circuit as that described in the above document is used as the demodulation circuit. For the detection of symbol timing, the algorithm of the above document was used. In this algorithm, peak detection of a correlation value of a synchronization signal is performed. FIG. 9 shows the relationship between the number of sample points required for peak detection and the bit error rate (BER). Furthermore,
In both the conventional example and the present invention, as the AGC preamble signal, a signal obtained by performing an inverse discrete Fourier transform on a complementary code (code length 48) capable of suppressing the peak amplitude to a low level is used. A signal based on a complementary code (code length 48) different from the AGC preamble signal was used as the synchronization signal in the conventional example.

Referring to FIG. 9, in the configuration of the present invention, the BER is improved by about 35% as compared with the conventional configuration not considering the correlation value. Further, in the present invention, since the peak of the correlation value rises sharply, even if the symbol detection is performed at the time when the threshold value is exceeded (the number of points required for peak detection = 0), the deterioration is less, and the sampling point time is 16 sample points longer than the conventional example. Symbol timing detection can be performed at high speed.

Therefore, according to the present invention, even when the preamble signal for AGC is considered, it is possible to suppress the deterioration of the BER and to realize the symbol timing detection at high speed.

[0086]

As described above, according to the OFDM preamble generation method and OFDM modulation circuit of the present invention,
Even when the AGC preamble signal is considered, the BER does not deteriorate and the symbol timing can be detected at high speed.

[Brief description of the drawings]

FIG. 1 is a time chart showing a correlation value of an OFDM signal generated in a first embodiment.

FIG. 2 is a time chart illustrating a correlation value of an OFDM signal generated in a second embodiment.

FIG. 3 is a flowchart illustrating a signal generation procedure according to a third embodiment.

FIG. 4 is a flowchart illustrating a signal generation procedure according to a fourth embodiment.

FIG. 5 is a block diagram of an OFDM modulation circuit according to the first embodiment.

FIG. 6 is a phase space diagram showing input signal points and output signal points of signal point mapping.

FIG. 7 is a block diagram of an OFDM modulation circuit according to a third embodiment.

FIG. 8 is a block diagram of an OFDM modulation circuit according to a fourth embodiment.

FIG. 9 is a graph showing the results of a simulation.

FIG. 10 is a block diagram illustrating a configuration example of an OFDM demodulation circuit.

FIG. 11 is a block diagram showing a conventional OFDM modulation circuit.

FIG. 12 is a time chart showing a conventional OFDM signal format.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Serial-parallel conversion circuit 2 DQPSK modulation circuit 3 IDFT circuit 4 Parallel-serial conversion circuit 5 Read-order storage circuit 6 D / A conversion circuit 100 Preamble signal generation means 101 S / P conversion circuit 102 QPSK modulation circuit 103 IDFT circuit 104 P / S Conversion circuit 105 GI addition circuit 106 S / P conversion circuit 107 IDFT circuit 108 Repetitive output circuit 109 Counter circuit 110 Phase calculation circuit 111 Switching circuit 301 Tw delay circuit 302 Conjugate complex signal generation circuit 303 Multiplication circuit 304, 307 Moving average filter 305, 306 Square arithmetic circuit 308 Square circuit 309 Peak detection circuit 310 DFT window timing control circuit 311 Arc tangent circuit 312 Divider circuit 313 Conjugate complex signal generation circuit 314 Sample hold circuit 315 Tw Delay circuit 316 Delay circuit 317 Multiplication circuit 318 Serial / parallel conversion circuit 319 DFT circuit 320 Delay detection circuit 321 Parallel / serial conversion circuit 400, 500 Preamble signal generation means 401, 407, 412, 501, 507, 512 S
/ P conversion circuits 402, 502 DQPSK modulation circuits 403, 408, 418, 503, 508, 518 I
DFT circuit 404, 416, 419, 504, 509, 519 P
/ S conversion circuit 405,505 GI addition circuit 409 Repetition output circuit 410,510 Counter circuit 411,511 Phase operation circuit 413,513 DFT circuit 414,514 Null signal insertion circuit 415,515 Signal point mapping circuit 417,517 Start symbol storage Circuit 420, 521 Output control circuit 421, 522 Preamble generation circuit 422, 523 Switching circuit 520 Waveform storage circuit

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] July 12, 1999 (1999.7.1)
2)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 3

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claim 4

[Correction method] Change

[Correction contents]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction contents]

A serial-parallel conversion means for performing a serial-parallel conversion process on input data, a modulation means for performing differential encoding on an output signal of the serial-parallel conversion means based on a start symbol, IDFT means for performing an inverse discrete Fourier transform on the output signal of the modulation means,
A parallel-to-serial conversion unit that performs parallel-to-serial conversion on the output signal of the DFT unit and outputs a time-domain signal, and a guard interval section in which signal repetition occurs in the time-domain signal output by the parallel-to-serial conversion unit is added. Guard interval addition means, preamble signal generation means for generating a preamble signal of a predetermined time waveform,
An output switching means for outputting an output signal of the parallel / serial conversion means so as to follow the preamble signal output by the preamble signal generation means, wherein the preamble signal generation means has a predetermined frequency domain. OFDM signal is generated by inverse discrete Fourier transform based on the fixed pattern of
Repetitive output means for repeatedly outputting the OFDM signal over a period of time twice as long as one cycle of the discrete Fourier transform corresponding to the length of the M signal, and a second output from the repetitive output means Phase calculating means for giving a phase change of about 180 degrees in the latter half of one OFDM signal, and a first series for performing serial-to-parallel conversion only for one OFDM signal including the area which has undergone the phase change by the phase calculating means Parallel converting means, first discrete Fourier transform means for performing a discrete Fourier transform on an output signal of the first serial-parallel converting means, and a signal output from the first discrete Fourier transform means being inputted and a part of the signal is used Sabiki
Null point insertion means for outputting as a carrier component, and a signal output by the null point insertion means, at any one of a plurality of signal points respectively representing a plurality of regions of a phase space determined according to the modulation means. Signal point mapping means arranged in an approximate manner, storage means for storing an output signal of the signal point mapping means as the start symbol, and first inverse discrete Fourier transform for performing an inverse discrete Fourier transform of the output signal of the signal point mapping means Means, first parallel-serial conversion means for parallel-to-serial conversion of the output signal of the first inverse discrete Fourier transform means, and a signal output from the first parallel-serial conversion means corresponding to the length of one OFDM signal. Output signal control means for outputting for a time twice as long as the time of one cycle of the discrete Fourier transform to be performed; Following a single OFDM signal, characterized in that a preamble generation circuit for outputting an output signal of the output signal control unit as a preamble signal.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0033

[Correction method] Change

[Correction contents]

Further, the null point insertion means inputs the signal output from the first discrete Fourier transform means and receives a part of the signal .
The signal is output as a subcarrier component using the signal . The signal point mapping means arranges the signal output by the null point insertion means so as to approximate one of a plurality of signal points respectively representing a plurality of regions of a phase space determined according to the modulation means.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0037

[Correction method] Change

[Correction contents]

A serial / parallel converter for performing serial / parallel conversion processing on input data, a modulator for performing differential encoding on an output signal of the serial / parallel converter based on a start symbol, IDFT means for performing an inverse discrete Fourier transform on the output signal of the modulation means,
A parallel-to-serial conversion unit that performs parallel-to-serial conversion on the output signal of the DFT unit and outputs a time-domain signal, and a guard interval section in which signal repetition occurs in the time-domain signal output by the parallel-to-serial conversion unit is added. Guard interval addition means, preamble signal generation means for generating a preamble signal of a predetermined time waveform,
An output switching means for outputting an output signal of the parallel-to-serial conversion means so as to follow the preamble signal output by the preamble signal generation means, wherein the preamble signal generation means has a predetermined start signal. Waveform storage means for storing one OFDM signal corresponding to the time of one cycle of the discrete Fourier transform obtained by inverse discrete Fourier transform of the symbol, and one cycle length of the discrete Fourier transform corresponding to the start symbol Phase calculation means for giving a phase change of about 180 degrees to one OFDM signal, first serial-parallel conversion means for performing serial-parallel conversion on an output signal of the phase calculation means,
A first discrete Fourier transform transforming means for transforming an output signal of the first serial-parallel transforming means into a discrete Fourier transform;
The signal output by the discrete Fourier transform converter is input and
Output as a subcarrier component using a part of the signal
And a null point insertion means for force, a signal output from the null point insertion unit, approximates any point of the plurality of signal points representing respectively a plurality of regions of the phase space determined according to the modulation means arranged Signal point mapping means, a first inverse discrete Fourier transform means for performing an inverse discrete Fourier transform of an output signal of the signal point mapping means, and a first parallel-serial for parallel-to-serial conversion of an output signal of the first inverse discrete Fourier transform means Conversion means, and a signal output from the waveform storage means,
Output signal control means for repeating and outputting twice over a period of two cycles of the discrete Fourier transform; and an output signal of the output signal control means as a preamble signal following the output signal of the first parallel / serial conversion means. And a preamble generation circuit that performs

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction contents]

The first serial / parallel conversion means performs serial / parallel conversion on the output signal of the phase calculation means. The first discrete Fourier transform transform unit performs a discrete Fourier transform on the time domain signal output from the first serial-parallel transform unit to generate a frequency domain signal. The null point insertion means may be a first point.
The signal output by the discrete Fourier transform converter is input and
Output as a subcarrier component using a part of the signal
Power . The signal point mapping means arranges the signal output by the null point insertion means so as to approximate one of a plurality of signal points respectively representing a plurality of regions of a phase space determined according to the modulation means.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0063

[Correction method] Change

[Correction contents]

The DFT circuit 413 performs a discrete Fourier transform on the parallel signal a 413 in the time domain to obtain a signal a in the frequency domain.
414 is output. In this example, since the number of points in the discrete Fourier transform of the DFT circuit 413 is 64, the signal a413 input thereto and the output signal a414 are 64 sets of parallel signals. The null signal insertion circuit 414 performs the DFT times
Of the signal a414 output from the path 413
Extracts and outputs only the carrier signal. That is,
In the example shown in FIG. 7, as shown in FIG.
64 sets of signals a414 are input and 48 sets of signals a415
Is output.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0064

[Correction method] Change

[Correction contents]

64 input to the null signal insertion circuit 414
The 16 signals among the set of signals a414 are used.
Absent. The signal point mapping circuit 415 maps the value of the input signal a415 to a signal point corresponding to the modulation format of the subcarrier.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0077

[Correction method] Change

[Correction contents]

The null signal insertion circuit 514 includes the DFT circuit 5
13 from the signal a514 output by
Extracts and outputs only the rear signal. That is, this example
Then, as shown in FIG. 8, the null signal insertion circuit 514 has 64
A set of signals a514 are input and 48 sets of signals a515 are output.
Power.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toru Sakata 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation (72) Inventor Hitoshi Takanashi 3- 19-2, Nishi-Shinjuku, Shinjuku-ku, Tokyo No. Nippon Telegraph and Telephone Corporation (72) Inventor Masahiro Morikura 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo F-Term within Nippon Telegraph and Telephone Corporation (reference) 5K004 AA05 FA05 FA09 FB01 FB06 FC02 FF04 5K022 DD13 DD17 DD19 DD22 DD23 5K047 AA02 AA11 BB01 HH43 HH53 JJ02 LL04 LL05 MM03 MM59

Claims (4)

[Claims] 1. OFD used for orthogonal frequency division multiplexing communication
In an OFDM preamble generating method for generating a burst signal including an M signal and a burst signal including at least one preamble signal for automatic gain control and two subsequent synchronizing signals, the method includes the steps of: Generating a preamble signal and the synchronizing signal, and applying a predetermined phase change to each of the latter half regions with respect to one of the preamble signal and the synchronizing signal; Forming an approximately 180-degree phase difference between a phase and a phase of a second half region of each of the plurality of synchronization signals.
A preamble generation method for DM. 2. A serial / parallel conversion means for performing serial / parallel conversion processing on input data, a modulation means for modulating an output signal of the serial / parallel conversion means, and an inverse signal for an output signal of the modulation means. IDFT means for performing a discrete Fourier transform, parallel / serial conversion means for performing a parallel / serial conversion on an output signal of the IDFT means to output a time domain signal, and a signal for a time domain signal output from the parallel / serial conversion means Guard interval adding means for adding a guard interval section in which repetition of the above occurs, a preamble signal generating means for generating a preamble signal having a predetermined time waveform, and the parallel so as to follow a preamble signal output by the preamble signal generating means. An OFDM modulation circuit comprising: an output switching unit that outputs an output signal of the serial conversion unit; Generates the OFDM signal by inverse discrete Fourier transform based on a fixed pattern of order determined frequency domain,
The OFD is performed over a time that is three times as long as one period of the discrete Fourier transform corresponding to the length of one OFDM signal.
A repetitive output means for repeatedly outputting the M signal; and three OFs sequentially output from the repetitive output means.
For the latter half area of each DM signal, the first OF
A phase calculating means for providing a phase difference of about 180 degrees between the DM signal and the second and third OFDM signals in said preamble signal generating means.
Modulation circuit for M. 3. A serial-to-parallel converter for performing serial-to-parallel conversion processing on input data, a modulator for performing differential encoding on an output signal of the serial-to-parallel converter based on a start symbol, and the modulator. IDFT means for performing an inverse discrete Fourier transform on the output signal of the IDFT means, a parallel-serial conversion means for performing a parallel-serial conversion on the output signal of the IDFT means and outputting a time-domain signal, and an output from the parallel-serial conversion means Guard interval adding means for adding a guard interval section in which signal repetition occurs to a time domain signal; preamble signal generating means for generating a preamble signal having a predetermined time waveform; and a preamble output by the preamble signal generating means Output switching means for outputting an output signal of the parallel / serial conversion means so as to follow the signal. In the OFDM modulation circuit, the preamble signal generation means generates an OFDM signal by inverse discrete Fourier transform based on a predetermined fixed pattern in a frequency domain,
The OFD is performed for a time that is twice as long as one period of the discrete Fourier transform corresponding to the length of one OFDM signal.
A repetitive output means for repeatedly outputting an M signal, and one O output secondly output from the repetitive output means
Phase calculation means for giving a phase change of approximately 180 degrees in the latter half of the FDM signal;
Of performing serial-to-parallel conversion only for two OFDM signals
Serial-to-parallel conversion means; first discrete Fourier transform means for performing a discrete Fourier transform on an output signal of the first serial-parallel conversion means; and a null point for an unused subcarrier component of the signal output by the first discrete Fourier transform means. Null point insertion means to insert the, the signal output by the null point insertion means, approximate to any of a plurality of signal points respectively representing a plurality of regions of the phase space determined according to the modulation means Signal point mapping means to be arranged; storage means for storing an output signal of the signal point mapping means as the start symbol; first inverse discrete Fourier transform means for performing an inverse discrete Fourier transform on an output signal of the signal point mapping means; A first parallel-to-serial converter for parallel-to-serial conversion of an output signal of the first inverse discrete Fourier transformer; The signal output from the stage is converted into one of the discrete Fourier transforms corresponding to the length of one OFDM signal.
Output signal control means for outputting over a period of time twice as long as the cycle time; and output of the output signal control means following one OFDM signal output first to the output of the repetitive output means. A modulation circuit for OFDM, comprising: a preamble generation circuit that outputs a signal as a preamble signal. 4. A serial / parallel conversion means for performing serial / parallel conversion processing on input data, a modulation means for performing differential encoding on an output signal of the serial / parallel conversion means based on a start symbol, and the modulation means IDFT means for performing an inverse discrete Fourier transform on the output signal of the IDFT means, a parallel-serial conversion means for performing a parallel-serial conversion on the output signal of the IDFT means and outputting a time-domain signal, and an output from the parallel-serial conversion means Guard interval adding means for adding a guard interval section in which signal repetition occurs to a time domain signal; preamble signal generating means for generating a preamble signal having a predetermined time waveform; and a preamble output by the preamble signal generating means Output switching means for outputting an output signal of the parallel / serial conversion means so as to follow the signal. In the modulation circuit for OFDM, a waveform storage for storing one OFDM signal corresponding to one discrete Fourier transform period obtained by performing inverse discrete Fourier transform on the predetermined start symbol in the preamble signal generation means. Means, one of the discrete Fourier transforms corresponding to the start symbol
Phase calculating means for giving a phase change of substantially 180 degrees to one OFDM signal having a period length; first serial-to-parallel converting means for performing serial-to-parallel conversion on an output signal of the phase calculating means; A first discrete Fourier transform transforming means for transforming an output signal of the serial-parallel transforming means into a discrete Fourier transform, and a null point for inserting a null point for an unused subcarrier component of the signal output by the first discrete Fourier transform transforming means Signal point mapping for arranging a signal output by the insertion means and the signal output by the null point insertion means to be approximate to any one of a plurality of signal points respectively representing a plurality of regions of a phase space determined according to the modulation means. Means, first inverse discrete Fourier transform means for performing an inverse discrete Fourier transform on an output signal of the signal point mapping means, and an output of the first inverse discrete Fourier transform means. First parallel-to-serial conversion means for performing parallel-to-serial conversion of a signal; output signal control means for repeatedly outputting a signal output from the waveform storage means twice over two discrete Fourier transform periods; A modulation circuit for OFDM, comprising: a preamble generation circuit for outputting an output signal of the output signal control means as a preamble signal following an output signal of the one parallel / serial conversion means.