JP2000068386A - Electrostatic protective element circuit, semiconductor device having the same and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the electrostatic protective capability by making the concentration of a well below a channel formation region of an N-type MOS transistor included in an electrostatic protective element circuit lower than that of a well below a channel formation region of an N-type MOS transistor included in other circuit than the electrostatic protective element circuit. SOLUTION: On a P-type semiconductor substrate 1, a P-type well 2 having a concentration of 3×1017 (atoms/cm3) or about is formed. Right under a gate electrode 6, a low concentration P-type impurity region 3 having a concentration of 1×1016 (atoms/cm3) or about which is for improvement of a snapback characteristic and has a lower a concentration than the P-type well 2, and a P-type impurity region 4 for adjusting Vt having the a concentration of 5×1017 (atoms/ cm3) or about which is higher than the concentration of the lower density P-type impurity region 3, are formed. Moreover, a gate oxide film 5, a gate electrode 6, and the source and the drain 7 are formed to build an N-type MOS transistor 20. As a result, the electrostatic protective capability can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including an electrostatic protection element circuit, and more particularly to a MOS device in the electrostatic protection element circuit. It relates to the structure of a well of a transistor.

[0002]

2. Description of the Related Art In this type of electrostatic protection element circuit, in order to protect an internal circuit including an arithmetic element circuit and the like formed in a semiconductor device, the electrostatic protection element circuit is simultaneously formed and arranged in the semiconductor device. The configuration is, for example, N-type M
A circuit in which an OS transistor and a P-type MOS transistor are combined is used.
Characteristics of the MOS transistor, the PN junction characteristics between the source or drain and the substrate, and the P-type MOS transistor.
It is one of the important factors to utilize the PN junction characteristics between the source or drain of the S transistor and the N well.

Normally, as shown in FIG. 6, an N-type MOS transistor having the same structure as the arithmetic circuit element, which is an internal circuit, is employed as an N-type MOS transistor in an electrostatic protection element circuit. That is, the P-type well 2 and the Vt adjusting P-type impurity region 4 exist on the P-type semiconductor substrate 1, and the gate oxide film 5, the gate electrode 6, the source and the drain 7
A type MOS transistor is formed.

Further, as shown in FIG. 7, an N-type well 11 is formed immediately below a source and a drain 7, and a MOS of an internal circuit is formed.
A technique of improving the electrostatic protection ability by making snapback more likely to occur than the transistor is employed. However, as the miniaturization progresses in recent years, the well concentration in the well region of the element has been increasing.

When the concentration of the well region is increased, P
The N-junction easily leaks, and the electrostatic protection ability using the PN junction characteristics is improved. However, in the N-type MOS transistor, when the well concentration increases, the potential change of the well hardly occurs and the snap-back characteristics hardly occur. .
As a result, the electrostatic protection ability utilizing the snapback characteristic is reduced.

On the other hand, in Japanese Patent Application Laid-Open No. 08-306811, in order to reduce the capacity of the input protection transistor,
It discloses that the well concentration of the protection element portion is lower than the well concentration of the internal circuit. In this technology, N-type MOS
Since the well concentration of the transistor is low, for example, ESD
(Electro Static Discharge) When a junction leak current flows due to the application, the potential of the well easily changes, and the electrostatic protection ability using the snapback characteristic increases.
However, since the PN junction breakdown voltage increases, the electrostatic protection ability using the PN junction decreases.

[0007]

In the above-mentioned conventional example, Japanese Patent Application Laid-Open No. 08-306811, the well concentration around the source and the drain of the input protection transistor is reduced in order to reduce the capacitance. Depletion layer easily spreads, and the breakdown voltage of the PN junction increases.

On the other hand, when the PN junction breakdown voltage increases, the ESD
Is applied, junction leakage current becomes difficult to flow,
There is a problem that the electrostatic protection ability using the PN junction is reduced. Further, in recent years, the gate oxide film has become thinner as the miniaturization of elements has progressed. In an N-type MOS transistor, when the well concentration is low, the potential change of the well is likely to occur.

Therefore, if a junction leak current required to cause snapback flows, snapback is likely to occur. However, since the PN junction breakdown voltage is high, there is a problem that a thin gate oxide film is destroyed before snapback occurs. Further, Japanese Patent Application Laid-Open No. 08-306811 has a problem that latch-up is likely to occur due to low well concentration.

Accordingly, an object of the present invention is to improve the above-mentioned drawbacks of the prior art, and to provide an electrostatic protection element circuit having a high electrostatic protection ability even when the concentration of wells increases with miniaturization of elements. An object of the present invention is to provide a semiconductor device using an electrostatic protection element circuit.

[0011]

In order to achieve the above-mentioned object, the present invention employs the following basic technical structure. That is, an N-type MOS transistor and a P-type M
And an N-type MO included in the electrostatic protection element circuit.
The well concentration in the lower part of the channel formation region of the S transistor is the same as that of the N type M
This is an electrostatic protection element circuit configured to be lower than the well concentration below the channel formation region in the OS transistor. Another embodiment is a semiconductor device including such an electrostatic protection element circuit.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The electrostatic protection element circuit according to the present invention and a semiconductor device using the electrostatic protection element circuit,
Since the above-described technical configuration is employed, the well concentration immediately below the channel formation region of the N-type MOS transistor included in the electrostatic protection element circuit is reduced by the N-type MOS transistor included in circuits other than the electrostatic protection element. The P-type MOS transistor that is thinner than the well concentration immediately below the channel formation region and that the well concentration immediately below the channel formation region of the P-type MOS transistor included in the electrostatic protection element circuit is included in circuits other than the electrostatic protection element In this case, the concentration is equal to or higher than the well concentration immediately below the channel formation region.

In the present invention, based on the above configuration, the well concentration immediately below the channel forming region of the N-type MOS transistor included in the electrostatic protection element circuit is reduced, and the wells immediately below the source and drain are formed. By increasing the concentration, an environment in which snapback characteristics are likely to occur is created. Therefore, there is an effect that the electrostatic protection capability of the N-type MOS transistor is improved.

A P-type MOS utilizing a PN junction characteristic
In a transistor, setting the same or higher well concentration as the well concentration of a P-type MOS transistor included in a circuit other than the electrostatic protection element plays an important function in creating an environment for keeping the PN junction breakdown voltage low. Therefore, there is an effect that the capacity of the electrostatic protection element of the P-type MOS transistor can be maintained.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of an electrostatic protection element circuit according to the present invention and a semiconductor device using the electrostatic protection element circuit. That is, FIGS. 1 and 2 are cross-sectional views showing the configuration of a specific example of the electrostatic protection element circuit according to the present invention, in which the N-type MOS transistor shown in FIG. 1 and the N-type MOS transistor shown in FIG. A well region 3 below a channel forming region of an N-type MOS transistor 20 included in the electrostatic protection device circuit.
The N-type MOS transistor (not shown) included in a circuit other than the electrostatic protection element circuit 20 has a well concentration of
In this case, an electrostatic protection element circuit configured to have a lower concentration than the well concentration below the channel formation region is provided, and is provided below the channel formation region 3 in the N-type MOS transistor 20. It is desirable that the corresponding well be formed of a P-type low concentration impurity region.

On the other hand, the well concentration of the well region 8 ′ below the channel forming region of the P-type MOS transistor 30 included in the electrostatic protection element circuit is determined by the P concentration in the circuits other than the electrostatic protection element circuit 30. An electrostatic protection element circuit having a well concentration equal to or higher than a well concentration in a well region below a channel forming region in a type MOS transistor (not shown) is shown.

In another embodiment according to the present invention,
As shown in FIG. 3, the P-type well constituting the N-type MOS transistor 20 is provided below the source region and the drain region 7 of the N-type MOS transistor 20 in the electrostatic protection element circuit. An N-type impurity region 11 having a depth is present. As still another specific example of the electrostatic protection element circuit according to the present invention, as shown in FIG.
The low concentration well region 3 below the channel formation region of the N-type MOS transistor 20 included in the electrostatic protection element circuit.
In a lower layer portion, a high concentration well region 12 having a higher concentration than the low concentration well region is formed.

It is desirable that the high-concentration well region 12 be formed of a P-type impurity region. As another specific example according to the present invention, as shown in FIG. 5, an N-type MOS transistor 20 included in the electrostatic protection element circuit includes a P-type high-concentration impurity region layer 13 on a P-type semiconductor substrate 1. The P-type high concentration impurity region layer 1 of the formed P-type semiconductor substrate 1
3 is formed.

Hereinafter, more specific examples of the electrostatic protection element circuit according to the present invention and a semiconductor device using the electrostatic protection element circuit will be described with reference to FIGS. FIG. 1 is a longitudinal sectional view of an N-type MOS transistor in an electrostatic protection circuit section according to the present invention. 3 on P-type semiconductor substrate 1
There is a P-type well 2 of about × 10 ¹⁷ (atoms / cm ³ ),
Immediately below the gate electrode 6, a concentration of 1 × 10 ¹⁶ (atoms / atom) lower than that of a P-type well for improving snapback characteristics
cm ³⁾ as low concentration P-type impurity region 3 and the low concentration P-type impurity region 3 than a high concentration ^{5 × 10 17 (atoms / cm} 3) of approximately Vt adjusting P-type impurity region 4 is present.

Further, the gate oxide film 5, the gate electrode 6, the source and the drain 7 are present, and constitute an N-type MOS transistor 20. The MOS transistor 20 has a P-type well 2 having a relatively high impurity concentration and a V
The presence of the t-adjustment P-type impurity region 4 can reduce the junction breakdown voltage.

Therefore, when an ESD is applied, a junction leak current easily flows. In addition, since the low-concentration P-type impurity region 3 exists immediately below the gate electrode 6, when a junction leak current flows, the potential of the low-concentration P-type impurity region 3 easily changes. The N-type MOS transistor of the present invention is easily snapbacked due to the two characteristics that the junction leak current easily flows and the potential change of the low-concentration P-type impurity region 3 easily occurs, and the electrostatic protection ability is improved. This has the effect.

FIG. 2 is a longitudinal sectional view of the P-type MOS transistor 30 in the electrostatic protection circuit section of the present invention. An N well 8, an N-type impurity region 9 for adjusting Vt are present on a P-type semiconductor substrate 1, and a gate oxide film 5, a gate electrode 6, and a source and a drain 10 are present. ing.

The structure of the P-type transistor 30 is the same as the structure of a P-type MOS transistor inside the LSI, for example, except for the electrostatic protection circuit. In the case of the P-type MOS transistor 30, electrostatic protection is performed using the PN junction characteristics. Therefore, the well concentration of the P-type MOS transistor 30 in the static electricity protection circuit section is LS
3 × 10 ¹⁷ same as P-type MOS transistor inside I
By setting the well concentration to about (atoms / cm ³ ), the electrostatic protection ability can be kept high.

Further, the well concentration of the P-type MOS transistor 30 in the electrostatic protection circuit section is determined by using an LSI other than the electrostatic protection circuit.
Even if the concentration is set higher than the concentration of the N-type well inside the P-type MOS transistor, a high electrostatic protection capability can be obtained. Next, a second specific example of the electrostatic protection element circuit according to the present invention will be described. FIG. 3 shows an N-type MO in an electrostatic protection circuit section of a second specific example of the electrostatic protection element circuit according to the present invention.
FIG. 3 is a longitudinal sectional view of an S transistor 20.

That is, in the present embodiment, the P-type well 2 exists on the P-type semiconductor substrate 1, and the P-type well 2 is located immediately below the source and the drain 7 around the gate electrode 6 or in the lower part in the vicinity thereof. N well 1 of about × 10 ¹⁷ (atoms / cm ³ )
There is one. Low-concentration P-type impurity region 3, P for Vt adjustment
The type impurity region 4, gate oxide film 5, gate electrode 6, and source and drain 7 are the same as those in the first embodiment of FIG.

In this example, since the N well 11 exists, when a junction leak current flows due to the application of ESD, the potential change of the P-type semiconductor substrate 1 immediately below the N well is changed to N
Through the well 11, it is possible to transmit to the source and the drain. Therefore, in the second specific example, the N-type MOS transistor is more likely to have a snapback characteristic than in the first specific example, and the electrostatic protection capability is also improved.

Next, a third specific example will be described. FIG. 4 is a cross-sectional view showing the configuration of a third specific example of the electrostatic protection element circuit according to the present invention.
FIG. 3 is a longitudinal sectional view of an S transistor 20. In this specific example, the P-type well 2 exists on the P-type semiconductor substrate 1, and the N-well 11 exists immediately below the source and the drain 7 around the gate electrode 6.

In addition, a P-type high-concentration impurity region 12 of about 3 × 10 ¹⁷ (atoms / cm ³ ) exists immediately below the low-concentration P-type impurity region 3 or in a lower portion in the vicinity thereof. The Vt adjusting P-type impurity region 4, gate oxide film 5, gate electrode 6, and source and drain 7 are the same as those in the first embodiment of FIG. In this specific example, since the P-type high-concentration impurity region 12 further exists below the low-concentration P-type impurity region 3,
There is an effect that the latch-up resistance is enhanced while maintaining the electrostatic protection capability.

A description will be given of a fourth embodiment of the electrostatic protection element circuit according to the present invention. That is, FIG. 5 shows N in the electrostatic protection circuit unit according to the fourth example of the present invention.
FIG. 3 is a longitudinal sectional view of a type MOS transistor. That is, the N-type MOS transistor 30 of the second embodiment described above is formed on an epi-substrate having the P-type high-concentration impurity region 13 on the P-type semiconductor substrate 1.

Due to the presence of the P-type high concentration impurity region 13,
This has the effect of improving the latch-up resistance. Although not specifically illustrated, the semiconductor device according to the present invention is a semiconductor device in which the electrostatic protection element circuit defined in each of the above specific examples is appropriately incorporated. The method for manufacturing the electrostatic protection element circuit according to the present invention includes, for example, an N-type MOS transistor and a P-type M
When manufacturing a semiconductor device including an electrostatic protection element circuit composed of an OS transistor, a well in a well region formed below a channel formation region of an N-type MOS transistor included in the electrostatic protection element circuit The impurity doping amount is adjusted so that the concentration is lower than the well concentration in the well region below the channel forming region in the N-type MOS transistor included in the arithmetic element circuit other than the electrostatic protection element circuit. Another specific example is a method of manufacturing a semiconductor device, the method comprising: forming a well concentration of a well region formed below a channel formation region of a P-type MOS transistor included in the electrostatic protection element circuit; Is the formation of the lower part of the channel formation region in a P-type MOS transistor included in an arithmetic element circuit other than the electrostatic protection element circuit. It is characterized in that for adjusting the doping amount of impurities so as to have a well concentration equal to or more well concentration of the well region.

On the other hand, in the present invention, the P-type MOS transistor is further provided below the source region and the drain region of the N-type MOS transistor in the electrostatic protection element circuit. It is also desirable to form an N-type impurity region having the same depth as the well. In the present invention, the N-type MOS included in the electrostatic protection element circuit is used.
A method of manufacturing a semiconductor device in which a high-concentration well region having a higher concentration than the well concentration of the low-concentration well region below the low-concentration well region below the channel formation region of the transistor may be formed. Forming an N-type MOS transistor included in the electrostatic protection element circuit on the P-type high-concentration impurity region layer of the P-type semiconductor substrate in which the P-type high-concentration impurity region layer is formed on the P-type semiconductor substrate; It may be something like that.

[0032]

As described above, since the electrostatic protection element circuit and the semiconductor device according to the present invention employ the above-described technical configuration, the N-type MOS transistor included in the electrostatic protection element circuit is used. A P-type low-concentration impurity region is formed only immediately below the channel formation region of N, and N is formed immediately below the channel formation region of the P-type MOS transistor included in the electrostatic protection element circuit.
By not forming the low-concentration impurity region, there is an effect that the electrostatic protection ability is improved.

The provision of the P-type high-concentration impurity region immediately below the P-type low-concentration impurity region or the use of the P-type epi-substrate also has the effect of improving the latch-up resistance. It should be noted that the present invention is not limited to the above embodiments, and it is clear that the embodiments can be appropriately modified within the scope of the technical idea of the present invention.

[Brief description of the drawings]

FIG. 1 is a first diagram of an electrostatic protection element circuit according to the present invention.
FIG. 4 is a longitudinal sectional view showing a configuration of an N-type MOS transistor as a specific example of FIG.

FIG. 2 is a diagram showing a P-type M according to a first embodiment of the present invention;
FIG. 3 is a longitudinal sectional view illustrating a configuration of an OS transistor.

FIG. 3 is a second view of the electrostatic protection element circuit according to the present invention.
FIG. 4 is a longitudinal sectional view showing a configuration of an N-type MOS transistor in a specific example of FIG.

FIG. 4 is a third view of the electrostatic protection element circuit according to the present invention.
FIG. 4 is a longitudinal sectional view showing a configuration of an N-type MOS transistor in a specific example of FIG.

FIG. 5 is a fourth embodiment of the electrostatic protection element circuit according to the present invention.
FIG. 4 is a longitudinal sectional view showing a configuration of an N-type MOS transistor in a specific example of FIG.

FIG. 6 is a longitudinal sectional view showing a configuration of an N-type MOS transistor in an example of a conventional electrostatic protection element circuit.

FIG. 7 is a longitudinal sectional view showing a configuration of an N-type MOS transistor in another specific example of the conventional electrostatic protection element circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... P type semiconductor substrate 2 ... P type well 3 ... Low concentration P type impurity region 4 ... Vt adjustment P type impurity region 5 ... Gate oxide film 6 ... Gate electrode 7 ... Source and drain 8 ... N type well 9 ... Vt Adjustment N-type impurity region 10 Source and drain 11 N-type well 12 P-type high-concentration impurity region 13 P-type high-concentration impurity region 20 N-type MOS transistor 30 P-type MOS transistor

Claims (12)

[Claims] 1. An electrostatic protection element circuit comprising an N-type MOS transistor and a P-type MOS transistor, wherein a well below a channel forming region of an N-type MOS transistor included in the electrostatic protection element circuit is provided. An electrostatic protection element circuit characterized in that the concentration is lower than the well concentration below a channel formation region in an N-type MOS transistor included in a circuit other than the electrostatic protection element circuit. 2. The well provided below a channel formation region in the N-type MOS transistor.
2. The electrostatic protection element circuit according to claim 1, wherein the electrostatic protection element circuit comprises a P-type low concentration impurity region. 3. The P included in the electrostatic protection element circuit.
The well concentration in the lower part of the channel formation region of the type MOS transistor is equal to or higher than the well concentration in the lower part of the channel formation region in the P-type MOS transistor included in a circuit other than the electrostatic protection element circuit. The electrostatic protection element circuit according to claim 1, wherein the circuit comprises: 4. The N-type M in the electrostatic protection element circuit.
4. An N-type impurity region having a depth equivalent to that of a P-type well constituting an N-type MOS transistor below a source region and a drain region of an OS transistor. The electrostatic protection element circuit according to any one of the above. 5. An N-type M included in the electrostatic protection element circuit.
5. A high-concentration well region having a higher concentration than the low-concentration well region in a low-layer well region below a channel formation region of the OS transistor. The electrostatic protection element circuit according to any one of the above. 6. An N-type M included in the electrostatic protection element circuit.
6. An OS transistor is formed on the P-type high-concentration impurity region layer of the P-type semiconductor substrate in which the P-type high-concentration impurity region layer is formed on the P-type semiconductor substrate. The electrostatic protection element circuit according to any one of the above. 7. A semiconductor device comprising the electrostatic protection element circuit according to claim 1. 8. When manufacturing a semiconductor device including a plurality of arithmetic circuit elements and including an electrostatic protection element circuit composed of an N-type MOS transistor and a P-type MOS transistor, said electrostatic protection element circuit N-type MO included in
The well concentration in the well region formed below the channel formation region of the S transistor is set to the well region below the channel formation region in the N-type MOS transistor included in the arithmetic element circuit other than the electrostatic protection element circuit. A method of manufacturing a semiconductor device, comprising: adjusting a doping amount of an impurity so as to be lower than a well concentration in a semiconductor device. 9. The P included in the electrostatic protection element circuit.
The well concentration of the well region formed below the channel formation region of the type MOS transistor is formed in the lower portion of the channel formation region of the P-type MOS transistor included in the arithmetic element circuit other than the electrostatic protection element circuit. 9. The method according to claim 8, wherein the doping amount of the impurity is adjusted so as to have a well concentration equal to or higher than the well concentration of the well region. 10. A lower part of a source region and a drain region of the N-type MOS transistor in the electrostatic protection element circuit, further having a depth equivalent to a P-type well constituting the N-type MOS transistor. The method according to claim 8, wherein the N-type impurity region is formed. 11. A low-concentration well region having a high-concentration higher than the low-concentration well region in a lower portion of the low-concentration well region below the channel formation region of the N-type MOS transistor included in the electrostatic protection element circuit. The method according to claim 8, wherein a well region is formed. 12. The P-type high-concentration impurity region layer of the P-type semiconductor substrate in which an N-type MOS transistor included in the electrostatic protection element circuit has a P-type high-concentration impurity region layer formed on a P-type semiconductor substrate. The method for manufacturing a semiconductor device according to claim 8, wherein the semiconductor device is formed thereon.