JP2000068376A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form an embedded wiring having a fine pattern on an interlayer insulation film which is difficult to be made fine patterning on a semiconductor substrate, without causing deterioration of the interlayer insulation film or increase in steps as well as to enhance the adhesion of the interlayer insulation film to a barrier metal film or a metal film for wiring. SOLUTION: A groove 306 for wiring having the bottom of a first insulation film 301 is formed on a third insulation film 304 comprising fluorine-doped polyimide on a first insulation film 301 made of a silicon nitride film on a silicon wafer 300. An embedded wiring 309 is formed on the groove 306 for wiring by filling a barrier metal film 307 comprising titanium nitride and a metal for wiring 308 made of copper. At the same time, a sidewall 302B which is made of a silicon oxide film and which has superior adhesion toward a third insulation film 304 and the barrier metal film 307, which is provided between the side surface of the groove 306 for wiring, and embedded wiring 309 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a buried wiring formed in an interlayer insulating film on a semiconductor substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art A method of forming a buried interconnect according to a first conventional example will be described below with reference to FIGS.
This will be described with reference to the process sectional views of (a) to (c).

First, as shown in FIG. 14A, after a first insulating film 11 made of, for example, a silicon nitride film is deposited on a silicon substrate 10, the first insulating film 11 is formed on the first insulating film 11. A second insulating film 12 made of, for example, a silicon oxide film having an etching selectivity with respect to the first insulating film 11 is deposited.

Next, as shown in FIG. 14B, after forming a resist pattern 13 on the second insulating film 12 by photolithography, the resist pattern 13 is formed as shown in FIG. Second insulating film 12 as a mask
Then, a wiring groove 14 having the first insulating film 11 as a bottom surface is formed in the second insulating film 12, and then the resist pattern 13 is removed.

Next, as shown in FIG. 15A, a barrier metal film 15 made of, for example, titanium nitride or tantalum nitride is deposited on the entire surface of the second insulating film 12 including the wiring groove 14. Thereafter, as shown in FIG. 15B, a wiring metal film 16 made of, for example, copper or aluminum is deposited on the barrier metal film 15 over the entire surface.

Next, as shown in FIG. 15C, portions of the barrier metal film 15 and the wiring metal film 16 exposed on the second insulating film 12 are flattened by, for example, a CMP method to form a wiring. A buried wiring 17 composed of a barrier metal film 15 and a wiring metal film 16 is formed inside the groove 14.

As the second insulating film 12, an insulating film which can be easily processed by etching, for example, a silicon oxide film, BP
A silicon oxide film containing phosphorus or boron, such as an SG film, or a fluorine-added silicon oxide film has been widely used.
The relative dielectric constant of the silicon oxide film and the silicon oxide film containing phosphorus or boron is about 4.3, and the relative dielectric constant of the fluorine-added silicon oxide film is about 3.3 to 3.8.

However, with the recent miniaturization and high-speed operation of semiconductor devices, the operation speed of the semiconductor devices has been improved, so that the capacity of the interlayer insulating film has been required to be reduced. It has become important to reduce the capacity of the formed interlayer insulating film. However, since the above materials have a large relative permittivity, when these materials are used as an interlayer insulating film, the capacitance between wirings cannot be reduced.

Therefore, in order to reduce the capacitance between wirings, an interlayer insulating film having a low dielectric constant such as methylsiloxane polymer, polyallyl ether, fluorinated polyimide, benzocyclobutene or polytetrafluoroethylene is used as an insulating film between wirings. Organic insulating film made of low dielectric constant material, porous insulating film, inorganic fine particle containing insulating film reduced in density by dispersing silicon-containing fine particles, or low dielectric constant fine particles containing low dielectric constant material dispersed therein It has been proposed to use an insulating film or the like.

However, since it is difficult to perform etching for fine processing on these low dielectric constant interlayer insulating films, FIGS. 14A to 14C and FIG.
When the embedded wiring forming method shown in (c) is used, there is a problem that it is difficult to form fine wiring grooves or wiring connection holes in these low dielectric constant interlayer insulating films.

In order to solve such a problem, Japanese Unexamined Patent Application Publication No. Hei 8-236621 discloses an interlayer insulating film having a low dielectric constant without directly performing etching for fine processing. A method for forming an embedded wiring having a fine pattern has been proposed.

Hereinafter, as a second conventional example, Japanese Patent Application Laid-Open No.
FIGS. 16 (a) to 16 (d) and FIG.
This will be described with reference to the process sectional views of (a) to (c).

First, as shown in FIG. 16A, a first insulating film 21 made of, for example, a BPSG film, for example, a barrier metal film 22 made of titanium nitride, is formed on a silicon substrate 20.
After sequentially depositing a second insulating film 23 made of, for example, a BPSG film, a resist pattern 24 is formed on the second insulating film 23 by photolithography.

Next, as shown in FIG. 16B, after the first etching is performed on the second insulating film 23 using the resist pattern 24 as a mask, the first etching is performed on the barrier metal film 22. By performing the second etching, a patterned barrier metal film 22A and a patterned second insulating film 23A are formed on the first insulating film 21. In this case, the barrier metal film 22 serves as an etching stopper for the first etching of the second insulating film 23.

Next, as shown in FIG. 16C, after removing the resist pattern 24, a patterned barrier metal film 22A and a patterned second insulating film 23 are formed.
A third insulating film 2 made of a low dielectric constant material such as a polyimide film over the entire surface of the first insulating film 21 including on
5 and then, as shown in FIG.
The insulating film 25 is flattened by, for example, a CMP method so that the patterned second insulating film 23A is exposed.

Next, as shown in FIG. 17A, by selectively removing the patterned second insulating film 23A by etching, the wiring groove 26 having the barrier metal film 22A as the bottom surface is formed. 3 is formed on the insulating film 25.

Next, as shown in FIG. 17B, a wiring metal film 27 made of, for example, copper is deposited on the entire surface of the third insulating film 25 including the wiring groove 26, and then, as shown in FIG. 17
As shown in (c), the third metal film 27
The portion exposed on the insulating film 25 is flattened by, for example, a CMP method to form a buried wiring 28 composed of the patterned barrier metal film 22A and the wiring metal film 27 inside the wiring groove 26. .

[0018]

However, in the second conventional example, it is necessary to perform two etching steps on the barrier metal film 22 and the second insulating film 23, so that the number of etching steps increases. There is a problem.

In the second conventional example, when the barrier metal film 22 is etched, a reaction product between the etching gas and the barrier metal film 22 adheres to the silicon substrate 20. A washing step using an organic solvent is required to remove the product. As a result, depending on the organic solvent used in the cleaning step,
Since the exposed portion of the insulating film 25 is deteriorated and unnecessary etching is performed on the third insulating film 25,
There is a problem that the third insulating film 25 is deteriorated. Also,
In the second conventional example, since the barrier metal film 22 is not provided between the wall surface of the wiring groove 26 and the wiring metal film 27, the metal atoms forming the wiring metal film 27 are removed from the third insulating film 2.
5, the third insulating film 25 is deteriorated.

Further, in the second conventional example, in addition to the above-mentioned problems of an increase in the number of etching steps and deterioration of the third insulating film 25, the third insulating film 25 and the barrier metal film 22 or the wiring metal There is a problem that the adhesion to the film 27 is reduced. Specifically, when an insulating film made of a fluorine-containing material such as a fluorine-added polyimide film is used as the third insulating film 25, the third insulating film 25 is made of, for example, titanium nitride, titanium, tantalum nitride, or tantalum. Since the adhesion to the barrier metal film 22 or the wiring metal film 27 made of, for example, copper or aluminum decreases, the film may peel off.

In view of the above, the present invention forms an embedded wiring having a fine pattern in an interlayer insulating film on a semiconductor substrate which is difficult to be finely processed, without deteriorating the interlayer insulating film and increasing the number of steps. It is a first object to improve the adhesion between an interlayer insulating film and a barrier metal film or a wiring metal film.

[0022]

In order to achieve the second object, a semiconductor device according to the present invention comprises: an insulating film deposited on a semiconductor substrate; a wiring groove formed in the insulating film;
The semiconductor device includes a buried wiring buried in the wiring groove, and a sidewall provided between the wall surface of the wiring groove and the buried wiring and made of an insulating material having excellent adhesion to the insulating film and the buried wiring.

According to the semiconductor device of the present invention, the insulating material having excellent adhesion to the insulating film and the embedded wiring is provided between the embedded wiring and the wall surface of the wiring groove formed in the insulating film on the semiconductor substrate. Since the side wall is provided, the adhesion between the insulating film and the embedded wiring is improved.

In order to achieve the first object, a method of manufacturing a semiconductor device according to the present invention comprises a first insulating film depositing step of depositing a first insulating film on a semiconductor substrate; A second insulating film depositing step of depositing a second insulating film having etching selectivity with respect to the first insulating film on the film, and patterning the second insulating film by patterning; A patterning step of forming a second insulating film; and a third insulating film depositing step of depositing a third insulating film over the entire surface of the first insulating film including the patterned second insulating film. A step of flattening the third insulating film so that the patterned second insulating film is exposed; and removing the patterned second insulating film to form a third insulating film. A wiring groove forming step of forming a wiring groove having a first insulating film as a bottom surface in the film; And a buried wiring forming step of forming a buried wiring by embedding a metal material.

According to the method of manufacturing a semiconductor device of the present invention,
Since the second insulating film has an etching selectivity with respect to the first insulating film, when the second insulating film is etched, a gap between the first insulating film and the second insulating film is generated. Since there is no need to deposit a barrier metal film as an etching stopper, an etching step for the barrier metal film is not required.

According to the method of manufacturing a semiconductor device of the present invention, after the third insulating film is deposited over the entire surface of the first insulating film including the patterned second insulating film. ,
The third insulating film is planarized so that the patterned second insulating film is exposed, and then the patterned second insulating film is removed, whereby the first insulating film is formed on the third insulating film. Since the wiring groove having the film as the bottom surface is formed, the wiring groove can be formed in the third insulating film without directly performing etching for fine processing on the third insulating film.

In order to achieve the first object, in the method of manufacturing a semiconductor device according to the present invention, the third insulating film is formed of the second insulating film.
It is preferable that the wiring groove forming step includes a step of selectively removing the patterned second insulating film by etching.

In order to achieve the first object, in the method of manufacturing a semiconductor device according to the present invention, the wiring groove forming step is a step of selectively removing the patterned second insulating film by photolithography and etching. It is preferable to include

In order to achieve the second object, in the method of manufacturing a semiconductor device according to the present invention, the patterning step includes a step of patterning the second insulating film into the same sectional shape as the buried wiring and the side walls on both sides thereof. Preferably, the wiring groove forming step includes a step of selectively removing the patterned second insulating film while leaving both side walls.

In the method of manufacturing a semiconductor device according to the present invention,
It is preferable that both side walls have a tapered shape that expands downward.

In the method of manufacturing a semiconductor device according to the present invention, a step of depositing an interlayer insulating film on a third insulating film including a portion above a buried wiring, a wiring connection hole reaching the buried wiring in the interlayer insulating film, Forming an upper layer wiring groove communicating with the wiring connection hole; and embedding a metal material in the wiring connection hole and the upper layer wiring groove to form an upper buried wiring connected to the buried wiring. Is preferred.

In the method for manufacturing a semiconductor device according to the present invention,
The first insulating film is preferably a silicon nitride film or a silicon nitride oxide film.

In the method of manufacturing a semiconductor device according to the present invention,
The second insulating film is preferably a silicon-based oxide film or an organic-inorganic composite insulating film containing both an inorganic component and an organic component.

In the method of manufacturing a semiconductor device according to the present invention,
The third insulating film is preferably an organic insulating film, a porous insulating film, or a fine particle-containing insulating film in which fine particles are dispersed.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention will be described below with reference to FIGS. 1 (a) to 1 (d) and 2 (a) to 2 (a). (C)
The process will be described with reference to the cross-sectional views of FIG.

First, as shown in FIG. 1A, a first insulating film 101 made of, for example, a silicon nitride film is deposited on a silicon substrate 100 by, for example, a plasma CVD method.
A second insulating film 102 made of, for example, a silicon oxide film is deposited on the first insulating film 101 by, for example, a CVD method,
After that, a resist pattern 103 is formed on the second insulating film 102 by photolithography. As the second insulating film 102, an insulating film having etching selectivity with respect to the first insulating film 101 is used.

Next, as shown in FIG. 1B, the second insulating film 102 is etched using the resist pattern 103 as a mask to form a patterned second insulating film 102A. In this case, the patterned second insulating film 102A is used for the embedded wiring 1 to be formed later.
08 (see FIG. 2C).

Next, as shown in FIG. 1 (c), after removing the resist pattern 103, the entire surface is formed on the first insulating film 101 including the patterned second insulating film 102A. Then, for example, an organic material such as a methylsiloxane polymer is spin-coated and then baked, that is, a third insulating film 104 is formed by a spin-on-glass method, and then, as shown in FIG. Insulating film 1
04 is flattened by, for example, an etch-back method using dry etching so that the patterned second insulating film 102A is exposed.

Next, as shown in FIG. 2A, the patterned second insulating film 102A is selectively removed by, for example, etching using hydrofluoric acid to form the first insulating film 102A.
A wiring groove 105 having the bottom surface of the insulating film 101 is formed in the third insulating film 104.

Next, as shown in FIG.
After a barrier metal film 106 made of, for example, titanium nitride and a wiring metal film 107 made of, for example, copper are sequentially deposited over the entire surface of the third insulating film 104 including
As shown in FIG. 2C, portions of the barrier metal film 106 and the wiring metal film 107 that are exposed on the third insulating film 104 are planarized by, for example, a CMP method, so that the inside of the wiring groove 105 is formed. Barrier metal film 106
And embedded wiring 108 made of wiring metal film 107
To form

According to the first embodiment, the second insulating film 1
02 has an etching selectivity with respect to the first insulating film 101, so that when the second insulating film 102 is etched, the first insulating film 101 and the second insulating film 102
It is not necessary to deposit a barrier metal film as an etching stopper between these steps, so that an etching step for the barrier metal film becomes unnecessary. Accordingly, the number of etching steps can be reduced, and a cleaning step for a reaction product between the etching gas and the barrier metal film is not required. Therefore, the quality of the third insulating film 104 is reduced by the organic solvent used in the cleaning step. Deterioration and unnecessary etching of the third insulating film 104 can be prevented.

According to the first embodiment, the wiring groove 1
Since the barrier metal film 106 is formed between the wall surface of the wiring 05 and the wiring metal film 107, the wiring metal film 10
7 can be prevented from diffusing into the third insulating film 104, so that the insulating property of the third insulating film 104 can be prevented from deteriorating.

According to the first embodiment, the wiring groove 105 can be formed in the third insulating film 104 without directly performing etching for fine processing on the third insulating film 104. As the insulating film 104, a low-dielectric-constant interlayer insulating film which is difficult to be finely processed by etching, for example, an organic insulating film made of a methylsiloxane polymer, can be used.
Wiring 1 having a fine pattern in the insulating film 104 of FIG.
08 can be formed.

According to the first embodiment, since the third insulating film 104 made of a methylsiloxane polymer has an etching selectivity with respect to the second insulating film 102 made of a silicon oxide film, it is patterned. Second insulating film 10
Since a photolithography step is not required when 2A is selectively removed, the number of steps can be further reduced.

In the first embodiment, a silicon nitride film is used as the first insulating film 101.
A silicon nitride oxide film may be used.

In the first embodiment, an organic insulating film made of a methylsiloxane polymer is used as the third insulating film 104. However, the present invention is not limited to this. An insulating film having a property can be used as appropriate. Specifically, the second insulating film 10
When a silicon-based oxide film such as a silicon oxide film or an organic-inorganic composite insulating film containing both an inorganic component and an organic component is used as the second insulating film 104, for example, as the third insulating film 104,
Low density was achieved by dispersing an organic insulating film, porous insulating film, and silicon-containing fine particles made of a low dielectric constant material such as methylsiloxane polymer, polyallyl ether, fluorine-added polyimide, benzocyclobutene, or polytetrafluoroethylene. It is preferable to use an insulating film containing inorganic fine particles, an insulating film containing low dielectric constant fine particles in which fine particles of a low dielectric constant material are dispersed, or the like.

In the first embodiment, a titanium nitride film is used as the barrier metal film 106. Instead of the titanium nitride film, a single film such as a titanium film, a tantalum film, a tantalum nitride film, or a titanium film is used. And a stacked film of a titanium film and a titanium film and a tantalum nitride film. Further, although a copper film was used as the wiring metal film 107, aluminum, tungsten, gold,
Alternatively, a film made of a conductive material such as silver may be used.

In the first embodiment, the third insulating film 104 is flattened by an etch-back method using dry etching, but may be flattened by a CMP method instead. The portions of the barrier metal film 106 and the wiring metal film 107 exposed on the third insulating film 104 were flattened by the CMP method, but instead were flattened by an etch-back method using dry etching. It may be.

(Second Embodiment) Hereinafter, a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS. 3 (a) to 3 (d) and 4 (a) to 4 (c). This will be described with reference to the process sectional views.

First, as shown in FIG. 3A, after a first insulating film 201 made of, for example, a silicon nitride film is deposited on a silicon substrate 200, the first insulating film 201 is formed on the first insulating film 201.
A second insulating film 202 made of, for example, a TEOS film is deposited by, for example, a plasma CVD method, and then a resist pattern 203 is formed on the second insulating film 202 by photolithography. As the second insulating film 202,
An insulating film having an etching selectivity with respect to the first insulating film 201 is used.

Next, as shown in FIG. 3B, the second insulating film 202 is etched using the resist pattern 203 as a mask to form a patterned second insulating film 202A. In this case, the patterned second insulating film 202A is used for the embedded wiring 2 to be formed later.
09 (see FIG. 4C).

Next, as shown in FIG. 3 (c), after removing the resist pattern 203, the entire surface is formed on the first insulating film 201 including the patterned second insulating film 202A. Thus, a third insulating film 204 made of, for example, a siloxane polymer is formed.

Next, as shown in FIG. 3D, the third insulating film 204 is planarized by, for example, an etch-back method using dry etching so that the patterned second insulating film 202A is exposed. After that, the resist pattern 20 is formed only on the third insulating film 204 by photolithography.
5 is formed.

Next, as shown in FIG. 4A, the second insulating film 202A patterned by using the resist pattern 205 as a mask is etched to make the first insulating film 201 a bottom surface. After forming the wiring groove 206 to be formed in the third insulating film 204, the resist pattern 20 is formed.
5 is removed.

Next, as shown in FIG.
After a barrier metal film 207 made of, for example, titanium nitride and a wiring metal film 208 made of, for example, copper are sequentially deposited over the entire surface of the third insulating film 204 including
As shown in FIG. 4C, portions of the barrier metal film 207 and the wiring metal film 208 that are exposed on the third insulating film 204 are planarized by, for example, a CMP method, so that the inside of the wiring groove 206 is formed. Barrier metal film 207
Buried wiring 209 made of a metal film 208 for wiring
To form

According to the second embodiment, the second insulating film 2
02 has an etching selectivity with respect to the first insulating film 201, so that when the second insulating film 202 is etched, the first insulating film 201 and the second insulating film 202
It is not necessary to deposit a barrier metal film as an etching stopper between these steps, so that an etching step for the barrier metal film becomes unnecessary. Therefore, the number of etching steps can be reduced, and a cleaning step for a reaction product between the etching gas and the barrier metal film is not required. Therefore, the quality of the third insulating film 204 is reduced by the organic solvent used in the cleaning step. Deterioration and unnecessary etching of the third insulating film 204 can be prevented.

According to the second embodiment, the wiring groove 206 can be formed in the third insulating film 204 without directly performing etching for fine processing on the third insulating film 204. A low dielectric constant interlayer insulating film, for example, an inorganic insulating film made of a siloxane polymer, which is difficult to perform fine processing by etching, can be used as the insulating film 204, so that the capacitance between wirings can be reduced and the third insulating film 204 An embedded wiring 209 having a pattern can be formed.

Further, according to the second embodiment, the patterned second insulating film 202A is etched using the resist pattern 205 formed only on the third insulating film 204 by photolithography as a mask. Is performed, the second insulating film 20 is used as the third insulating film 204.
It is not necessary to use an insulating film having etching selectivity with respect to the second insulating film 202 and the third insulating film 2.
A wide variety of materials can be used for 04.

Although the TEOS film is used as the second insulating film 202 in the second embodiment, an organic-inorganic composite insulating film containing both an inorganic component and an organic component, or a fluorine-added film is used instead. A silicon-based oxide film such as a silicon oxide film may be used.

In the second embodiment, an inorganic insulating film made of a siloxane polymer is used as the third insulating film 204. However, another inorganic insulating film made of silsesquioxane hydride or the like is used instead. Film, an organic-inorganic composite insulating film containing both an inorganic component and an organic component, a porous insulating film made of an inorganic material, an inorganic fine particle-containing insulating film reduced in density by dispersing silicon-containing fine particles, or a low dielectric constant material Low-permittivity fine-particle-containing insulating film or the like in which the fine particles are dispersed.

(Third Embodiment) Hereinafter, a semiconductor device according to a third embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS. 5 (a) to 5 (d) and FIGS. 6 (a) to 6 (c). This will be described with reference to the process sectional views.

First, as shown in FIG. 5A, a first insulating film 301 made of, for example, a silicon nitride film is deposited on a silicon substrate 300, and then, on the first insulating film 301,
For example, a second insulating film 302 made of a silicon oxide film is deposited, and then a resist pattern 303 is formed on the second insulating film 302 by photolithography. Second
As the insulating film 302, an insulating film having etching selectivity with respect to the first insulating film 301 is used.

Next, as shown in FIG. 5B, anisotropic etching is performed on the second insulating film 302 using the resist pattern 303 as a mask to form the patterned second insulating film 302A. Form. In this case, the patterned second insulating film 302A has the same cross-sectional shape as the buried wiring 309 to be formed later and the side walls 302B on both sides thereof (see FIG. 6C).

Next, as shown in FIG. 5C, after removing the resist pattern 303, the entire surface of the first insulating film 301 including the patterned second insulating film 302A is covered. And a third material made of, for example, fluorine-added polyimide.
Of the insulating film 304 is formed.

Next, as shown in FIG. 5D, the third insulating film 304 is planarized by, for example, an etch-back method using dry etching so that the patterned second insulating film 302A is exposed. After that, a resist pattern 305 is formed by photolithography on the third insulating film 304 and on a portion of the patterned second insulating film 302A adjacent to the third insulating film 304.

Next, as shown in FIG. 6A, anisotropic etching is performed on the patterned second insulating film 302A using the resist pattern 305 as a mask, so that the third insulating film 304 is formed. A wiring groove 306 having the first insulating film 301 as a bottom surface,
After forming side walls 302B formed on both sides of the patterned second insulating film 302A on the wall surface 06, the resist pattern 305 is removed.

Next, as shown in FIG.
After a barrier metal film 307 made of, for example, titanium nitride and a wiring metal film 308 made of, for example, copper are sequentially deposited over the entire surface of the third insulating film 304 including
As shown in FIG. 6C, portions of the barrier metal film 307 and the wiring metal film 308 exposed on the third insulating film 304 are flattened by, for example, a CMP method, so that the inside of the wiring groove 306 is formed. Barrier metal film 307
Buried wiring 309 made of metal wiring 308
To form

According to the third embodiment, the second insulating film 3
02 has an etching selectivity with respect to the first insulating film 301, so that when the second insulating film 302 is etched, the first insulating film 301 and the second insulating film 302
It is not necessary to deposit a barrier metal film as an etching stopper between these steps, so that an etching step for the barrier metal film becomes unnecessary. Accordingly, the number of etching steps can be reduced, and a cleaning step for a reaction product between the etching gas and the barrier metal film is not required. Therefore, the quality of the third insulating film 304 is reduced by an organic solvent used in the cleaning step. Deterioration and unnecessary etching of the third insulating film 304 can be prevented.

According to the third embodiment, the wiring groove 306 can be formed in the third insulating film 304 without directly performing etching for fine processing on the third insulating film 304. As the insulating film 304, a low-dielectric-constant interlayer insulating film which is difficult to be finely processed by etching, for example, an organic insulating film made of fluorine-added polyimide can be used, so that the capacity between wirings can be reduced and the third insulating film 304 Embedded wiring 309 having fine pattern
Can be formed.

Further, according to the third embodiment, the third insulating film 3 on the third insulating film 304 and in the patterned second insulating film 302A by photolithography.
Since the patterned second insulating film 302A is etched using the resist pattern 305 formed on the portion adjacent to the portion 04 as a mask, the second insulating film 302 is formed as a third insulating film 304. Since it is not necessary to use an insulating film having etching selectivity, a wide range of materials can be used for the second insulating film 302 and the third insulating film 304.

Further, according to the third embodiment, the third insulating film 304 made of fluorine-doped polyimide and the nitrided film are provided between the wall surface of the wiring groove 306 formed in the third insulating film 304 and the buried wiring 309. Since the side wall 302B made of a silicon oxide film having excellent adhesion to the barrier metal film 307 made of titanium can be formed, the third insulating film 3
04 and the buried wiring 309 are improved.

In the third embodiment, a silicon oxide film is used as the second insulating film 302. However, the second insulating film 302 is not limited to the silicon oxide film, and the second insulating film 302 has a good adhesion to the third insulating film 304 and the barrier metal film 307. Another silicon-based oxide film which is favorable and easy to perform fine processing, or an organic-inorganic composite insulating film containing both an inorganic component and an organic component can be appropriately used. Specifically, in the case where an organic insulating film including a fluorine-containing low dielectric constant material such as fluorine-doped polyimide, fluorinated polyallyl ether, or polytetrafluoroethylene is used as the third insulating film 304, the second insulating film As the insulating film 302, it is preferable to use a silicon oxide film which has good adhesion to the organic insulating film made of a low dielectric constant material containing fluorine and the barrier metal film 307 and is easy to perform fine processing.

(Fourth Embodiment) Hereinafter, a semiconductor device according to a fourth embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 7 (a) to 7 (d) and 8 (a) to 8 (c). This will be described with reference to the process sectional views.

First, as shown in FIG. 7A, a first insulating film 401 made of, for example, a silicon nitride film is deposited on a silicon substrate 400, and then, on the first insulating film 401,
For example, a second insulating film 402 made of a silicon oxide film is deposited, and then a resist pattern 403 is formed on the second insulating film 402 by photolithography. Second
As the insulating film 402, an insulating film having etching selectivity with respect to the first insulating film 401 is used.

Next, as shown in FIG. 7B, the second insulating film 402 is subjected to isotropic etching using the resist pattern 403 as a mask to form a patterned second insulating film 402A. To form in this case,
The patterned second insulating film 402A has the same trapezoidal cross-sectional shape extending downward as the embedded wiring 408 to be formed later and the side walls 402B on both sides thereof (see FIG. 8C).

Next, as shown in FIG. 7 (c), after removing the resist pattern 403, the entire surface is formed on the first insulating film 401 including the patterned second insulating film 402A. And a third material made of, for example, fluorine-added polyimide.
After that, as shown in FIG. 7D, the third insulating film 404 is etched back using, for example, dry etching so that the patterned second insulating film 402A is exposed, as shown in FIG. It is flattened by the method.

Next, as shown in FIG. 8A, the patterned second insulating film 402A is removed in a rectangular shape by, for example, anisotropic dry etching using a fluorine-based gas. First insulating film 40 on the first insulating film 404
1 as a bottom surface, and a second insulating film 402 patterned on the wall surface of the wiring groove 405.
A side wall 402B including both side ends of A is formed. In this case, the side wall 402B has a tapered shape expanding downward.

Next, as shown in FIG.
After a barrier metal film 406 made of, for example, titanium nitride and a wiring metal film 407 made of, for example, copper are sequentially deposited over the entire surface of the third insulating film 404 including
As shown in FIG. 8C, portions of the barrier metal film 406 and the wiring metal film 407 that are exposed on the third insulating film 404 are planarized by, for example, a CMP method, so that the inside of the wiring groove 405 is formed. Barrier metal film 406
Wiring 408 made of a metal film 407 for wiring
To form

According to the fourth embodiment, the second insulating film 4
02 has an etching selectivity with respect to the first insulating film 401, so that when the second insulating film 402 is etched, the first insulating film 401 and the second insulating film 402
It is not necessary to deposit a barrier metal film as an etching stopper between these steps, so that an etching step for the barrier metal film becomes unnecessary. Accordingly, the number of etching steps can be reduced, and a cleaning step for a reaction product between the etching gas and the barrier metal film is not required. Therefore, the film quality of the third insulating film 404 depends on an organic solvent used in the cleaning step. Deterioration and unnecessary etching of the third insulating film 404 can be prevented.

According to the fourth embodiment, the wiring groove 405 can be formed in the third insulating film 404 without directly performing etching for fine processing on the third insulating film 404. As the insulating film 404, a low-dielectric-constant interlayer insulating film which is difficult to be finely processed by etching, for example, an organic insulating film made of fluorine-doped polyimide can be used. Embedded wiring 408 having fine pattern
Can be formed.

According to the fourth embodiment, since the third insulating film 404 made of fluorine-doped polyimide has an etching selectivity with respect to the second insulating film 402 made of a silicon oxide film, the third insulating film 404 is patterned. Second insulating film 402A
When the is removed in a rectangular shape, a photolithography step is not required, so that the number of steps can be further reduced.

Further, according to the fourth embodiment, the third insulating film 404 made of fluorine-doped polyimide and the nitrided film are formed between the wall surface of the wiring groove 405 formed in the third insulating film 404 and the buried wiring 408. Since the side wall 402B made of a silicon oxide film having excellent adhesion to the barrier metal film 406 made of titanium can be formed, the third insulating film 4
04 and the embedded wiring 408 are improved in adhesion.

In the fourth embodiment, the silicon oxide film is used as the second insulating film 402. However, the present invention is not limited to this, and the adhesion to the third insulating film 404 and the barrier metal film 406 is good. In addition, another silicon-based oxide film or an organic-inorganic composite insulating film containing both an inorganic component and an organic component, which can be easily microfabricated, can be appropriately used.

In the fourth embodiment, the third insulating film 404 is an organic insulating film made of fluorine-doped polyimide. However, the present invention is not limited to this.
2, another organic insulating film having etching selectivity with respect to 2,
A porous insulating film or a fine particle-containing insulating film in which fine particles are dispersed can be used as appropriate.

(Fifth Embodiment) Hereinafter, a semiconductor device and a method of manufacturing the same according to a fifth embodiment of the present invention will be described with reference to FIGS. 9 (a) to 9 (c), 10 (a) to 10 (c), and FIGS. FIG.
1 (a) to (c), FIGS. 12 (a), (b) and FIG.
This will be described with reference to the process cross-sectional views of (a) and (b).
Note that the semiconductor device according to the present embodiment uses the method for manufacturing a semiconductor device according to the first embodiment of the present invention to form a lower-level buried interconnect on a silicon substrate. An embedded wiring of an upper layer is formed on a silicon substrate by repeatedly using each step of the method for manufacturing a semiconductor device according to the embodiment.

First, as shown in FIG. 9A, using the method for manufacturing a semiconductor device according to the first embodiment of the present invention,
First silicon nitride film on silicon substrate 500
In the third insulating film 502 made of, for example, a methyl siloxane polymer on the insulating film 501, the lower embedded wiring 5 made up of the barrier metal film 503 and the wiring metal film 504 is formed.
After the formation of the second insulating film 505, a fourth insulating film 506 made of, for example, a silicon oxide film is deposited on the entire surface of the third insulating film 502 including the lower embedded wiring 505, and then the fourth insulating film 506 is formed. A resist pattern 507 is formed on the insulating film 506 by photolithography. Note that the second insulating film used in the method for manufacturing the semiconductor device according to the first embodiment of the present invention has been removed by etching before the underlying embedded wiring 505 is formed.
It is not shown in FIG.

Next, as shown in FIG. 9B, the fourth insulating film 506 is etched using the resist pattern 507 as a mask to form a lower embedded wiring 505.
A patterned fourth insulating film 506A is formed thereon. In this case, the patterned fourth insulating film 506A
Has the same cross-sectional shape as a wiring connection 516 to be formed later (see FIG. 13B).

Next, as shown in FIG. 9 (c), after removing the resist pattern 507, the entire surface is formed on the third insulating film 502 including the patterned second insulating film 506A. Then, a fifth insulating film 508 made of the same methyl siloxane polymer as the third insulating film 502 is formed, and then, as shown in FIG.
Is flattened by, for example, an etch-back method using dry etching so that the patterned fourth insulating film 506A is exposed.

Next, as shown in FIG. 10B, the fourth insulating film 506 is formed over the entire surface of the fifth insulating film 508 including the patterned fourth insulating film 506A. And depositing a sixth insulating film 509 made of a silicon oxide film,
Thereafter, as shown in FIG. 10C, the sixth insulating film 50 is formed.
9 on the resist pattern 5 by photolithography
Form 10.

Next, as shown in FIG. 11A, the sixth insulating film 509 is etched using the resist pattern 510 as a mask, thereby forming a pattern on the fourth insulating film 506A. Patterned sixth
Is formed, and then the resist pattern 510 is removed. In this case, the patterned sixth insulating film 509A is used as an upper embedded wiring 5 to be formed later.
17 (see FIG. 13B).

Next, as shown in FIG. 11B, a third insulating film 502 is formed over the entire surface of the fifth insulating film 508 including the patterned sixth insulating film 509A. 7th insulating film 5 made of the same methylsiloxane polymer
11 is formed, and then, as shown in FIG. 11C, the seventh insulating film 511 is patterned into the sixth insulating film 50.
The surface is flattened by, for example, an etch-back method using dry etching so that 9A is exposed.

Next, as shown in FIG. 12A, the patterned fourth insulating film 506A and the patterned sixth insulating film 509A are selectively removed by, for example, dry etching. Lower layer embedded wiring 5
A wiring connection hole 512 reaching 05 is formed in the fifth insulating film 508, and an upper wiring groove 513 communicating with the wiring connection hole 512 is formed in the seventh insulating film 511.

Next, as shown in FIG. 12B, the entire surface is formed on the fifth insulating film 508 including the wiring connection hole 512 and on the seventh insulating film 511 including the upper wiring groove 513. After depositing a barrier metal film 514 made of, for example, titanium nitride, a wiring metal film 515 made of, for example, copper is deposited over the entire surface of the barrier metal film 514 as shown in FIG. I do.

Next, as shown in FIG. 13B, the seventh metal film 514 in the barrier metal film 514 and the wiring metal film 515 is formed.
By flattening a portion exposed on the insulating film 511 by, for example, a CMP method, a wiring connection 516 including a barrier metal film 514 and a wiring metal film 515 is formed inside the wiring connection hole 512, and An upper embedded wiring 517 composed of a barrier metal film 514 and a wiring metal film 515 is formed inside the second wiring groove 513. As a result, an embedded wiring having a dual damascene structure is formed.

According to the fifth embodiment, the fourth insulating film 5
06 and the sixth insulating film 509 have etching selectivity with respect to the third insulating film 502, the fifth insulating film 508, and the seventh insulating film 511, so that the patterned fourth insulating film 506A and Sixth patterned insulating film 509
When A is selectively removed by etching, it is not necessary to deposit an etching stop insulating film having a large relative dielectric constant, so that the number of etching steps can be reduced and the capacitance between wirings and interlayer capacitance can be further reduced. can do.

Hereinafter, as a first comparative example, a method of manufacturing a conventional semiconductor device having a buried interconnect having a dual damascene structure will be described with reference to the process sectional views of FIGS. . In addition, FIG.
In (d), the illustration of the barrier metal film is omitted.

First, as shown in FIG. 18A, a first silicon nitride film 31, a first interlayer insulating film 32, a second silicon nitride film 33, and a second silicon nitride film 31 are formed on a silicon substrate 30. Two interlayer insulating films 34 are sequentially deposited.

Next, as shown in FIG. 18B, a wiring groove 35 is formed by patterning the silicon nitride film 33 of the second layer and the interlayer insulating film 34 of the second layer, respectively. The silicon nitride film 31 and the first interlayer insulating film 32 are patterned to form wiring connection holes 36. In this case, the second-layer silicon nitride film 33 serves as an insulating film for stopping etching in etching the second-layer interlayer insulating film 34, and the first-layer silicon nitride film 31 serves as the first-layer interlayer insulating film. 3
2 plays a role of an insulating film for stopping etching in etching.

Next, as shown in FIG. 18C, the entire surface is formed on the second interlayer insulating film 34 including the wiring groove 35 and the second silicon nitride film 33 including the wiring connection hole 36. After the wiring metal film 37 made of, for example, copper is deposited, the portion of the wiring metal film 37 exposed on the second-layer interlayer insulating film 34 is formed as shown in FIG. For example, by flattening by a CMP method, a buried wiring 38 made of the wiring metal film 37 is formed inside the wiring groove 35 and a wiring connection 39 made of the wiring metal film 37 is formed inside the wiring connection hole 36. I do.

According to the first comparative example, the first silicon nitride film 31 and the second silicon nitride film 33 are deposited as insulating films for stopping etching to form the wiring grooves 35 and the wiring connection holes 36. Therefore, the number of etching steps increases, and the silicon nitride film used as an insulating film for stopping etching has a large relative dielectric constant, so that the capacitance between wirings and the capacitance between layers increase.

In the fifth embodiment, the third insulating film 502, the fifth insulating film 508, and the seventh insulating film 51
Although an organic insulating film made of a methylsiloxane polymer was used as 1, instead of this, an organic insulating film made of another low dielectric constant material, a porous insulating film, and an inorganic material having a low density by dispersing silicon-containing fine particles were used. A fine particle-containing insulating film, a low dielectric constant fine particle-containing insulating film in which fine particles of a low dielectric constant material are dispersed, or the like may be used.

In the fifth embodiment, a buried interconnect having a two-layer structure is formed by using each step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention. By repeatedly using each step of the method of manufacturing the semiconductor device according to the first embodiment, it is possible to form a buried wiring having a multilayer structure of three or more layers, similarly to a buried wiring having a two-layer structure.

[0103]

According to the semiconductor device of the present invention, an insulating material having excellent adhesion to the insulating film and the buried wiring is provided between the buried wiring and the wall surface of the wiring groove formed in the insulating film on the semiconductor substrate. Since the side wall made of is provided, the adhesion between the insulating film and the embedded wiring is improved.

According to the method of manufacturing a semiconductor device of the present invention,
When etching the second insulating film, it is not necessary to deposit a barrier metal film as an etching stopper between the first insulating film and the second insulating film. The process becomes unnecessary. Therefore, the number of etching steps can be reduced, and
Since a cleaning step for a reaction product between the etching gas and the barrier metal film is not required, the quality of the third insulating film is degraded by an organic solvent used in the cleaning step, and the third insulating film is not affected. Necessary etching can be prevented from being performed.

Further, according to the method of manufacturing a semiconductor device of the present invention, the wiring groove can be formed in the third insulating film without directly performing etching for fine processing on the third insulating film. Since an interlayer insulating film having a low dielectric constant, which is difficult to perform fine processing by etching, can be used as the insulating film, the capacitance between wires can be reduced, and a buried wiring having a fine pattern can be formed in the third insulating film.

In the method of manufacturing a semiconductor device according to the present invention,
The third insulating film has an etching selectivity with respect to the second insulating film, and the wiring groove forming step is formed by patterning the second insulating film.
Including the step of selectively removing the insulating film by etching, it is possible to reliably form a wiring groove in the third insulating film without directly performing etching for fine processing on the third insulating film, Since a photolithography step is not required when the patterned second insulating film is selectively removed, the number of steps can be reduced.

In the method of manufacturing a semiconductor device according to the present invention,
When the wiring groove forming step includes a step of selectively removing the patterned second insulating film by photolithography and etching, the third insulating film can be removed without performing etching for fine processing directly. Since the wiring groove can be reliably formed in the third insulating film, and it is not necessary to use an insulating film having an etching selectivity with respect to the second insulating film as the third insulating film, the second insulating film and the third A wide range of insulating film materials can be used as the insulating film.

In the method of manufacturing a semiconductor device according to the present invention,
The patterning step includes a step of patterning the second insulating film into the same sectional shape as the buried wiring and the side walls on both sides thereof, and the wiring groove forming step selectively removes the patterned second insulating film while leaving the side walls on both sides. Including the step of removing
The side wall made of the second insulating film can be reliably formed between the wall surface of the wiring groove and the embedded wiring.

In the method of manufacturing a semiconductor device according to the present invention,
When the side walls on both sides have a tapered shape that expands downward, the side walls can be easily formed between the wall surface of the wiring groove and the embedded wiring.

The method of manufacturing a semiconductor device according to the present invention comprises the steps of: depositing an interlayer insulating film on a third insulating film including a portion above a buried wiring; forming a wiring connection hole reaching the buried wiring in the interlayer insulating film; Forming an upper layer wiring groove communicating with the wiring connection hole; and embedding a metal material in the wiring connection hole and the upper layer wiring groove to form an upper buried wiring connected to the buried wiring. Accordingly, a buried interconnect having a multilayer structure can be formed without performing etching on the barrier metal film and directly performing etching for fine processing on the third insulating film.

In the method of manufacturing a semiconductor device according to the present invention,
When the first insulating film is a silicon nitride film or a silicon nitride oxide film, the second insulating film may be formed using a silicon-based oxide film or an organic-inorganic composite insulating film containing both an inorganic component and an organic component. Since the first insulating film has an etching selectivity with respect to the first insulating film, it serves as an etching stopper between the first insulating film and the second insulating film when etching the second insulating film. There is no need to deposit a barrier metal film.

In the method of manufacturing a semiconductor device according to the present invention,
When the second insulating film is a silicon-based oxide film or an organic-inorganic composite insulating film containing both an inorganic component and an organic component, etching for fine processing can be directly performed on the second insulating film. In addition, when an insulating film containing fluorine, an organic insulating film, a porous insulating film, or an insulating film containing fine particles in which fine particles are dispersed is used as the third insulating film, the wall surface of the wiring groove formed in the third insulating film is used. By forming the side wall made of the second insulating film between the third insulating film and the buried wiring, the adhesion between the third insulating film and the buried wiring can be improved.

In the method of manufacturing a semiconductor device according to the present invention,
When the third insulating film is an organic insulating film, a porous insulating film, or a fine particle-containing insulating film in which fine particles are dispersed, the organic insulating film, the porous insulating film, or the fine particle-containing insulating film in which fine particles are dispersed has a low dielectric constant. When the embedded wiring is formed in the third insulating film, the capacitance between the wirings can be reduced.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a first embodiment.

FIGS. 2A to 2C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to the first embodiment.

FIGS. 3A to 3D are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment.

FIGS. 4A to 4C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a second embodiment.

FIGS. 5A to 5D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a third embodiment.

FIGS. 6A to 6C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a third embodiment.

FIGS. 7A to 7D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fourth embodiment.

FIGS. 8A to 8C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fourth embodiment.

FIGS. 9A to 9C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a fifth embodiment.

FIGS. 10A to 10C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fifth embodiment.

FIGS. 11A to 11C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fifth embodiment.

FIGS. 12A and 12B are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fifth embodiment.

FIGS. 13A and 13B are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fifth embodiment.

FIGS. 14A to 14C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a first conventional example.

FIGS. 15A to 15C are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to a first conventional example.

FIGS. 16A to 16D are cross-sectional views showing steps of a method for manufacturing a semiconductor device according to a second conventional example.

FIGS. 17A to 17C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a second conventional example.

FIGS. 18A to 18D are cross-sectional views showing steps of a method for manufacturing a semiconductor device according to a third conventional example.

[Explanation of symbols]

 Reference Signs List 10 silicon substrate 11 first insulating film 12 second insulating film 13 resist pattern 14 wiring groove 15 barrier metal film 16 wiring metal film 17 buried wiring 20 silicon substrate 21 first insulating film 22 barrier metal film 22A patterned Barrier metal film 23 second insulating film 23A patterned second insulating film 24 resist pattern 25 third insulating film 26 wiring groove 27 wiring metal film 28 buried wiring 30 silicon substrate 31 first layer silicon nitride Film 32 First-layer interlayer insulating film 33 Second-layer silicon nitride film 34 Second-layer interlayer insulating film 35 Wiring groove 36 Wiring connection hole 37 Wiring metal film 38 Embedded wiring 39 Wiring connection 100 Silicon substrate 101 First Insulating film 102 Second insulating film 102A Patterned second insulating film 103 Resist Pattern 104 third insulating film 105 wiring groove 106 barrier metal film 107 wiring metal film 108 buried wiring 200 silicon substrate 201 first insulating film 202 second insulating film 202A patterned second insulating film 203 resist Pattern 204 third insulating film 205 resist pattern 206 wiring groove 207 barrier metal film 208 wiring metal film 209 buried wiring 300 silicon substrate 301 first insulating film 302 second insulating film 302A patterned second insulating film 302B Side wall 303 Resist pattern 304 Third insulating film 305 Resist pattern 306 Wiring groove 307 Barrier metal film 308 Wiring metal film 309 Embedded wiring 400 Silicon substrate 401 First insulating film 402 Second insulating film 402A Second insulating film 402B side wall 403 resist pattern 404 third insulating film 405 wiring groove 406 barrier metal film 407 wiring metal film 408 buried wiring 500 silicon substrate 501 first insulating film 502 third insulating film 503 Barrier metal film 504 Wiring metal film 505 Lower layer embedded wiring 506 Fourth insulating film 506A Patterned fourth insulating film 507 Resist pattern 508 Fifth insulating film 509 Sixth insulating film 509A Patterned fourth 6 insulating film 510 resist pattern 511 seventh insulating film 512 wiring connection hole 513 upper wiring groove 514 barrier metal film 515 wiring metal film 516 wiring connection 517 upper embedded wiring

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Tetsuya Ueda 1-1, Komachi, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. F-term (reference) 5F033 AA09 AA13 AA17 AA23 AA28 AA29 AA52 AA54 AA62 AA64 BA12 BA15 BA16 BA17 BA25 BA37 EA02 EA03 EA06 EA19 EA22 EA25 EA26 EA28 EA29 FA03

Claims (10)

[Claims] An insulating film deposited on a semiconductor substrate; a wiring groove formed in the insulating film; a buried wiring buried in the wiring groove; And a side wall made of an insulating material having excellent adhesion to the insulating film and the buried wiring. 2. A first insulating film depositing step of depositing a first insulating film on a semiconductor substrate, and having an etching selectivity on the first insulating film with respect to the first insulating film. A second insulating film depositing step of depositing a second insulating film; a patterning step of patterning the second insulating film to form a patterned second insulating film; Forming a third insulating film over the entire surface of the first insulating film including the second insulating film;
An insulating film depositing step; a flattening step of flattening the third insulating film so that the patterned second insulating film is exposed; and removing the patterned second insulating film. A wiring groove forming step of forming a wiring groove having the first insulating film as a bottom surface in the third insulating film; and a buried wiring forming step of forming a buried wiring by burying a metal material in the wiring groove. And a method of manufacturing a semiconductor device. 3. The third insulating film has etching selectivity with respect to the second insulating film, and the wiring groove forming step etches the patterned second insulating film. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of selectively removing the semiconductor device. 4. The semiconductor device according to claim 2, wherein the wiring groove forming step includes a step of selectively removing the patterned second insulating film by photolithography and etching. Production method. 5. The patterning step includes a step of patterning the second insulating film into the same sectional shape as the buried wiring and sidewalls on both sides of the buried wiring. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of selectively removing said insulating film while leaving said side walls. 6. The method according to claim 5, wherein the side walls on both sides have a tapered shape expanding downward. 7. A step of depositing an interlayer insulating film on the third insulating film including on the buried wiring, a wiring connecting hole reaching the buried wiring and the wiring connecting hole in the interlayer insulating film. Forming an upper layer wiring groove communicating with the embedded wiring, and embedding a metal material in the wiring connection hole and the upper layer wiring groove to form an upper layer embedded wiring connected to the embedded wiring. The method for manufacturing a semiconductor device according to claim 2, wherein: 8. The method according to claim 2, wherein the first insulating film is a silicon nitride film or a silicon nitride oxide film. 9. The semiconductor device according to claim 2, wherein the second insulating film is a silicon-based oxide film or an organic-inorganic composite insulating film containing both an inorganic component and an organic component. Method. 10. The method according to claim 2, wherein the third insulating film is an organic insulating film, a porous insulating film, or a fine particle-containing insulating film in which fine particles are dispersed.