JP2000059988A - Rush current preventive circuit - Google Patents

Rush current preventive circuit

Info

Publication number
JP2000059988A
JP2000059988A JP10225636A JP22563698A JP2000059988A JP 2000059988 A JP2000059988 A JP 2000059988A JP 10225636 A JP10225636 A JP 10225636A JP 22563698 A JP22563698 A JP 22563698A JP 2000059988 A JP2000059988 A JP 2000059988A
Authority
JP
Japan
Prior art keywords
voltage
circuit
difference
smoothing capacitor
reference voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10225636A
Other languages
Japanese (ja)
Inventor
Seiichi Funakura
清一 舩倉
Seiichirou Satou
清市郎 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP10225636A priority Critical patent/JP2000059988A/en
Publication of JP2000059988A publication Critical patent/JP2000059988A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a rush current preventive circuit which can securely avoid a rush current exceeding the strength of a rectifying device when a power supply is closed and, further, can turn on a switching means in a shortest time. SOLUTION: A rush current preventive circuit has a parallel circuit which is composed of a rush current preventive resistor 9 and a thyristor 10 and connected between rectifying diodes 2-7 and a smoothing capacitor 8. Further, a sampling circuit 21 which detects the voltages of the smoothing capacitor 8 periodically with a certain time interval and outputs the sampling signals of the detected voltages periodically with a certain time interval, a differential voltage calculation circuit 22 which calculates the differential voltages of the sampling signals which are outputted from the sampling circuit 21 successively, a reference power supply 23 which generates a reference voltage VR2 which defines the reference value of the differential voltage and a comparison circuit 24 which compares the voltage of the output signal of the differential voltage calculation circuit 22 with the reference voltage VR2 of the reference power supply 23 and, if the voltage of the output signal of the differential voltage calculation circuit 22 is lower than the reference voltage VR2 of the reference power supply 23, turns on the thyristor 10 which is in an off-state, are provided.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は電源投入時に流れる
突入電流を防止する突入電流防止回路、特に電源投入時
において整流素子の耐量を越える突入電流を確実に防止
できると共に、最短時間でスイッチ手段をオン状態にす
ることが可能な突入電流防止回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inrush current prevention circuit for preventing an inrush current flowing when a power is turned on, and more particularly to an inrush current exceeding a rectifying element withstand capability when the power is turned on. The present invention relates to an inrush current prevention circuit that can be turned on.

【0002】[0002]

【従来の技術】整流素子としての整流ダイオード及び平
滑コンデンサで構成されかつ商用電源等の交流電源又は
通信用電源等として使用される双極性の直流電圧を発生
する直流電源に接続される所謂コンデンサ入力型整流回
路では、電源投入時に整流ダイオードの耐量を越える突
入電流が流れ込み、整流ダイオードが破損する場合があ
る。そこで、電源投入時に流れる突入電流を防止する目
的で、整流回路を構成する少なくとも1つの整流ダイオ
ードと平滑コンデンサとの間に接続される突入電流防止
用抵抗と、突入電流防止用抵抗と並列に接続されかつ平
滑コンデンサの電圧が定常状態となるときにオフ状態か
らオン状態となる電磁リレー又はサイリスタ等のスイッ
チ手段とから成る突入電流防止回路が通常設けられてい
る。図3の破線部Aは、三相交流電源に接続されるコン
デンサ入力型整流回路に組み込まれた一般的な突入電流
防止回路を示し、三相交流電源1の各相に接続された6
個の整流ダイオード2〜7と平滑コンデンサ8との間に
接続される突入電流防止用抵抗9と、突入電流防止用抵
抗9と並列に接続されるスイッチ手段としてのサイリス
タ10と、平滑コンデンサ8の電圧VCが十分高くなり
定常状態となる時点でサイリスタ10にオン信号を出力
する制御回路11とを備えている。制御回路11は、平
滑コンデンサ8の電圧VCの基準値を規定する基準電圧
R1を発生する基準電源12と、平滑コンデンサ8の電
圧VCと基準電源12の基準電圧VR1とを比較して平滑
コンデンサ8の電圧VCが基準電源12の基準電圧VR1
を越えたときにオン信号VONを出力するコンパレータ1
3と、予め設定された時間の経過後にコンパレータ13
からのオン信号VONを出力するタイマ回路14とから構
成される。また、平滑コンデンサ8の両端にはインバー
タ又はDC−DCコンバータ等の負荷15が接続され
る。
2. Description of the Related Art A so-called capacitor input which is composed of a rectifying diode as a rectifying element and a smoothing capacitor and is connected to a DC power supply for generating a bipolar DC voltage used as an AC power supply such as a commercial power supply or a communication power supply. In the type rectifier circuit, when the power is turned on, an inrush current exceeding the rectifier diode's withstand current flows, and the rectifier diode may be damaged. Therefore, in order to prevent an inrush current flowing when the power is turned on, a rush current prevention resistor connected between at least one rectifier diode and a smoothing capacitor constituting a rectifier circuit, and a rush current prevention resistor connected in parallel with the rush current prevention resistor An inrush current prevention circuit is generally provided which includes a switching means such as an electromagnetic relay or a thyristor which is turned on and turned off when the voltage of the smoothing capacitor becomes a steady state. A broken line portion A in FIG. 3 shows a general inrush current prevention circuit incorporated in a capacitor input type rectifier circuit connected to a three-phase AC power supply.
A rush current prevention resistor 9 connected between the rectifier diodes 2 to 7 and the smoothing capacitor 8; a thyristor 10 as a switch connected in parallel with the rush current prevention resistor 9; And a control circuit 11 for outputting an ON signal to the thyristor 10 when the voltage V C becomes sufficiently high to reach a steady state. The control circuit 11 compares the reference power supply 12 which generates a reference voltage V R1 for defining the reference value of the voltage V C of the smoothing capacitor 8, and a reference voltage V R1 of the voltage V C and the reference power source 12 of the smoothing capacitor 8 The voltage V C of the smoothing capacitor 8 is equal to the reference voltage V R1 of the reference power supply 12.
Comparator 1 that outputs ON signal V ON when it exceeds
3 and the comparator 13 after a lapse of a preset time.
And a timer circuit 14 for outputting an ON signal V ON from the CPU. A load 15 such as an inverter or a DC-DC converter is connected to both ends of the smoothing capacitor 8.

【0003】[0003]

【発明が解決しようとする課題】ところで、図3に示す
従来の突入電流防止回路では、三相交流電源1の電圧が
異常に高い場合、電源投入と略同時に平滑コンデンサ8
の電圧VCが基準電源12の基準電圧VR1を越えてサイ
リスタ10がオン状態となり、6個の整流ダイオード2
〜7のうちの何れかにその耐量を越える突入電流が流れ
る可能性がある。また、三相交流電源1の電圧が正常で
あっても平滑コンデンサ8の容量が十分大きい場合は、
電源投入時に突入電流防止用抵抗9及び平滑コンデンサ
8の時定数の増加に伴って各整流ダイオード2〜7の耐
量を越える突入電流が流れる可能性がある。したがっ
て、電源投入時において各整流ダイオード2〜7の耐量
を越える突入電流を確実に防止できない欠点があった。
また、コンパレータ13からオン信号VONが出力されて
からタイマ回路14の設定時間後にサイリスタ10がオ
ン状態となるため、タイマ回路14の設定時間よりも前
に平滑コンデンサ8の電圧VCが十分高くなり定常状態
になってもサイリスタ10をオン状態にすることができ
ず、その結果突入電流防止用抵抗9に出力電流が流れて
電力損失が発生する欠点があった。
By the way, in the conventional inrush current prevention circuit shown in FIG. 3, when the voltage of the three-phase AC power supply 1 is abnormally high, the smoothing capacitor 8 is almost simultaneously supplied with the power supply.
Voltage V C exceeds the reference voltage V R1 of the reference power supply 12, and the thyristor 10 is turned on.
There is a possibility that an inrush current exceeding the withstand current will flow in any of 7 to 77. Also, even if the voltage of the three-phase AC power supply 1 is normal, if the capacity of the smoothing capacitor 8 is sufficiently large,
When the power is turned on, an inrush current exceeding the withstand capability of each of the rectifier diodes 2 to 7 may flow with an increase in the time constant of the inrush current prevention resistor 9 and the smoothing capacitor 8. Therefore, there is a disadvantage that inrush current exceeding the withstand capability of each of the rectifier diodes 2 to 7 cannot be reliably prevented when the power is turned on.
In addition, since the thyristor 10 is turned on after the set time of the timer circuit 14 from the output of the on signal V ON from the comparator 13, the voltage V C of the smoothing capacitor 8 becomes sufficiently high before the set time of the timer circuit 14. In other words, the thyristor 10 cannot be turned on even in the steady state. As a result, there is a drawback that an output current flows through the rush current prevention resistor 9 and power loss occurs.

【0004】そこで、本発明では電源投入時において整
流素子の耐量を越える突入電流を確実に防止できかつ最
短時間でスイッチ手段をオン状態にできる突入電流防止
回路を提供することを目的とする。
Accordingly, an object of the present invention is to provide a rush current prevention circuit which can surely prevent a rush current exceeding the withstand capability of a rectifier element when power is turned on, and can turn on a switch means in a shortest time.

【0005】[0005]

【課題を解決するための手段】本発明による突入電流防
止回路は、整流回路を構成する少なくとも1つの整流素
子と平滑コンデンサとの間に接続される突入電流防止用
抵抗と、該突入電流防止用抵抗と並列に接続されかつ前
記平滑コンデンサの電圧が定常状態となるときにオフ状
態からオン状態となるスイッチ手段とを備えている。こ
の突入電流防止回路では、或る時刻における前記平滑コ
ンデンサの電圧と前記時刻から一定時間経過後の前記平
滑コンデンサの電圧との差電圧を検出する差電圧検出手
段と、前記差電圧の基準値を規定する基準電圧を発生す
る基準電圧発生手段と、該基準電圧発生手段の基準電圧
と前記差電圧検出手段の検出信号の電圧とを比較しかつ
前記差電圧検出手段の検出信号の電圧が前記基準電圧発
生手段の基準電圧以下となるときに前記スイッチ手段を
オフ状態からオン状態にする比較手段とを備えている。
電源投入時においては、差電圧検出手段により検出され
る或る時刻における平滑コンデンサの電圧と或る時刻か
ら一定時間経過後の平滑コンデンサの電圧との差電圧が
基準電圧発生手段の基準電圧よりも大きいため、比較手
段からは何も出力されず、スイッチ手段はオフ状態を保
持する。これにより、電源投入時において発生する突入
電流は全て突入電流防止用抵抗により抑制されるので、
整流素子の耐量を越える突入電流を確実に防止できる。
また、電源投入後は時間の経過と共に差電圧検出手段に
より検出される差電圧が小さくなり、平滑コンデンサの
電圧が定常状態となった時点で前記の差電圧が基準電圧
発生手段の基準電圧以下になると、比較手段の出力信号
によりスイッチ手段がオフ状態からオン状態となる。こ
れにより、平滑コンデンサの電圧が定常状態となると同
時にスイッチ手段がオフ状態からオン状態となるので、
最短時間でスイッチ素子をオン状態にすることが可能と
なる。
According to the present invention, there is provided an inrush current prevention circuit comprising: a rush current prevention resistor connected between at least one rectifier element constituting a rectifier circuit and a smoothing capacitor; A switch connected in parallel with the resistor and turned on from the off state when the voltage of the smoothing capacitor becomes a steady state. In this rush current prevention circuit, a difference voltage detecting means for detecting a difference voltage between a voltage of the smoothing capacitor at a certain time and a voltage of the smoothing capacitor after a lapse of a predetermined time from the time, and a reference value of the difference voltage. A reference voltage generating means for generating a prescribed reference voltage; comparing a reference voltage of the reference voltage generating means with a voltage of a detection signal of the difference voltage detecting means; Comparing means for switching the switch means from the off state to the on state when the voltage becomes equal to or lower than the reference voltage of the voltage generating means.
When the power is turned on, the difference voltage between the voltage of the smoothing capacitor at a certain time detected by the difference voltage detecting means and the voltage of the smoothing capacitor after a certain time has elapsed from the certain time is higher than the reference voltage of the reference voltage generating means. Since it is large, nothing is output from the comparing means, and the switching means keeps the off state. As a result, all the inrush currents that occur when the power is turned on are suppressed by the inrush current prevention resistor.
Inrush current exceeding the withstand capability of the rectifier can be reliably prevented.
Further, after the power is turned on, the difference voltage detected by the difference voltage detecting means decreases with the passage of time, and when the voltage of the smoothing capacitor becomes a steady state, the difference voltage falls below the reference voltage of the reference voltage generating means. Then, the switch means is turned on from the off state by the output signal of the comparison means. Thereby, since the voltage of the smoothing capacitor becomes a steady state and the switch means is turned on from the off state at the same time,
The switching element can be turned on in the shortest time.

【0006】本発明の実施形態における前記差電圧検出
手段は、前記平滑コンデンサの電圧を一定時間毎に検出
しかつ該検出電圧の標本化信号を一定時間毎に出力する
サンプリング手段と、該サンプリング手段から一定時間
毎に出力される標本化信号の差電圧を演算する差電圧演
算手段とから成る。この場合、サンプリング手段により
平滑コンデンサの電圧が一定の時間間隔で標本化(サン
プリング)され、これらの標本化信号の差電圧が差電圧
演算手段により演算されるので、或る時刻における平滑
コンデンサの電圧と或る時刻から一定時間経過後の平滑
コンデンサの電圧との差電圧をより正確に検出すること
ができる利点がある。また、本発明の実施形態における
前記比較手段は、前記基準電圧発生手段の基準電圧と前
記差電圧検出手段の検出信号の電圧との差を演算する減
算回路と、該減算回路の出力信号の正負を判別しかつ前
記出力信号が正値であるときに前記スイッチ手段にオン
信号を出力する正負判定回路とから成る。この場合、減
算回路により基準電圧発生手段の基準電圧と差電圧検出
手段の検出信号の電圧との差を演算し、正負判定回路に
よりその差信号の正負を判別して正値であるときにスイ
ッチ手段にオン信号を出力するので、基準電圧発生手段
の基準電圧と差電圧検出手段の検出信号の電圧との差が
極めて小さい場合においてもスイッチ手段を正確にオフ
状態からオン状態にすることができる利点がある。
In one embodiment of the present invention, the difference voltage detecting means detects a voltage of the smoothing capacitor at regular intervals and outputs a sampling signal of the detected voltage at regular intervals, and the sampling means. And a difference voltage calculating means for calculating a difference voltage of the sampled signal output at regular intervals from the sampling signal. In this case, the voltage of the smoothing capacitor is sampled (sampled) at a fixed time interval by the sampling means, and the difference voltage of these sampled signals is calculated by the difference voltage calculating means. There is an advantage that the difference voltage from the voltage of the smoothing capacitor after a certain time has elapsed from a certain time can be detected more accurately. Further, in the embodiment of the present invention, the comparison means includes a subtraction circuit for calculating a difference between a reference voltage of the reference voltage generation means and a voltage of a detection signal of the difference voltage detection means, and a sign of an output signal of the subtraction circuit. And a positive / negative determination circuit for outputting an ON signal to the switch means when the output signal is a positive value. In this case, the difference between the reference voltage of the reference voltage generation means and the voltage of the detection signal of the difference voltage detection means is calculated by the subtraction circuit, and the sign of the difference signal is discriminated by the sign judgment circuit. Since the on signal is output to the means, even when the difference between the reference voltage of the reference voltage generating means and the voltage of the detection signal of the difference voltage detecting means is extremely small, the switch means can be accurately switched from the off state to the on state. There are advantages.

【0007】[0007]

【発明の実施の形態】以下、本発明による突入電流防止
回路の一実施形態を図1に基づいて説明する。但し、図
1では図3に示す箇所と実質的に同一の部分には同一の
符号を付し、その説明を省略する。本実施形態の突入電
流防止回路は、図1の破線部Aに示すように、図3にお
ける制御回路11を、或る時刻tn(n=1、2、3、
・・・)における平滑コンデンサ8の電圧VCnと或る時
刻tnから一定時間(数百μsec〜数msec)経過後の平
滑コンデンサ8の電圧VCn+1との差電圧VCn+1−VCn
ΔVnを検出する差電圧検出手段としての差電圧検出回
路20と、差電圧ΔV1、ΔV2、ΔV3、・・・の基準
値を規定する基準電圧VR2を発生する基準電圧発生手段
としての基準電源23と、基準電源23の基準電圧VR2
と差電圧検出回路20の差電圧ΔV1、ΔV2、ΔV3
・・・とを比較しかつ差電圧検出回路20の差電圧ΔV
1、ΔV2、ΔV3、・・・が基準電源23の基準電圧V
R2以下となるときにサイリスタ10をオフ状態からオン
状態にする比較手段としての比較回路24とを備えた制
御回路27に変更したものである。本実施例における差
電圧検出回路20は、平滑コンデンサ8の電圧VCを一
定時間(数百μsec〜数msec)毎に検出しかつその検出
電圧VC1、VC2、VC3、VC4、・・・の標本化信号
S1、VS2、VS3、V S4、・・・を一定時間毎に出力す
るサンプリング手段としてのサンプリング回路21と、
サンプリング回路21から一定時間毎に出力される標本
化信号VS1、V S2、VS3、VS4、・・・の差電圧ΔV1
=VS2−VS1、ΔV2=VS3−VS2、ΔV 3=VS4
S3、・・・を演算する差電圧演算手段としての差電圧
演算回路22とから成る。また、比較回路24は基準電
源23の基準電圧VR2と差電圧演算回路22の差電圧Δ
1、ΔV2、ΔV3、・・・との差VR2−ΔV1、VR2
ΔV2、VR2−ΔV3、・・・を演算する減算回路25
と、減算回路25の出力信号VD F1、VDF2、VDF3、・
・・の正負を判別しかつ出力信号VDFn(n=1、2、
3、・・・)が正値であるときにサイリスタ10のゲー
ト端子にオン信号VONを出力する正負判定回路26とか
ら成る。また、基準電源23の基準電圧VR2は、許容電
源電圧範囲、最低電源インピーダンス、整流ダイオード
2〜7の耐量、平滑コンデンサ8の内部抵抗、サンプリ
ング回路21のサンプリング間隔(数百μsec〜数mse
c)から決定される。その他の回路構成は、図3の破線
部Aに示す突入電流防止回路と同一である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Inrush current prevention according to the present invention will now be described.
One embodiment of the circuit will be described with reference to FIG. However,
In FIG. 1, the same parts as those shown in FIG.
The reference numerals are used and the description is omitted. Inrush power of this embodiment
The flow prevention circuit is shown in FIG.
Control circuit 11 at a certain time tn(N = 1, 2, 3,
..))CnAnd one time
Time tnAfter a certain time (several hundred μsec to several msec)
The voltage V of the smoothing capacitor 8Cn + 1And the difference voltage VCn + 1-VCn=
ΔVnVoltage detection circuit as the differential voltage detection means for detecting
Path 20 and differential voltage ΔV1, ΔVTwo, ΔVThree,···Standards of
Reference voltage V that defines the valueR2Reference voltage generating means for generating
Power supply 23 as a reference and reference voltage V of reference power supply 23R2
And the difference voltage ΔV of the difference voltage detection circuit 201, ΔVTwo, ΔVThree,
.. And the difference voltage ΔV of the difference voltage detection circuit 20.
1, ΔVTwo, ΔVThree,... Represent the reference voltage V of the reference power supply 23.
R2Thyristor 10 is turned on from off state when
And a comparison circuit 24 as comparison means for setting a state.
The control circuit 27 has been changed. Difference in this embodiment
The voltage detection circuit 20 detects the voltage V of the smoothing capacitor 8.COne
Detect at regular time intervals (several hundred μsec to several msec) and detect
Voltage VC1, VC2, VC3, VC4, ... sampling signal
VS1, VS2, VS3, V S4, ... are output at regular intervals
A sampling circuit 21 as a sampling means,
Sample output from the sampling circuit 21 at regular intervals
Signal VS1, V S2, VS3, VS4,... Difference voltage ΔV1
= VS2-VS1, ΔVTwo= VS3-VS2, ΔV Three= VS4
VS3,... For calculating the differential voltage
And an arithmetic circuit 22. In addition, the comparison circuit 24
Reference voltage V of source 23R2And the difference voltage Δ of the difference voltage calculation circuit 22
V1, ΔVTwo, ΔVThree, And the difference VR2-ΔV1, VR2
ΔVTwo, VR2-ΔVThree,.
And the output signal V of the subtraction circuit 25D F1, VDF2, VDF3,
.. Judgment of positive / negative and output signal VDFn(N = 1, 2,
3) are positive values, the thyristor 10
ON signal VONPositive / negative judgment circuit 26 that outputs
Consisting of Also, the reference voltage V of the reference power supply 23R2Is the allowable
Source voltage range, minimum source impedance, rectifier diode
2-7, internal resistance of smoothing capacitor 8, sampler
Sampling interval (several hundred μsec to several mse
Determined from c). Other circuit configurations are indicated by broken lines in FIG.
This is the same as the inrush current prevention circuit shown in the section A.

【0008】上記の構成において、平滑コンデンサ8の
電圧VCは差電圧検出回路20内のサンプリング回路2
1により一定の時間間隔(数百μsec〜数msec)で標本
化され、一定の時間間隔で平滑コンデンサ8の電圧VC
の標本化信号VS1、VS2、VS 3、VS4、・・・が逐次出
力される。これらの標本化信号VS1、VS2、VS3
S 4、・・・は差電圧演算回路22に逐次入力され、差
電圧演算回路22により前回取り込まれた標本化信号V
S1、VS2、VS3、・・・と今回取り込まれた標本化信号
S2、VS3、VS4、・・・との差電圧ΔV1=VS2−V
S1、ΔV2=VS3−V S2、ΔV3=VS4−VS3、・・・が
演算される。ここで、三相交流電源1を投入すると、極
めて大きな突入電流が発生し、平滑コンデンサ8の両端
にかかる電圧VCが数十msecのパルス幅で急激に上昇す
るため、差電圧演算回路22から最初に出力される差電
圧ΔV1は基準電源23の基準電圧VR2よりも大きな値
となる。基準電源23の基準電圧VR2及び差電圧演算回
路22から最初に出力される差電圧ΔV1は、比較回路
24内の減算回路25にそれぞれ入力され、減算回路2
5から基準電圧VR2と最初の差電圧ΔV1との差VR2
ΔV1=VDF1が出力される。このとき、VR2<ΔV1
あるから、減算回路25の出力信号VDF1の値は負とな
り、正負判別回路26からは何も出力されない。したが
って、サイリスタ10はオフ状態を保持するので、三相
交流電源1の投入時において発生する突入電流は全て突
入電流防止用抵抗9により抑制され、各整流ダイオード
2〜7には耐量以上の電流が流れない。
In the above configuration, the smoothing capacitor 8
Voltage VCIs the sampling circuit 2 in the difference voltage detection circuit 20.
Samples at fixed time intervals (several hundred μsec to several msec) by 1
And the voltage V of the smoothing capacitor 8 at certain time intervals.C
Sampled signal VS1, VS2, VS Three, VS4, ... appear sequentially
Is forced. These sampled signals VS1, VS2, VS3,
VS Four,... Are sequentially input to the difference voltage calculation circuit 22,
The sampling signal V previously captured by the voltage calculation circuit 22
S1, VS2, VS3, ... and the sampled signal captured this time
VS2, VS3, VS4, And the difference voltage ΔV1= VS2-V
S1, ΔVTwo= VS3-V S2, ΔVThree= VS4-VS3,···But
Is calculated. When the three-phase AC power supply 1 is turned on,
A large inrush current occurs, and both ends of the smoothing capacitor 8
Voltage applied toCRises rapidly with a pulse width of several tens of milliseconds
Therefore, the difference voltage output first from the difference voltage calculation circuit 22
Pressure ΔV1Is the reference voltage V of the reference power supply 23R2Greater than
Becomes Reference voltage V of reference power supply 23R2And differential voltage calculation times
Differential voltage ΔV first output from the path 221Is the comparison circuit
24, each of which is input to a subtraction circuit 25,
5 to reference voltage VR2And the first difference voltage ΔV1Difference VR2
ΔV1= VDF1Is output. At this time, VR2<ΔV1so
Therefore, the output signal V of the subtraction circuit 25DF1Is negative
Nothing is output from the positive / negative discriminating circuit 26. But
Therefore, since the thyristor 10 keeps the off state,
All inrush currents generated when the AC power supply 1 is turned on
Each rectifier diode is suppressed by the input current prevention resistor 9.
No more current than the withstand current flows through 2-7.

【0009】三相交流電源1の投入後、時間の経過と共
に平滑コンデンサ8の充電電圧VCが上昇し、平滑コン
デンサ8に流れ込む電流が徐々に減少して行くと、平滑
コンデンサ8の電圧VCの変化が時間の経過と共に緩や
かになり、ΔV1以降に差電圧演算回路22から出力さ
れる差電圧ΔV2、ΔV3、・・・が時間の経過と共に小
さくなる。そして、平滑コンデンサ8の電圧VCが定常
状態となり、このときに差電圧演算回路22から出力さ
れる差電圧ΔV3が基準電源23の基準電圧VR2以下
(即ち、VR2≧ΔV3)になると、比較回路24内の減
算回路25から出力される基準電圧VR2と差電圧ΔV3
との差信号VR2−ΔV3=VDF3の値が正となる。このと
き、正負判定回路26からサイリスタ10のゲート端子
にオン信号V ONが付与され、サイリスタ10がオフ状態
からオン状態となるので、これ以降は各整流ダイオード
2〜7からサイリスタ10を介して平滑コンデンサ8及
び負荷15に出力電流が流れる。
After the three-phase AC power supply 1 is turned on,
The charging voltage V of the smoothing capacitor 8CRises and smoothes
When the current flowing into the capacitor 8 gradually decreases,
Voltage V of capacitor 8CChanges slowly over time
Cana, ΔV1Thereafter, the output from the difference voltage calculation circuit 22 is output.
Difference voltage ΔVTwo, ΔVThree, ... are small over time
It will be cheap. Then, the voltage V of the smoothing capacitor 8CIs steady
State. At this time, the output
Difference voltage ΔVThreeIs the reference voltage V of the reference power supply 23R2Less than
(Ie, VR2≧ ΔVThree), The reduction in the comparison circuit 24
Reference voltage V output from arithmetic circuit 25R2And the difference voltage ΔVThree
Difference signal VR2-ΔVThree= VDF3Is positive. This and
From the positive / negative determination circuit 26 to the gate terminal of the thyristor 10
ON signal V ONAnd the thyristor 10 is turned off.
The rectifier diode is turned on from
Smoothing capacitors 8 through 2 through 7 through thyristor 10
And an output current flows through the load 15.

【0010】本実施形態の突入電流防止回路では、三相
交流電源1の投入時において平滑コンデンサ8の両端に
かかる電圧VCが急激に上昇するので、差電圧演算回路
22から最初に出力される差電圧ΔV1が基準電源23
の基準電圧VR2よりも大きな値となり、比較回路24内
の減算回路25の出力信号VDF1の値は負となる。この
とき、比較回路24内の正負判別回路26からは何も出
力されず、サイリスタ10はオフ状態を保持する。した
がって、三相交流電源1の投入時において発生する突入
電流は全て突入電流防止用抵抗9により抑制されるの
で、各整流ダイオード2〜7の耐量を越える突入電流を
確実に防止できる。また、三相交流電源1の投入後は時
間の経過と共に平滑コンデンサ8の電圧VCの変化が緩
やかになるので、ΔV1以降に差電圧演算回路22から
逐次出力される差電圧ΔV2、ΔV3、・・・が時間の経
過と共に小さくなる。平滑コンデンサ8の電圧VCが定
常状態となり、差電圧演算回路22から差電圧ΔV3
出力された時点で差電圧ΔV3が基準電源23の基準電
圧VR2以下になると、比較回路24内の減算回路25の
出力信号VDF3の値は正となる。このとき、正負判定回
路26からサイリスタ10のゲート端子にオン信号VON
が付与され、サイリスタ10がオフ状態からオン状態と
なる。したがって、平滑コンデンサ8の電圧VCが定常
状態となると同時にサイリスタ10がオフ状態からオン
状態となるので、最短時間でサイリスタ10をオン状態
にすることが可能となる。特に、本実施形態では、サン
プリング回路21により平滑コンデンサ8の電圧VC
一定の時間間隔(数百μsec〜数msec)で標本化し、こ
れらの標本化信号VS1、VS2、VS3、VS4、・・・の差
電圧ΔV1、ΔV2、ΔV3、・・・を差電圧演算回路2
2により演算するので、或る時刻tn(n=1、2、
3、・・・)における平滑コンデンサ8の電圧VCnと或
る時刻tnから一定時間(数百μsec〜数msec)経過後
の平滑コンデンサ8の電圧VCn+1との差電圧ΔVnを正
確に検出できる利点がある。また、比較回路24内の減
算回路25により基準電源23の基準電圧VR2と差電圧
演算回路22の差電圧ΔV1、ΔV2、ΔV3、・・・と
の差を演算し、正負判定回路26により減算回路25の
出力信号VDFnの正負を判別して正値であるときにサイ
リスタ10にオン信号VONを出力するので、基準電源2
3の基準電圧VR2と差電圧演算回路22の差電圧Δ
1、ΔV2、ΔV3、・・・との差が極めて小さい場合
においてもサイリスタ10を正確にオフ状態からオン状
態にすることができる利点がある。
[0010] In the inrush current preventing circuit of this embodiment, it is output since the three-phase AC voltage V C across the smoothing capacitor 8 during power cycle 1 increases rapidly, from the difference voltage calculation circuit 22 to the first The difference voltage ΔV 1 is equal to the reference power 23
Becomes a value larger than the reference voltage V R2, the value of the output signal V DF1 of the subtraction circuit 25 in the comparison circuit 24 becomes negative. At this time, nothing is output from the positive / negative discriminating circuit 26 in the comparing circuit 24, and the thyristor 10 holds the off state. Therefore, the inrush current generated when the three-phase AC power supply 1 is turned on is all suppressed by the inrush current prevention resistor 9, so that the inrush current exceeding the withstand capability of each of the rectifier diodes 2 to 7 can be surely prevented. Moreover, since the later-on the three-phase AC power supply 1 is the change in voltage V C of the smoothing capacitor 8 over time is moderate, the difference voltage [Delta] V 2 sequentially outputted from the difference voltage calculation circuit 22 to [Delta] V 1 after, [Delta] V 3 becomes smaller over time. When the voltage V C of the smoothing capacitor 8 is in a steady state and the difference voltage ΔV 3 becomes equal to or lower than the reference voltage V R2 of the reference power supply 23 at the time when the difference voltage ΔV 3 is output from the difference voltage calculation circuit 22, The value of the output signal VDF3 of the subtraction circuit 25 is positive. At this time, the ON signal V ON is sent from the positive / negative determination circuit 26 to the gate terminal of the thyristor 10.
, And the thyristor 10 changes from the off state to the on state. Therefore, the thyristor 10 changes from the off state to the on state at the same time that the voltage V C of the smoothing capacitor 8 reaches the steady state, so that the thyristor 10 can be turned on in the shortest time. In particular, in the present embodiment, the sampling circuit 21 samples the voltage V C of the smoothing capacitor 8 at fixed time intervals (several hundred μsec to several msec), and these sampled signals V S1 , V S2 , V S3 , V S The difference voltages ΔV 1 , ΔV 2 , ΔV 3 ,... Of S4 ,.
2 so that a certain time t n (n = 1, 2,
3, the difference voltage [Delta] V n between the voltage V Cn + 1 of the voltage V Cn and certain time t n from a certain time (hundreds μsec~ number msec) after the lapse of the smoothing capacitor 8 of the smoothing capacitor 8 in.) There is an advantage that it can be detected accurately. Further, the subtraction circuit 25 in the comparison circuit 24 calculates the difference between the reference voltage V R2 of the reference power supply 23 and the difference voltages ΔV 1 , ΔV 2 , ΔV 3 ,. 26 determines whether the output signal V DFn of the subtraction circuit 25 is positive or negative and outputs an ON signal V ON to the thyristor 10 when the output signal V DFn has a positive value.
Differential voltage between the third reference voltage V R2 and a differential voltage computation circuit 22 delta
There is an advantage that the thyristor 10 can be accurately turned from the off state to the on state even when the difference between V 1 , ΔV 2 , ΔV 3 ,.

【0011】本発明の実施態様は前記の実施形態に限定
されず、種々の変更が可能である。例えば、上記の実施
形態ではサンプリング回路21により平滑コンデンサ8
の電圧VCを一定の時間間隔(数百μsec〜数msec)で
標本化し、これらの標本化信号VS1、VS2、VS3
S4、・・・の差電圧ΔV1、ΔV2、ΔV3、・・・を
差電圧演算回路22により演算する形態を示したが、或
る時刻tn(n=1、2、3、・・・)における平滑コ
ンデンサ8の電圧VCnと或る時刻tnから一定時間(数
百μsec〜数msec)経過後の平滑コンデンサ8の電圧V
Cn+1との差電圧VCn +1−VCn=ΔVnを直接的に検出し
てもよい。また、上記の実施形態では比較回路24を減
算回路25及び正負判別回路26で構成した形態を示し
たが、図2に示すように、非反転入力(+)端子に入力
される基準電源23の基準電圧VR2と反転入力(−)端
子に入力される差電圧演算回路22の差電圧ΔV1、Δ
2、ΔV3、・・・とを比較しかつ差電圧演算回路22
の差電圧ΔV1、ΔV2、ΔV3、・・・が基準電源23
の基準電圧VR2以下となるときにサイリスタ10のゲー
ト端子に高レベル信号VH(オン信号VON)を出力する
コンパレータ28で比較回路24を構成してもよい。ま
た、上記の各実施形態ではスイッチ手段としてサイリス
タを使用した形態を示したが、電磁リレーや高耐量のパ
ワートランジスタ等を使用することも勿論可能である。
更に、上記の各実施形態では三相交流電源に接続された
コンデンサ入力型整流回路に本発明の突入電流防止回路
を組み込んだ形態を示したが、単相交流電源又は三相以
外の多相交流電源等の他の交流電源、若しくは通信用電
源等として使用される双極性の直流電圧を発生する直流
電源に接続されたコンデンサ入力型整流回路に本発明の
突入電流防止回路を組み込むことも可能であることは云
うまでもない。
The embodiments of the present invention are not limited to the above embodiments, and various modifications are possible. For example, in the above embodiment, the smoothing capacitor 8 is
Of the voltage V C is sampled at regular time intervals (hundreds μsec~ number msec), these sampled signals V S1, V S2, V S3 ,
The difference voltage ΔV 1 , ΔV 2 , ΔV 3 ,... Of V S4 ,... Is calculated by the difference voltage calculation circuit 22, but at a certain time t n (n = 1, 2, 3,. ..) And the voltage V Cn of the smoothing capacitor 8 after a certain time (several hundred μsec to several msec) from a certain time t n.
The difference voltage V Cn +1 −V Cn = ΔV n from Cn + 1 may be directly detected. In the above embodiment, the comparison circuit 24 is constituted by the subtraction circuit 25 and the positive / negative discrimination circuit 26. However, as shown in FIG. 2, the reference power supply 23 inputted to the non-inverting input (+) terminal is used. The reference voltage V R2 and the difference voltages ΔV 1 , ΔV of the difference voltage calculation circuit 22 input to the inverted input (−) terminal
, V 2 , ΔV 3 ,.
, The difference voltages ΔV 1 , ΔV 2 , ΔV 3 ,.
The comparison circuit 24 may be composed of a comparator 28 that outputs a high-level signal V H (ON signal V ON ) to the gate terminal of the thyristor 10 when the reference voltage V R2 becomes equal to or lower than the reference voltage V R2 . Further, in each of the above embodiments, a mode in which a thyristor is used as the switch means has been described. However, an electromagnetic relay, a power transistor having a high withstand voltage, or the like may be used.
Further, in each of the above embodiments, the form in which the inrush current prevention circuit of the present invention is incorporated in the capacitor input type rectifier circuit connected to the three-phase AC power supply is shown. It is also possible to incorporate the inrush current prevention circuit of the present invention into a capacitor input type rectifier circuit connected to a DC power supply that generates a bipolar DC voltage used as another AC power supply such as a power supply or a communication power supply. Needless to say, there is.

【0012】[0012]

【発明の効果】本発明によれば、電源投入時において整
流素子の耐量を越える突入電流を確実に防止できるの
で、電源投入時の突入電流による整流素子の破損事故を
未然に防ぐことが可能となる。また、平滑コンデンサの
電圧が定常状態となると同時にスイッチ手段をオン状態
にできるので、平滑コンデンサの電圧が定常状態のとき
は突入電流防止用抵抗に出力電流が流れず、それによる
電力損失を略0にすることが可能となる。
According to the present invention, it is possible to reliably prevent an inrush current exceeding the withstand capability of the rectifier element when the power is turned on, so that it is possible to prevent damage to the rectifier element due to the inrush current when the power is turned on. Become. Further, since the switching means can be turned on at the same time when the voltage of the smoothing capacitor becomes steady, the output current does not flow through the inrush current prevention resistor when the voltage of the smoothing capacitor is steady, and the power loss caused by the inrush current is substantially zero. It becomes possible to.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明による突入電流防止回路の一実施形態
を示す電気回路図
FIG. 1 is an electric circuit diagram showing one embodiment of an inrush current prevention circuit according to the present invention.

【図2】 図1の変更実施形態を示す電気回路図FIG. 2 is an electric circuit diagram showing a modified embodiment of FIG. 1;

【図3】 従来の突入電流防止回路を示す電気回路図FIG. 3 is an electric circuit diagram showing a conventional inrush current prevention circuit.

【符号の説明】[Explanation of symbols]

1...三相交流電源、2〜7...整流ダイオード
(整流素子)、8...平滑コンデンサ、9...突入
電流防止用抵抗、10...サイリスタ(スイッチ手
段)、11...制御回路、12...基準電源、1
3...コンパレータ、14...タイマ回路、1
5...負荷、20...差電圧検出回路(差電圧検出
手段)、21...サンプリング回路(サンプリング手
段)、22...差電圧演算回路(差電圧演算手段)、
23...基準電源(基準電圧発生手段)、24...
比較回路(比較手段)、25...減算回路、2
6...正負判定回路、27...制御回路、2
8...コンパレータ
1. . . Three-phase AC power supply, 2-7. . . Rectifier diode (rectifier element), 8. . . 8. smoothing capacitor; . . 10. Inrush current prevention resistor; . . 10. thyristor (switch means), . . Control circuit, 12. . . Reference power supply, 1
3. . . Comparator, 14. . . Timer circuit, 1
5. . . Load, 20. . . 21. difference voltage detection circuit (difference voltage detection means); . . 21. sampling circuit (sampling means); . . Difference voltage calculation circuit (difference voltage calculation means),
23. . . 13. reference power supply (reference voltage generating means); . .
25. a comparing circuit (comparing means); . . Subtraction circuit, 2
6. . . Positive / negative determination circuit, 27. . . Control circuit, 2
8. . . comparator

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5G013 AA02 AA16 BA01 CA11 CA18 5G065 BA04 DA06 EA06 HA05 KA02 MA03 NA01 NA02 NA08 5H006 AA05 CA03 CB01 CC08 DA02 DB03 DC05 FA02 GA02 5H410 BB05 CC04 DD02 EA03 EA32 EB01 FF03 FF26 KK02 LL07 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 整流回路を構成する少なくとも1つの整
流素子と平滑コンデンサとの間に接続される突入電流防
止用抵抗と、該突入電流防止用抵抗と並列に接続されか
つ前記平滑コンデンサの電圧が定常状態となるときにオ
フ状態からオン状態となるスイッチ手段とを備えた突入
電流防止回路において、 或る時刻における前記平滑コンデンサの電圧と前記時刻
から一定時間経過後の前記平滑コンデンサの電圧との差
電圧を検出する差電圧検出手段と、前記差電圧の基準値
を規定する基準電圧を発生する基準電圧発生手段と、該
基準電圧発生手段の基準電圧と前記差電圧検出手段の検
出信号の電圧とを比較しかつ前記差電圧検出手段の検出
信号の電圧が前記基準電圧発生手段の基準電圧以下とな
るときに前記スイッチ手段をオフ状態からオン状態にす
る比較手段とを備えたことを特徴とする突入電流防止回
路。
An inrush current preventing resistor connected between at least one rectifying element forming a rectifying circuit and a smoothing capacitor, and a voltage of the smoothing capacitor connected in parallel with the inrush current preventing resistor. A rush current prevention circuit comprising: a switching unit that changes from an off state to an on state when a steady state is reached, wherein a voltage of the smoothing capacitor at a certain time and a voltage of the smoothing capacitor after a lapse of a predetermined time from the time are determined. Difference voltage detecting means for detecting a difference voltage, reference voltage generating means for generating a reference voltage for defining a reference value of the difference voltage, a reference voltage of the reference voltage generating means, and a voltage of a detection signal of the difference voltage detecting means. And when the voltage of the detection signal of the difference voltage detection means is lower than or equal to the reference voltage of the reference voltage generation means, the switch means is turned on from the off state. Rush current prevention circuit comprising the comparing means for the.
【請求項2】 前記差電圧検出手段は、前記平滑コンデ
ンサの電圧を一定時間毎に検出しかつ該検出電圧の標本
化信号を一定時間毎に出力するサンプリング手段と、該
サンプリング手段から一定時間毎に出力される標本化信
号の差電圧を演算する差電圧演算手段とから成る「請求
項1」に記載の突入電流防止回路。
2. The method according to claim 1, wherein the difference voltage detecting means detects a voltage of the smoothing capacitor at regular intervals and outputs a sampling signal of the detected voltage at regular intervals. 2. A rush current prevention circuit according to claim 1, further comprising: a difference voltage calculating means for calculating a difference voltage of the sampled signal output to said sampling signal.
【請求項3】 前記比較手段は、前記基準電圧発生手段
の基準電圧と前記差電圧検出手段の検出信号の電圧との
差を演算する減算回路と、該減算回路の出力信号の正負
を判別しかつ前記出力信号が正値であるときに前記スイ
ッチ手段にオン信号を出力する正負判定回路とから成る
「請求項1」又は「請求項2」に記載の突入電流防止回
路。
3. The subtraction circuit for calculating a difference between a reference voltage of the reference voltage generation means and a voltage of a detection signal of the difference voltage detection means, and determines whether the output signal of the subtraction circuit is positive or negative. 3. The inrush current prevention circuit according to claim 1, further comprising a positive / negative determination circuit that outputs an ON signal to said switch means when said output signal has a positive value.
JP10225636A 1998-08-10 1998-08-10 Rush current preventive circuit Pending JP2000059988A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10225636A JP2000059988A (en) 1998-08-10 1998-08-10 Rush current preventive circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10225636A JP2000059988A (en) 1998-08-10 1998-08-10 Rush current preventive circuit

Publications (1)

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JP2000059988A true JP2000059988A (en) 2000-02-25

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Application Number Title Priority Date Filing Date
JP10225636A Pending JP2000059988A (en) 1998-08-10 1998-08-10 Rush current preventive circuit

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013140874A1 (en) * 2012-03-23 2013-09-26 株式会社日立産機システム Power conversion device
JP2020505901A (en) * 2017-01-11 2020-02-20 カリィ テクノロジCaly Technologies Devices for protection of electrical equipment
JP2020109698A (en) * 2016-07-04 2020-07-16 ハン−ウィン テクノロジー カンパニー リミテッドHan−Win Technology Co. Ltd. Power supply apparatus with soft start and protection

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013140874A1 (en) * 2012-03-23 2013-09-26 株式会社日立産機システム Power conversion device
JP2013198383A (en) * 2012-03-23 2013-09-30 Hitachi Industrial Equipment Systems Co Ltd Power conversion device
JP2020109698A (en) * 2016-07-04 2020-07-16 ハン−ウィン テクノロジー カンパニー リミテッドHan−Win Technology Co. Ltd. Power supply apparatus with soft start and protection
JP2020505901A (en) * 2017-01-11 2020-02-20 カリィ テクノロジCaly Technologies Devices for protection of electrical equipment

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