JP2000058818A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent leak current in a drain side end in MOSFET having the gate electrode of two layer structure through the use of tungsten and the like on an upper layer. SOLUTION: A silicon substrate 1 is etched/removed to a prescribed depth at the periphery of a gate electrode, and an oxide film thick part is formed at the end part of a gate oxide film 2. The film thickness of the gate oxide film at the end is set to 1.4-3.0 times as large as the thickness of a center part. The gate electrode is set to two layer structure formed of phosphorus dope polysilicon 3 and WSi4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a gate electrode using a metal material such as tungsten and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in order to respond to the demand for high-speed devices, a method of using a MOSFET with a two-layered gate electrode has been widely used. FIG.
Reference numeral 1 denotes an example. This MOSFET
Has a gate electrode provided on a silicon substrate 1 with a gate oxide film 2 interposed therebetween. The gate electrode has a lower layer made of phosphorus-doped polysilicon 3 and an upper layer made of WSi (tungsten silicide) 4. When the gate electrode has such a two-layer structure, the resistance of the gate electrode can be reduced and the speed of the element can be increased.

Hereinafter, a conventional method for manufacturing a MOSFET will be described with reference to FIG.

First, a silicon oxide film 2 having a thickness of about 10 nm which becomes a gate oxide film on the silicon substrate surface by thermal oxidation.
To form Then, on top of it, phosphorus-doped silicon 3,
WSi4 is formed by a CVD method. The film thickness is 1 each
It is about 00 nm. Subsequently, these unnecessary portions are removed and patterned into a gate electrode shape (FIG. 12).
(A)).

Next, a heat treatment is performed in an atmosphere containing oxygen to form a silicon oxide film 5 on the side surface.
(B)). The condition of the heat treatment is, for example, an atmosphere temperature of 80
0 ° C., treatment time 40 minutes. This is a condition under which a 5 nm-thick thermal oxide film is formed when a silicon substrate having a flat surface is processed.

Subsequently, diffusion layers 6 are formed by ion implantation (FIG. 12C).

[0007]

However, in the above prior art, the GIDL is formed at the end of the gate electrode on the drain side.
(Gate Induced Drain Leakage Current), which is a problem. This is because the electric field is concentrated at the end of the gate electrode, so that a leak current due to a tunnel phenomenon occurs.

The occurrence of GIDL has not been a serious problem in conventional MOSFETs having a single-layer gate electrode made of only polysilicon (polycrystalline silicon). The reason will be described below. In a MOSFET having a polysilicon gate, after forming a gate electrode, a thermal oxide film having a thickness of about 10 nm is formed in a relatively strong oxidation condition, for example, when a silicon substrate having a flat surface is processed in an oxidation process of a side surface portion. It was possible to perform oxidation under the following conditions. This is because, even if oxidation is performed under such strong oxidation conditions, polysilicon is not usually damaged by abnormal oxidation or the like. As a result, a bird's peak grew on the side wall, and as a result, a thick oxide film portion occurred at the gate end (FIG. 10). Due to the presence of this thick film,
Since the electric field concentration at the end of the gate electrode is reduced, the GI
DL was less likely to occur.

However, when a gate having a two-layer structure using tungsten or the like as an upper layer is used, oxidation cannot be performed under a strong oxidizing condition like a polysilicon gate. This is because, if oxidation is performed under strong oxidation conditions, tungsten or the like in the upper layer causes abnormal oxidation. Therefore, it is necessary to select a weak oxidation condition for the oxidation step of the side surface of the gate electrode, for example, a condition under which a thermal oxide film having a thickness of about 5 nm is formed when a silicon substrate having a flat surface is processed. Under such conditions, a bird's peak grows only slightly on the gate side wall, and a sufficient oxide film portion does not occur at the gate end (surrounded portion in FIG. 12B). For this reason, electric field concentration occurs at the end of the gate electrode, and the occurrence of GIDL becomes a problem. Although a method of forming an oxide film portion at the gate end by RTA (Rapid Thermal Annealing) is also conceivable, the process becomes complicated.

[0010] In recent years, the gate oxide film tends to be thinner with the miniaturization of elements. However, the generation of GIDL becomes more remarkable as the average thickness of the gate oxide film becomes thinner. Will be noticeable.

In addition, as the distance between the gate electrode and the contact hole becomes shorter with the miniaturization of the device, the GID
The problem of L becomes more pronounced. Usually, a sidewall oxide film made of non-doped silicon (hereinafter, referred to as “NSG film”) or the like is provided on the inner wall of the contact hole to prevent a short circuit between the metal film embedded in the hole and the gate electrode. However, the NSG film generates an interface state in the vicinity of a portion in contact with the substrate. When such an interface state occurs in the drain region, the GID due to the tunnel phenomenon occurs.
L is more likely to occur.

As described above, with the miniaturization of elements, measures against the above-mentioned problem of GIDL are more strongly desired than ever.

The present invention has been made in view of the above circumstances, and in a MOSFET having a two-layer gate electrode using tungsten or the like as an upper layer, generation of a leakage current (GIDL) at a drain side end is prevented. The purpose is to:

[0014]

According to the present invention, there is provided a silicon substrate, a gate electrode provided on the silicon substrate via a gate oxide film, and a gate electrode formed on both sides of the gate electrode. And a drain region, wherein the gate electrode has a lower layer portion made of polycrystalline silicon and an upper layer portion made of a metal material, and the gate oxide film at a gate length direction central portion of the gate electrode. The thickness of the gate oxide film at the end in the gate length direction of the gate electrode is 1.4 to 3.0 times the thickness of the gate oxide film at the center in the gate length direction.
There is provided a semiconductor device characterized by a factor of two.

In the present invention, the thickness of the central portion of the gate oxide film is 10 nm or less, while the thickness of the edge portion of the gate oxide film is 1.4 to 3.0 times that of the central portion. . Therefore, the concentration of the electric field at the boundary between the gate end and the drain region can be reduced, and the leak current can be effectively prevented. Further, since the gate electrode has an upper layer portion made of a metal material, excellent responsiveness can be obtained.

Here, the "central portion" of the gate oxide film is a portion sandwiched between a channel layer formed on the substrate surface and the gate electrode, and is a region near the center of the gate oxide film. The “end” of the gate oxide film refers to a region excluding the “center”. For example, in the semiconductor device of FIG. 1, the film thickness indicated by the arrow at the center is 10 nm or less, and the film thickness indicated by the arrow at the surrounding portion is 1.4 to 3.0 times that of the center.

Further, according to the present invention, in the above semiconductor device, the semiconductor device further includes an interlayer insulating film formed so as to bury the gate electrode, and an inner wall is provided at a predetermined position of the interlayer insulating film so as to be separated from the gate electrode. Is a semiconductor device having a contact hole covered with a silicon oxide film and having a drain region between the gate electrode and the contact hole, wherein the following formula (1) or (2) is satisfied. Semiconductor device is provided.

[0018]

(Equation 2) (The distance between the end on the gate electrode side where the silicon oxide film contacts the silicon substrate and the end of the gate oxide film on the contact hole side is x (nm), and the end of the gate oxide film is The film thickness of Tox (nm), the voltage between the gate electrode and the drain region is V _DG (V), the impurity concentration of the drain region is N _D (cm ⁻³ ), and the operating temperature of the semiconductor device is T (K).)

In a semiconductor device in which a contact hole is provided near a gate electrode, the occurrence of GIDL depends not only on the thickness of the gate oxide film but also on the distance between the gate electrode and the end of the contact hole. receive. This is because, as described above, an interface level is generated in the drain region by the oxide film on the side wall of the hole. The present invention clarifies the influence of the thickness of the end portion of the gate oxide film and the distance between the gate electrode and the end portion on the contact hole side on the threshold value of GIDL, and defines these relationships. ADVANTAGE OF THE INVENTION According to this invention, GIDL can be prevented more effectively and the threshold value of GIDL can be improved.

Further, according to the present invention, (A) a step of forming a silicon oxide film, a polycrystalline silicon film, and a metal silicide film or a metal film on a silicon substrate surface in this order; Forming a gate electrode by removing unnecessary portions of the silicon oxide film, the polycrystalline silicon film, and the metal silicide film or the metal film by etching, and further etching the substrate to a predetermined depth. And (C) a step of performing heat treatment in an atmosphere containing oxygen.

According to this method of manufacturing a semiconductor device,
Since the substrate around the gate electrode is etched to a predetermined depth in the step (B), a portion located below the gate oxide film is exposed on the side surface of the gate electrode. Thus, when performing the heat treatment in the step (C), oxidation proceeds from the lower side of the gate oxide film on the side surface of the gate electrode, and a bird's beak grows. Thereby, a thick film portion can be formed at the end of the gate oxide film. In this method of manufacturing a semiconductor device, the thickness of the end of the gate oxide film can be precisely controlled by adjusting the etching amount of the substrate.

In the method of manufacturing a semiconductor device,
In the step (B), the substrate is preferably etched by 1 to 10 nm, more preferably by 2 to 5 nm. If the etching amount is less than 1 nm, the area of the exposed portion of the side surface of the gate electrode is small, and it may not be possible to sufficiently increase the thickness of the end portion of the gate oxide film. If it exceeds 10 nm, the film thickness at the end of the gate oxide film becomes too large, which may lower the device efficiency.

In the step (C), a heat treatment
It is preferable that a silicon oxide film be grown to a predetermined thickness at an end of the gate electrode in the gate length direction.
That is, it is preferably grown to 1.4 to 3.0 times, more preferably 2.0 to 2.5 times the central part.
This silicon oxide film corresponds to the end of the gate oxide film, and by setting this film thickness in the above range, a leak current can be effectively prevented.

In the step (D), the heat treatment is performed at 750.
It is preferably carried out at a temperature of ８850 ° C. By setting the temperature in such a range, the film thickness at the end of the gate oxide film can be controlled to an appropriate value.

According to the present invention, (A) a step of forming a silicon oxide film, a polycrystalline silicon film, and a metal silicide film or a metal film on a silicon substrate surface in this order; and (B) the silicon oxide film Forming a gate electrode by removing unnecessary portions of a polycrystalline silicon film and a metal silicide film or a metal film; and (C) performing a first heat treatment in an atmosphere containing oxygen to form a gate electrode peripheral portion. Forming a silicon thermal oxide film on the surface of the substrate, and removing the silicon thermal oxide film; and (D) performing a second heat treatment in an atmosphere containing oxygen. An apparatus manufacturing method is provided.

According to the method of manufacturing a semiconductor device of the present invention, the thickness of the edge of the gate oxide film can be controlled more precisely. This is because the thickness of the silicon thermal oxide film can be easily controlled by adjusting the heating conditions in the step (C).

In this method of manufacturing a semiconductor device,
In the step (C), the thickness of the silicon thermal oxide film is set to 2 to 20 n.
m is preferable. Performing the step (C) several times,
The total thickness of the removed silicon thermal oxide film is 2 to 20 nm.
It can also be. The thickness of the silicon thermal oxide film corresponds to about twice the substrate etching amount. If this value is less than 2 nm, the area of the exposed portion of the side surface of the gate electrode is so small that the thickness of the end portion of the gate oxide film cannot be sufficiently increased in some cases. If the thickness exceeds 20 nm, the thickness of the end portion of the gate oxide film may be too large, which may lower the device efficiency. In order to more precisely control the thickness of the silicon thermal oxide film, it is more preferable to make the thickness of the silicon thermal oxide film 2 to 5 nm by one thermal oxidation in the step (C).

In the step (D), heat treatment
It is preferable that a silicon oxide film be grown to a predetermined thickness at an end of the gate electrode in the gate length direction.
That is, it is preferably grown to 1.4 to 3.0 times, more preferably 2.0 to 2.5 times the central part.
This silicon oxide film corresponds to the end of the gate oxide film, and by setting this film thickness in the above range, a leak current can be effectively prevented.

In the step (D), the heat treatment is performed at 750.
It is preferably carried out at a temperature of ８850 ° C. By setting the temperature in such a range, the film thickness at the end of the gate oxide film can be controlled to an appropriate value.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the semiconductor device of the present invention, the metal material includes not only a metal such as tungsten and aluminum but also a metal silicide such as tungsten silicide. For example, one or more materials selected from the group consisting of tungsten, copper, tungsten silicide, titanium silicide, molybdenum silicide, and cobalt silicide can be used. By using such a material, the resistance of the gate electrode can be reduced.

In the semiconductor device of the present invention, the gate oxide film is thick at the end. In order to obtain such a structure, it is preferable that the substrate is removed to a predetermined depth around the gate electrode. By doing so, thermal oxidation from the side of the gate electrode is promoted in the manufacturing process, so that a structure in which the gate oxide film has a large thickness at the gate end can be easily formed. Further, the thickness of the gate end can be precisely controlled.
Here, regarding the removal amount of the substrate around the gate electrode,
Preferably 1 to 10 nm, more preferably 2 to 5 nm
Shall be removed to the depth of. If the thickness is less than 1 nm, the area of the exposed portion of the side surface of the gate electrode is so small that the thickness of the end portion of the gate oxide film may not be sufficiently increased. 10
If it exceeds nm, the film thickness at the end of the gate oxide film becomes too large, which may cause a decrease in device efficiency.

In the method for manufacturing a semiconductor device according to the present invention,
The metal silicide film or the metal film is preferably made of one or more materials selected from the group consisting of, for example, tungsten, copper, tungsten silicide, titanium silicide, molybdenum silicide, and cobalt silicide. By using such a material, the resistance of the gate electrode can be reduced.

Hereinafter, a preferred embodiment of the present invention will be described.

(First Embodiment) A first embodiment of the present invention will be described with reference to FIG. The semiconductor device shown in FIG. 1 is formed on a silicon substrate 1 with a gate oxide film 2 interposed therebetween.
A gate electrode is provided. The gate electrode has a lower layer made of phosphorus-doped polysilicon 3 and an upper layer made of WSi4. A diffusion layer 6 is provided in the vicinity of the substrate surface.
A silicon oxide film 5 is formed. The thickness of the end portion of the gate oxide film 2 (arrow portion in the encircled portion in the figure) is 1.4 to 1.4 in the central portion.
3.0 times, preferably 2.0 to 2.5 times. With such a thickness, the concentration of the electric field at the boundary between the gate end and the drain region can be reduced, and the leakage current can be effectively prevented. On the other hand, the thickness of the central portion of the gate oxide film is set to 10 nm or less. With such a film thickness, a device having good responsiveness can be obtained, and it is possible to meet a demand for miniaturization of the device. Although there is no particular lower limit of the thickness of the central portion of the gate oxide film, for example, 1
nm or more.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIG. The semiconductor device shown in FIG. 2 is formed on a silicon substrate 1 with a gate oxide film 2 interposed therebetween.
A gate electrode is provided. The gate electrode has a lower layer made of phosphorus-doped polysilicon 3 and an upper layer made of WSi (tungsten silicide) 4. A diffusion layer 6 is provided near the substrate surface, and a silicon oxide film 5 is formed on the surface of the gate electrode and the silicon substrate 1. Then, an interlayer insulating film 8 is formed so as to bury the gate electrode, and a contact hole 10 is formed in the interlayer insulating film 8 near the gate electrode. An NSG film 9 is formed on the inner wall of the contact hole 10.

As described above, the contact hole is provided close to the gate electrode, and the NSG by the CVD method is formed on the inner wall thereof.
In a semiconductor device on which a film is formed, an interface state occurs at a position where the NSG film and the substrate are in contact with each other. Therefore G
Whether or not IDL is generated depends not only on the thickness of the gate oxide film but also on the thickness of the gate oxide film.
It is also affected by the distance (x in the figure) between the gate electrode and the end of the contact hole. Specifically, when the depletion layer extending in the lateral direction from directly below the gate electrode reaches a position where the silicon oxide film and the substrate are in contact with each other, GIDL is likely to occur due to the influence of the interface state.

Therefore, in the semiconductor device as shown in FIG. 2, the thickness of the gate oxide film at the end of the gate electrode (T _ox in the figure) and the distance between the gate electrode and the end of the contact hole (x in the figure) Is a factor in determining whether or not GIDL has occurred.

Therefore, in the present embodiment, the influence of the thickness of the end portion of the gate oxide film and the distance between the gate electrode and the end portion on the contact hole side on the GIDL threshold is clarified, and these relationships are optimized. I have.

In the present embodiment, the thickness of the end portion of the gate oxide film 2 is 1.4 to 3.0 times the central portion, preferably 2.0 to 3.0 times.
2.5 times. On the other hand, the thickness of the central portion of the gate oxide film is set to 10 nm or less.

Further, x and _Tox shown in the figure satisfy the following equation (1) or (2).

[0041]

(Equation 3)

X is the distance between the end on the gate electrode side where the NSG film 9 contacts the diffusion layer 6 on the surface of the silicon substrate and the end on the contact hole side of the gate oxide film 2.
_Tox is the film thickness at the end of the gate oxide film. Further, the voltage between the gate electrode and the drain region is V _DG (V), the impurity concentration of the drain region is N _D (cm ⁻³ ), and the operating temperature of the semiconductor device is T (K).

By designing the semiconductor device so as to satisfy the above formula (1) or (2), it is possible to effectively prevent generation of a leak current even when a contact hole is provided close to the gate electrode. Can be. Thus, a semiconductor device which is excellent in withstand voltage characteristics in which generation of a leak current is suppressed while responding to a demand for miniaturization of an element is provided.

The above equations (1) and (2) are derived as follows. The width L of the depletion layer extending immediately below the gate electrode is
It is given by the following equation (3).

[0045]

(Equation 4)

Here, if the value of x (the distance between the contact hole and the gate) is larger than the extension of the depletion layer, that is, if x> L, the frequency of occurrence of GIDL can be significantly reduced. Substituting equation (3) into this inequality,
Further, by substituting the following numerical values, the above equation (1) is obtained. ε ₀ = 8.854 × 10 ^-12 [F / m] ε _s = 11.8 ε _OX = 3.9 q = 1.602 × 10 ^-19 [C]

Further, according to the depletion layer approximation, there is an upper limit to the extent of the depletion layer, and the value _Lmax is given by the following equation (4).

[0048]

(Equation 5)

[0049] If is larger in x than the L _max, that is, it is possible to significantly reduce the frequency of GIDL if x> L _max.

By substituting the above equation (4) into this inequality, and further substituting the following numerical values, the above equation (2) is obtained. ^{_{ε 0 = 8.854 × 10 -12 [}} F / m] ε s = 11.8 k = 1.38 × 10 -23 [J / K] n i = 1.5 × 10 16 [m -3] q = 1.602 × 10 ^-19 [C]

As described above, if Expression (1) or (2) is satisfied, GIDL is prevented.

FIG. 3 shows the result of a simulation of the relationship between the thickness of the gate oxide film at the end of the gate electrode and the width of the depletion layer. The voltage between the drain and the gate was 2 V and 3 V. In the figure, the points indicated by open triangles are the simulation results when N _D = 5 × 10 ¹⁷ cm ⁻³ , and the points indicated by black squares are the results when N _D = 1 × 10 ¹⁸ cm ⁻³ . To prevent the occurrence of GIDL, the distance x between the gate electrode and the contact hole side end in FIG.
Should be larger than the width of the depletion layer. Therefore,
If the distance x between the gate electrode and the end of the contact hole and the thickness T _ox of the oxide film at the end of the gate are designed so as to fall within the region located above the solid line in FIG. Can be prevented.

Therefore, in the semiconductor device of this embodiment, the relationship between the thickness of the gate oxide film and the distance x between the gate electrode and the contact hole is within the above-described region, and the thickness of the end portion of the gate oxide film is Is 1.4 to 3.0 times that of the central portion, and the central portion of the gate oxide film has a thickness of 10 nm or less to prevent GIDL. Note that the NSG film or the like formed by the CVD method comes into contact with the substrate as described above even when a gate electrode and a sidewall are formed. That is, when the NSG film formed by the CVD method is used as an interlayer insulating film and is applied so as to cover the gate electrode and the sidewall, the NSG film comes into contact with the substrate. In this case, when the width of the sidewall is x and this x satisfies the above equations (1) and (2), GIDL is prevented.

[0054]

(First Embodiment) A first embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 4, a silicon oxide film 2 serving as a gate oxide film having a thickness of about 10 nm was formed on the surface of a silicon substrate by thermal oxidation. Next, phosphorus-doped polysilicon 3 and WSi4 were formed thereon to have a thickness of 100 nm by the CVD method, respectively (FIG. 4A).

Subsequently, a gate electrode was formed by patterning the silicon oxide film 2, the phosphorus-doped polysilicon 3 and the WSi4. The gate length was 0.3 μm (FIG. 4)
(B)).

Next, the silicon substrate 1 around the gate electrode was dry-etched by 3 nm except for the position where the gate electrode was provided (FIG. 4C).

The heat treatment was performed in this state. The conditions of the heat treatment were an atmosphere temperature of 800 ° C. and a treatment time of 40 minutes.
This is a condition under which a 5 nm-thick thermal oxide film is formed when a silicon substrate having a flat surface is processed. A silicon oxide film is formed on the entire surface by this thermal oxidation. At this time, a thick film portion of the gate oxide film 2 is formed at the gate end (FIG. 5D). This is because the silicon substrate 1 around the gate electrode is dug down by etching in the previous step, so that oxidation from the exposed side surface of the gate electrode progresses and bird's beaks occur at the upper and lower portions of the gate oxide film 2. is there. In this regard, according to the prior art, bird's beak is hardly generated only above the gate oxide film 2 as shown in the encircled portion in FIG. This is because the oxidation does not proceed in this portion because the polysilicon below the gate oxide film 2 is not exposed.

After that, the diffusion layer 6 was formed by ion implantation to complete the MOSFET (FIG. 5E). The order of forming the silicon oxide film 5 and performing ion implantation may be reversed.

When the cross section of the completed MOSFET was observed by SEM, it was confirmed that the thickness of the silicon oxide film at the end of the gate electrode was 14 nm. Abnormal oxidation of WSi4 was not observed.

According to the method of the present embodiment, a thick film portion can be formed at the end of the gate oxide film 2 even under relatively weak oxidation conditions such that abnormal oxidation of WSi does not occur. Thus, concentration of the electric field at the boundary between the gate end and the drain region can be reduced, and leakage current can be effectively prevented.

The MOSFE manufactured by the method of this embodiment
The hold time of a DRAM having T as a memory cell transistor was evaluated. FIG. 7 shows the results. In the figure, A is a product prepared without performing side oxidation, B
Indicates a side surface oxidized by the conventional method shown in FIG. 12, and C indicates a side surface oxidized by the method of the present embodiment. Both side oxidations of B and C were performed at an ambient temperature of 800.
C., the processing time was 40 minutes, and the conditions were such that a thermal oxide film having a thickness of 4 nm was formed when a silicon substrate having a flat surface was processed. The difference between the two is that B performs side oxidation without etching the substrate as shown in FIG. 12B (condition 1), and C etches the substrate as shown in FIG. After that, the side oxidation is performed (condition 2). The film thickness of the central part of the gate oxide film is 10 nm in all of A to C. On the other hand, the film thickness at the end of the gate oxide film is A
Is 10 nm, B is 12 nm, and C is 14 nm. That is, the thickness of the oxide film derived from the bird's beak generated by the side oxidation is 0 nm for A, 2 nm for B, and 4 nm for C.
As shown in the figure, according to the method of the present embodiment (C in the figure),
It is clear that the hold time can be significantly improved.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIG. The method shown in the present embodiment differs from the first embodiment in the step of etching the silicon substrate around the gate electrode.

First, a silicon oxide film 2 serving as a gate oxide film was formed to a thickness of about 10 nm on the surface of a silicon substrate by thermal oxidation. Next, a phosphorus-doped polysilicon 3 and a WSi 4 are respectively formed thereon by a CVD method to a thickness of 100 nm.
The film was formed with a thickness of nm (FIG. 8A).

Subsequently, the gate electrode was formed by patterning the silicon oxide film 2, the phosphorus-doped polysilicon 3 and the WSi4. At this time, the etching stops at the Si substrate (FIG. 8B). The gate length was 0.3 μm.

Next, an atmosphere temperature of 800 ° C. and a processing time of 40
The first heat treatment was performed in minutes. This is a condition under which a thermal oxide film having a thickness of 4 nm is formed when a silicon substrate having a flat surface is processed. This thermal oxidation forms a silicon thermal oxide film 7 on the entire surface (FIG. 8C).

Next, the silicon thermal oxide film 7 is removed by dry etching or wet etching. Thus, except for the position where the gate electrode is provided, the silicon substrate 1 around the gate electrode is etched by about half the thickness of the silicon thermal oxide film 7. (FIG. 8D).

Thereafter, a second heat treatment was performed in the same manner as in the first embodiment, and a bird's beak was generated by oxidizing the side surface of the gate electrode. Next, a diffusion layer 6 is formed, and a MOS
The FET was completed.

According to the method of this embodiment, the silicon substrate 1 can be etched by about half the thickness of the silicon thermal oxide film 7. Since the bird's beak length formed below the gate oxide film 2 can be controlled by adjusting the etching amount, the thickness of the end portion of the gate oxide film 2 is controlled by adjusting the thickness of the silicon thermal oxide film 7 after all. be able to. Here, the thickness of the silicon thermal oxide film 7 can be easily controlled by adjusting the oxidation conditions. Therefore, according to the method of this embodiment, the thickness of the end portion of the gate oxide film 2 can be controlled as designed. .

(Third Embodiment) The first and second embodiments described above
In the embodiment, immediately after the silicon substrate 1 around the gate electrode is etched (FIGS. 4C and 8D), the side surface of the gate oxide film 2 may be etched by wet etching. As an etchant, for example, dilute hydrofluoric acid (HF: H ₂ O = 1: 200 to 1: 400) can be used. By etching the side surface so that the gate oxide film 2 is recessed inward as shown in FIG. 9, the progress of oxidation from the side surface of the gate electrode can be further promoted. Thus, the thickness of the end portion of the gate oxide film 2 can be sufficiently increased even under weak oxidation conditions that do not adversely affect the metal film on the gate electrode.

[0071]

As described above, in the semiconductor device of the present invention, since the thickness of the gate oxide film is increased at the end, the concentration of the electric field is reduced at the boundary between the gate end and the drain region, and the leakage is reduced. Current can be effectively prevented. Further, since the upper layer of the gate electrode is made of a metal material, excellent responsiveness can be obtained.

In the method of manufacturing a semiconductor device according to the present invention, since the substrate around the gate electrode is etched to a predetermined depth, the progress of oxidation on the side surface of the gate electrode is promoted, and a thick film is formed at the end of the gate oxide film. can do. The thickness of the end portion of the gate oxide film can be precisely controlled by adjusting the etching amount of the substrate.

In the method of manufacturing a semiconductor device according to the present invention, if a method of removing a substrate around a gate electrode by forming a silicon thermal oxide film by heat treatment and then removing the silicon thermal oxide film is employed, The film thickness at the end of the oxide film can be controlled more precisely.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is a schematic sectional view of a semiconductor device according to the present invention.

FIG. 3 is a diagram showing a relationship between a gate oxide film and the extension of a depletion layer.

FIG. 4 is a process sectional view of the method for manufacturing a semiconductor device according to the present invention;

FIG. 5 is a process sectional view of the method for manufacturing a semiconductor device according to the present invention;

FIG. 6 is a process sectional view of the method for manufacturing a semiconductor device according to the present invention;

FIG. 7 is a diagram showing the results of evaluation of the hold times of the semiconductor device of the present invention and the semiconductor device according to the related art.

FIG. 8 is a process sectional view of the method for manufacturing a semiconductor device according to the present invention;

FIG. 9 is a process sectional view of the semiconductor device manufacturing method of the present invention.

FIG. 10 is a schematic sectional view of a conventional semiconductor device.

FIG. 11 is a schematic sectional view of a conventional semiconductor device.

FIG. 12 is a process sectional view of a conventional semiconductor device manufacturing method.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 gate oxide film 3 phosphorus-doped polysilicon 4 WSi 5 silicon oxide film 6 diffusion layer 7 silicon oxide film 8 interlayer insulating film 9 NSG film 10 contact hole

Claims (14)

[Claims] 1. A gate electrode comprising: a silicon substrate; a gate electrode provided on the silicon substrate via a gate oxide film; and a source region and a drain region formed on both sides of the gate electrode. Has a lower layer portion made of polycrystalline silicon and an upper layer portion made of a metal material, the thickness of the gate oxide film at the central portion in the gate length direction of the gate electrode is 10 nm or less, The thickness of the gate oxide film at the end is 1.4 to 3 times the thickness of the gate oxide film at the center in the gate length direction.
A semiconductor device characterized in that it is 0 times. 2. The method according to claim 1, wherein the upper layer of the gate electrode is made of one or more materials selected from the group consisting of tungsten, copper, tungsten silicide, titanium silicide, molybdenum silicide, and cobalt silicide. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the substrate is removed to a predetermined depth around the gate electrode. 4. A contact hole, further comprising an interlayer insulating film formed so as to bury the gate electrode, and a predetermined position of the interlayer insulating film being spaced apart from the gate electrode and having an inner wall covered with a silicon oxide film. 4. A semiconductor device having a drain region between the gate electrode and the contact hole, wherein the following formula (1) or (2) is satisfied. Semiconductor device. (Equation 1) (The distance between the end on the gate electrode side where the silicon oxide film contacts the silicon substrate and the end of the gate oxide film on the contact hole side is x (nm), and the end of the gate oxide film is The film thickness of Tox (nm), the voltage between the gate electrode and the drain region is V _DG (V), the impurity concentration of the drain region is N _D (cm ⁻³ ), and the operating temperature of the semiconductor device is T (K).) 5. A step of forming a silicon oxide film, a polycrystalline silicon film, and a metal silicide film or a metal film on a silicon substrate surface in this order, and FIG. Later, the silicon oxide film,
Forming a gate electrode by removing unnecessary portions of the polycrystalline silicon film and the metal silicide film or the metal film by etching, and further etching the substrate to a predetermined depth; and (C) heating in an atmosphere containing oxygen Performing a process. 6. In the step (B), the silicon substrate is
The method for manufacturing a semiconductor device according to claim 5, wherein etching is performed to 10 to 10 nm. 7. In the step (C), by the heat treatment,
At the end of the gate electrode in the gate length direction, the silicon oxide film has a thickness of 1.
7. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is grown to a thickness of 4 to 3.0 times. 8. In the step (C), the heat treatment is performed at 750.
The method for manufacturing a semiconductor device according to claim 5, wherein the method is performed at a temperature of from −850 ° C. 9. A step of (A) forming a silicon oxide film, a polycrystalline silicon film, and a metal silicide film or a metal film on a silicon substrate surface in this order; and (B) forming the silicon oxide film and the polycrystalline silicon film. Forming a gate electrode by removing unnecessary portions of the metal silicide film or the metal film; and (C) performing a first heat treatment in an atmosphere containing oxygen to form silicon on the substrate surface around the gate electrode. A method for manufacturing a semiconductor device, comprising: after forming a thermal oxide film, removing the silicon thermal oxide film; and (D) performing a second heat treatment in an atmosphere containing oxygen. 10. The method according to claim 9, wherein in the step (C), the thickness of the silicon thermal oxide film is set to 2 to 20 nm. 11. The method according to claim 9, wherein the step (C) is performed a plurality of times, and the total thickness of the removed silicon thermal oxide film is set to 2 to 20 nm. 12. In the step (D), by the second heat treatment, at the gate length direction end of the gate electrode,
12. The semiconductor device according to claim 9, wherein the silicon oxide film is grown to a thickness of 1.4 to 3.0 times the thickness at the central portion in the gate length direction. Manufacturing method. 13. The method of manufacturing a semiconductor device according to claim 9, wherein in the step (D), the second heat treatment is performed at a temperature of 750 to 850 ° C. 14. The metal silicide film or the metal film is made of one or two or more materials selected from the group consisting of tungsten, copper, tungsten silicide, titanium silicide, molybdenum silicide, and cobalt silicide. A method for manufacturing a semiconductor device according to claim 5.