JP2000058718A - Resin sealed semiconductor device - Google Patents

Resin sealed semiconductor device

Info

Publication number
JP2000058718A
JP2000058718A JP23092298A JP23092298A JP2000058718A JP 2000058718 A JP2000058718 A JP 2000058718A JP 23092298 A JP23092298 A JP 23092298A JP 23092298 A JP23092298 A JP 23092298A JP 2000058718 A JP2000058718 A JP 2000058718A
Authority
JP
Japan
Prior art keywords
resin
substrate
semiconductor device
molding
peeling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23092298A
Other languages
Japanese (ja)
Other versions
JP3732660B2 (en
Inventor
Shigesato Yamanaka
林里 山中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP23092298A priority Critical patent/JP3732660B2/en
Publication of JP2000058718A publication Critical patent/JP2000058718A/en
Application granted granted Critical
Publication of JP3732660B2 publication Critical patent/JP3732660B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

PROBLEM TO BE SOLVED: To surely prevent the peeling of a molding resin from a substrate by providing notched sections on the peripheral edge section of a substrate so as to make the molding resin flow in the notched section when the resin molded. SOLUTION: A BGA semiconductor device A has a package constituted by molding an IC chip 2 and bonding wires 3 with a thermosetting resin 5 on the upper surface of a nearly square film substrate 1. Since the resin 5 which flows and cures in notched sections 6 at the time of molding the resin 5 holds the substrate 1 in a wrapping state, the adhesion between the substrate 1 and resin 5 is improved and the peeling of the resin 5 from the substrate 1 can be prevented efficiently. Therefore, the peeling of the resin 5 from the substrate 1 from which the resin 5 easily peels can be prevented efficiently even when the number of notched sections 6 is small, because the resin 5 holds the substrate 1 by wrapping the corner sections of the substrate 1.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、樹脂封止型半導
体装置に関し、詳しくはそのパッケージ構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device, and more particularly, to a package structure thereof.

【0002】[0002]

【従来の技術】従来、樹脂封止型半導体装置としてBG
A型半導体装置が知られており、図4に示すように、か
かるBGA型半導体装置Xは、基板100 にICチップ20
0 を搭載・固着し、同ICチップ200 の端子と、基板10
0 上に形成してある導通パタン(図示せず)とをボンデ
ィングワイヤ300 で接続し、さらに、ICチップ200 及
びボンディングワイヤ300 とを熱硬化性のモールド用樹
脂400 でモールドしてパッケージ化している。
2. Description of the Related Art Conventionally, BG has been used as a resin-encapsulated semiconductor device.
An A-type semiconductor device is known. As shown in FIG. 4, such a BGA type semiconductor device X has an IC chip 20 mounted on a substrate 100.
0 is mounted and fixed, and the terminals of the IC chip 200 and the substrate 10
0 is connected to a conductive pattern (not shown) formed thereon by a bonding wire 300, and the IC chip 200 and the bonding wire 300 are molded with a thermosetting molding resin 400 to form a package. .

【0003】基板100 の裏面には半田バンプ500 が形成
されており、同半田バンプ500 と前記導通パタンとを、
図示しないスルーホールを介して導通させることで、I
Cチップ200 と半田バンプ500 とを導通させている。
A solder bump 500 is formed on the back surface of the substrate 100. The solder bump 500 and the conduction pattern are
By conducting through a not-shown through hole, I
The C chip 200 and the solder bump 500 are conducted.

【0004】基板100 はリードフレームに連続状に形成
されており、前記したようにパッケージ化された後にリ
ードフレームから切り離されて単品化される。
The substrate 100 is formed continuously on a lead frame. After being packaged as described above, the substrate 100 is cut off from the lead frame and made into a single product.

【0005】また、基板100 は、ガラスエポキシ樹脂等
で板状に形成されたものが一般的であるが、近年では、
量産化を図るべく、ポリプロピレン樹脂等からなるフィ
ルム体が用いられることも多い。
The substrate 100 is generally formed in a plate shape with glass epoxy resin or the like.
For mass production, a film made of a polypropylene resin or the like is often used.

【0006】[0006]

【発明が解決しようとする課題】ところが、上記した従
来のBGA型半導体装置Xのパッケージ構造では、図示
したように、モールド用樹脂400 が基板100 の上面にの
みモールドされているために、基板100 表面との溶着が
不十分となって、単品カット時などにモールド用樹脂40
0 が基板100 から剥離しやすいという欠点があった。
However, in the package structure of the conventional BGA type semiconductor device X described above, since the molding resin 400 is molded only on the upper surface of the substrate 100 as shown in the figure, Insufficient welding to the surface causes molding resin 40
0 has a disadvantage that it is easily peeled from the substrate 100.

【0007】すなわち、基板100 とモールド用樹脂400
との材質が異なるので熱膨張率が異なり、モールド時に
反りを生じ、基板100 とモールド樹脂400 との密着性が
低下し、さらに、BGA型半導体装置Xの実装時やリフ
ロー時にも同様に反りを生じるので剥離しやすい。特
に、基板100 がフィルム体であると、その傾向が顕著で
ある。
That is, the substrate 100 and the molding resin 400
Because of the different materials, the coefficient of thermal expansion is different, warpage occurs during molding, the adhesion between the substrate 100 and the molding resin 400 is reduced, and the warpage is similarly caused during mounting and reflow of the BGA type semiconductor device X. It is easy to peel off. This tendency is particularly remarkable when the substrate 100 is a film.

【0008】かかる剥離が生じると、接合面から吸湿し
てBGA型半導体装置Xの実装時やリフロー時にパッケ
ージクラックの原因となるので、モールド用樹脂400 の
剥離防止が大きな課題となっている。
[0008] When such peeling occurs, moisture is absorbed from the bonding surface and causes package cracking at the time of mounting or reflowing the BGA type semiconductor device X. Therefore, preventing peeling of the molding resin 400 is a major problem.

【0009】本発明は、上記課題を解決することのでき
る樹脂封止型半導体装置を提供することを目的としてい
る。
An object of the present invention is to provide a resin-sealed semiconductor device which can solve the above-mentioned problems.

【0010】[0010]

【課題を解決するための手段】そこで、上記課題を解決
するために、請求項1記載の本発明では、基板上面にI
Cチップを固着してワイヤボンディングし、樹脂モール
ドした樹脂封止型半導体装置において、基板の周側部
に、樹脂モールド時にモールド用樹脂を流入させる切欠
部を設けた。したがって、切欠部に流入して硬化したモ
ールド用樹脂が基板を包み込むようにホールドした状態
となり、モールド部の剥離を防止することができる。
Therefore, in order to solve the above-mentioned problems, according to the present invention, in accordance with the present invention, I
In a resin-encapsulated semiconductor device in which a C chip is fixed, wire-bonded, and resin-molded, a notch portion through which molding resin flows during resin molding is provided on the peripheral side of the substrate. Therefore, the mold resin that has flowed into the cutout portion and hardened is held so as to enclose the substrate, and peeling of the mold portion can be prevented.

【0011】また、請求項2記載の本発明では、前記切
欠部を、基板上の導通パタンを避けた位置に設けた。
Further, in the present invention, the notch is provided at a position on the substrate which avoids the conduction pattern.

【0012】また、請求項3記載の本発明では、前記切
欠部を、基板の周縁部に複数個設けた。
Further, in the present invention, a plurality of the notches are provided in a peripheral portion of the substrate.

【0013】さらに、請求項4記載の本発明では、前記
切欠部を、少なくとも基板の四隅に設けた。
Further, according to the present invention, the notches are provided at least at four corners of the substrate.

【0014】[0014]

【発明の実施の形態】本発明は、基板上面にICチップ
を固着してワイヤボンディングし、樹脂モールドした樹
脂封止型半導体装置において、基板の周側部に、樹脂モ
ールド時にモールド用樹脂を流入させる切欠部を設けた
ものである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a resin-encapsulated semiconductor device in which an IC chip is fixed on the upper surface of a substrate, wire-bonded, and resin-molded, and a molding resin flows into a peripheral portion of the substrate during resin molding. It is provided with a notch portion to be made.

【0015】すなわち、基板の周側部に予め切欠部を設
けておき、モールド時に同切欠部内にモールド用樹脂を
流入させ、かかるモールド用樹脂を基板の下面まで至ら
せることで、硬化したときにモールド用樹脂が基板を包
み込むようにホールドして密着性を向上させ、モールド
用樹脂と基板との剥離を防止したものである。
That is, a notch is provided in advance on the peripheral side of the substrate, the molding resin flows into the notch at the time of molding, and the molding resin reaches the lower surface of the substrate. The mold resin is held so as to enclose the substrate to improve the adhesion, thereby preventing the mold resin from separating from the substrate.

【0016】切欠部を設ける箇所は、半導体装置の機能
を阻害することのないように基板上に形成された導通パ
タンを避ける箇所とし、その箇所としては、例えば基板
の周縁とすることが考えられる。
The location where the notch is provided is a location where a conductive pattern formed on the substrate is avoided so as not to hinder the function of the semiconductor device, and the location may be, for example, the periphery of the substrate. .

【0017】また、切欠部の個数としては特に限定する
ものではないが、基板の各辺に1個ずつ、もしくは、基
板の四隅にそれぞれ設けることができる。
Although the number of cutouts is not particularly limited, one cutout may be provided on each side of the board or at each of the four corners of the board.

【0018】特に、四隅に設けた場合は、少ない個数で
効率的に基板とモールド用樹脂との剥離を防止すること
ができる。
In particular, when provided at the four corners, the separation of the substrate and the molding resin can be efficiently prevented with a small number.

【0019】また、基板の各辺に複数個の切欠部を設け
てモールドすることもでき、モールド用樹脂による基板
のホールド力を大きくして密着性をより向上させること
もできる。
Also, a plurality of notches can be provided on each side of the substrate for molding, and the holding force of the substrate by the molding resin can be increased to further improve the adhesion.

【0020】このように、本発明によれば、モールド用
樹脂と基板との密着性が向上してモールド用樹脂の基板
からの剥離を効果的に防止することができる。
As described above, according to the present invention, the adhesion between the molding resin and the substrate is improved, and the peeling of the molding resin from the substrate can be effectively prevented.

【0021】特に、基板を薄いフィルム体とした場合に
はその効果は大きくなり、フィルム体を基板とし、か
つ、かかるフィルム基板の欠点であるモールド用樹脂の
剥離を防止して不良品の発生を可及的に抑えることによ
り、薄型で高品質のBGA型半導体装置の量産化を実現
することができる。
In particular, when the substrate is made of a thin film, the effect becomes great. The film is used as a substrate, and the molding resin, which is a drawback of such a film substrate, is prevented from being peeled off to prevent defective products. By suppressing as much as possible, mass production of a thin and high-quality BGA type semiconductor device can be realized.

【0022】[0022]

【実施例】以下、本発明の実施例を図面を参照しながら
具体的に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the drawings.

【0023】(第1実施例)図1は第1実施例に係る樹
脂封止型半導体装置としてのBGA型半導体装置Aの底
面図、図2は図1のI−I線における断面図である。
(First Embodiment) FIG. 1 is a bottom view of a BGA type semiconductor device A as a resin-sealed type semiconductor device according to a first embodiment, and FIG. 2 is a cross-sectional view taken along line II of FIG. .

【0024】図2に示すように、BGA型半導体装置A
は、ポリプロピレン等の樹脂製のフィルム体からなる略
正方形のフィルム基板1の上面にICチップ2を固着
し、フィルム基板1上に形成した図示しない導通パタン
にワイヤボンィングしている。
As shown in FIG. 2, a BGA type semiconductor device A
The IC chip 2 is fixed to the upper surface of a substantially square film substrate 1 made of a film made of resin such as polypropylene, and is wire-bonded to a conductive pattern (not shown) formed on the film substrate 1.

【0025】3はボンディングワイヤである。Reference numeral 3 denotes a bonding wire.

【0026】フィルム基板1の裏面には、半田バンプ4
がマトリックス状に多数突設されており、同半田バンプ
4と前記導通パタンとを図示しないスルーホールを介し
て導通させている。
On the back surface of the film substrate 1, solder bumps 4
Are provided in a matrix shape, and the solder bumps 4 and the conductive patterns are electrically connected through through holes (not shown).

【0027】そして、ICチップ2とボンディングワイ
ヤ3とを熱硬化性樹脂5によりモールドしてパッケージ
を構成している。
The IC chip 2 and the bonding wires 3 are molded with a thermosetting resin 5 to form a package.

【0028】かかる構成のBGA型半導体装置Aにおい
て、本発明の要旨となるのは、フィルム基板1の周側部
に、モールド用樹脂である熱硬化性樹脂5を流入させる
切欠部6を設けたことにある。
In the BGA type semiconductor device A having such a structure, the gist of the present invention is that a notch 6 into which a thermosetting resin 5 as a molding resin flows is provided on the peripheral side of the film substrate 1. It is in.

【0029】すなわち、熱硬化性樹脂5とフィルム基板
1とは、その材質の違いにより熱膨張率が異なるので、
樹脂モールド時や、後工程の半田バンプ4のリフロー
時、あるいは、BGA型半導体装置Aの実装時にパッケ
ージ自体に反りを生じ、フィルム基板1と熱硬化性樹脂
5とが剥離しやすくなるものであるが、上記構成とした
ことにより、モールド時に切欠部6に熱硬化性樹脂5が
流入して硬化し、かかる熱硬化性樹脂5がフィルム基板
1を包み込むようにホールドすることになるので、フィ
ルム基板1と熱硬化性樹脂5との密着性が向上して両者
の剥離を効率良く防止することができる。
That is, since the thermosetting resin 5 and the film substrate 1 have different coefficients of thermal expansion due to the difference in their materials,
The package itself is warped at the time of resin molding, at the time of reflow of the solder bumps 4 in a later process, or at the time of mounting the BGA type semiconductor device A, so that the film substrate 1 and the thermosetting resin 5 are easily separated. However, with the above-described configuration, the thermosetting resin 5 flows into the cutout portion 6 at the time of molding and is hardened, and the thermosetting resin 5 is held so as to enclose the film substrate 1. The adhesiveness between the thermosetting resin 1 and the thermosetting resin 5 is improved, and the peeling of the two can be efficiently prevented.

【0030】本実施例では、切欠部6を、図1に示すよ
うに、前記した導通パタン(図示せず)を避ける位置と
してフィルム基板1の四隅に形成している。
In this embodiment, as shown in FIG. 1, the notches 6 are formed at the four corners of the film substrate 1 so as to avoid the conductive patterns (not shown).

【0031】したがって、熱硬化性樹脂5が剥離しやす
いフィルム基板1の各角部を熱硬化性樹脂5が包み込ん
でホールドするので、切欠部6の個数が少なくても効率
的な剥離防止が可能となる。
Therefore, since the thermosetting resin 5 wraps and holds each corner of the film substrate 1 from which the thermosetting resin 5 is easily peeled, even if the number of the cutouts 6 is small, the peeling can be efficiently prevented. Becomes

【0032】フィルム基板1の四隅に設ける切欠部6
は、各フィルム基板1毎に形成してもよいが、フィルム
基板1を多数集合させた大判の集合基板フィルムにマト
リックス状に形成すれば、切欠部6を各フィルム基板1
の四隅により効率的に形成することができる。
Notches 6 provided at four corners of film substrate 1
May be formed for each film substrate 1, but if the film substrate 1 is formed in a matrix on a large-sized aggregate substrate film in which many film substrates 1 are aggregated, the notch 6 is formed in each film substrate 1.
Can be efficiently formed by the four corners.

【0033】また、切欠部6の形状としては、図1に示
したような五角形に限らずいかなる形状であっても構わ
ない。
The shape of the notch 6 is not limited to a pentagon as shown in FIG. 1, but may be any shape.

【0034】(第2実施例)図3に第2実施例に係るB
GA型半導体装置Aの底面図を示す。なお、本実施例で
用いた符号は、同一構成要素については第1実施例と同
一のものを用いている。
(Second Embodiment) FIG. 3 shows a B according to a second embodiment.
The bottom view of GA type semiconductor device A is shown. The reference numerals used in this embodiment are the same as those in the first embodiment for the same components.

【0035】図示するように、本実施例では、切欠部6
をフィルム基板1の周縁部に複数個形成している。
As shown, in this embodiment, the notch 6
Are formed on the periphery of the film substrate 1.

【0036】また、切欠部6は熱硬化性樹脂5が最も剥
がれやすい四隅と、各辺に設けており、切欠部6の形状
は自由であるが、本実施例では、四隅部分には四分円形
状のものを、各辺には半円形状のものを形成している。
また、各辺に設けた切欠部6は、単数であっても複数で
あってもよく、本実施例では、一定間隔をあけた複数個
設けている。なお、他の構成については第1実施例と同
様なのでここでの説明は省略する。
The cutouts 6 are provided at the four corners where the thermosetting resin 5 is most likely to be peeled off and on each side, and the cutouts 6 can have any shape. A circular shape is formed, and a semi-circular shape is formed on each side.
The number of the cutouts 6 provided on each side may be singular or plural. In the present embodiment, a plurality of cutouts 6 are provided at regular intervals. The other configuration is the same as that of the first embodiment, and the description is omitted here.

【0037】以上の構成としたことから、本実施例で
は、第1実施例のパッケージ構造に比べて熱硬化性樹脂
5によるフィルム基板1のホールド力が大きくなり、密
着性がより増大して剥がれを確実に防止することができ
る。
With the above-described structure, in the present embodiment, the holding force of the film substrate 1 by the thermosetting resin 5 is larger than in the package structure of the first embodiment, and the adhesion is further increased and the film substrate 1 is peeled off. Can be reliably prevented.

【0038】[0038]

【発明の効果】本発明は上記のような形態で実施される
もので、以下の効果を奏する。
The present invention is embodied in the above-described embodiment, and has the following effects.

【0039】請求項1記載の本発明では、基板上面に
ICチップを固着してワイヤボンディングし、樹脂モー
ルドした樹脂封止型半導体装置において、基板の周側部
に、樹脂モールド時にモールド用樹脂を流入させる切欠
部を設けたことにより、切欠部に流入して硬化したモー
ルド用樹脂が基板を包み込むようにホールドした状態と
なり、モールド部の剥離を防止することができる。
According to the first aspect of the present invention, in a resin-sealed semiconductor device in which an IC chip is fixed to the upper surface of a substrate, wire-bonded, and resin-molded, a molding resin is applied to a peripheral portion of the substrate during resin molding. By providing the cut-out portion to be flown, the mold resin flowing into the cut-out portion and being hardened is held so as to enclose the substrate, and peeling of the mold portion can be prevented.

【0040】請求項2記載の本発明では、前記切欠部
を、基板上の導通パタンを避けた位置に設けたことによ
り、樹脂封止型半導体装置の機能を阻害することがな
い。
According to the second aspect of the present invention, the function of the resin-encapsulated semiconductor device is not hindered by providing the notch at a position avoiding the conductive pattern on the substrate.

【0041】請求項3記載の本発明では、前記切欠部
を、基板の周縁部に複数個設けたことにより、モールド
用樹脂による基板のホールド力を大きくして密着性がよ
り向上し、モールド部の剥離をより確実に防止すること
ができる。
According to the third aspect of the present invention, by providing a plurality of the notches in the peripheral portion of the substrate, the holding force of the substrate by the molding resin is increased, and the adhesion is further improved. Can be prevented more reliably.

【0042】請求項4記載の本発明では、前記切欠部
を、少なくとも基板の四隅に設けたことにより、少ない
個数で効率的に基板とモールド用樹脂との剥離を防止す
ることができる。
According to the fourth aspect of the present invention, since the notches are provided at least at the four corners of the substrate, the separation of the substrate and the molding resin can be efficiently prevented with a small number.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1実施例に係るBGA型半導体装置の底面図
である。
FIG. 1 is a bottom view of a BGA type semiconductor device according to a first embodiment.

【図2】図1のI−I線における断面図である。FIG. 2 is a cross-sectional view taken along line II of FIG.

【図3】第2実施例に係るBGA型半導体装置の底面図
である。
FIG. 3 is a bottom view of a BGA type semiconductor device according to a second embodiment.

【図4】従来のBGA型半導体装置のパッケージ構造を
示す説明図である。
FIG. 4 is an explanatory view showing a package structure of a conventional BGA type semiconductor device.

【符号の説明】[Explanation of symbols]

A BGA型半導体装置(樹脂封止型半導体装置) 1 フィルム基板(基板) 2 ICチップ 3 ボンディングワイヤ 4 半田バンプ 5 熱硬化性樹脂(モールド用樹脂) 6 切欠部 A BGA type semiconductor device (resin-sealed type semiconductor device) 1 film substrate (substrate) 2 IC chip 3 bonding wire 4 solder bump 5 thermosetting resin (resin for molding) 6 notch

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】基板上面にICチップを固着してワイヤボ
ンディングし、樹脂モールドした樹脂封止型半導体装置
において、 基板の周側部に、樹脂モールド時にモールド用樹脂を流
入させる切欠部を設けたことを特徴とする樹脂封止型半
導体装置。
1. A resin-encapsulated semiconductor device in which an IC chip is fixed to an upper surface of a substrate, wire-bonded, and resin-molded, a notch portion for allowing a molding resin to flow during resin molding is provided in a peripheral portion of the substrate. A resin-encapsulated semiconductor device, comprising:
【請求項2】切欠部を、基板上の導通パタンを避けた位
置に設けたことを特徴とする請求項1記載の樹脂封止型
半導体装置。
2. The resin-encapsulated semiconductor device according to claim 1, wherein the notch is provided at a position avoiding the conductive pattern on the substrate.
【請求項3】切欠部を、基板の周縁部に複数個設けたこ
とを特徴とする請求項1又は2に記載の樹脂封止型半導
体装置。
3. The resin-encapsulated semiconductor device according to claim 1, wherein a plurality of cutouts are provided in a peripheral portion of the substrate.
【請求項4】切欠部を、少なくとも基板の四隅に設けた
ことを特徴とする請求項1〜3のいずれかに記載の樹脂
封止型半導体装置。
4. The resin-sealed semiconductor device according to claim 1, wherein the notches are provided at least at four corners of the substrate.
JP23092298A 1998-08-17 1998-08-17 Resin-sealed semiconductor device Expired - Fee Related JP3732660B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23092298A JP3732660B2 (en) 1998-08-17 1998-08-17 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23092298A JP3732660B2 (en) 1998-08-17 1998-08-17 Resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JP2000058718A true JP2000058718A (en) 2000-02-25
JP3732660B2 JP3732660B2 (en) 2006-01-05

Family

ID=16915393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23092298A Expired - Fee Related JP3732660B2 (en) 1998-08-17 1998-08-17 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JP3732660B2 (en)

Also Published As

Publication number Publication date
JP3732660B2 (en) 2006-01-05

Similar Documents

Publication Publication Date Title
US8652879B2 (en) Lead frame ball grid array with traces under die
US20080111224A1 (en) Multi stack package and method of fabricating the same
US8163601B2 (en) Chip-exposed semiconductor device and its packaging method
US20060081978A1 (en) Heat dissipating package structure and method for fabricating the same
US6110755A (en) Method for manufacturing semiconductor device
US9196470B1 (en) Molded leadframe substrate semiconductor package
JP2007088453A (en) Method of manufacturing stack die package
US20070122943A1 (en) Method of making semiconductor package having exposed heat spreader
US6825064B2 (en) Multi-chip semiconductor package and fabrication method thereof
US8461694B1 (en) Lead frame ball grid array with traces under die having interlocking features
US8460970B1 (en) Lead frame ball grid array with traces under die having interlocking features
US6650005B2 (en) Micro BGA package
US6339253B1 (en) Semiconductor package
US7605018B2 (en) Method for forming a die-attach layer during semiconductor packaging processes
KR100871379B1 (en) Method of manufacturing semiconductor package
JP2000058718A (en) Resin sealed semiconductor device
JP2000114427A (en) Semiconductor device and its manufacture
KR100401497B1 (en) Stack type Multi Chip Package and Manufacture Method the same
JPH07249707A (en) Semiconductor package
KR100308393B1 (en) Semiconductor Package and Manufacturing Method
US8399967B2 (en) Package structure
JPH10270603A (en) Semiconductor device and manufacture thereof
JPH11204577A (en) Manufacture of semiconductor device
KR100600366B1 (en) Semiconductor and method for manufacturing the same
JP2001144036A (en) Ic chip package method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20041116

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050426

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050510

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050711

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050913

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20051013

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111021

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111021

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121021

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees