JP2000058639A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device the operating speed of which does not deteriorate and which does no cause malfunctions by reducing the connection resistance between a lower wiring layer and an upper wiring layer, as compared with the conventional technology by adjusting the amount of carbon contained in a metal nitride film deposited on the bottoms of recessed sections, such as through-holes, etc. SOLUTION: A method for manufacturing semiconductor devices includes a process of forming a lower wiring layer 102 on a substrate 101, a process of depositing insulating films 103, 104, and 105 covering the wiring layer 102 on the substrate 101, a process of forming recessed sections 106 and 107 at least partially reaching the wiring layer 102 in the insulating films 103, 104, and 105, and a process of forming an upper wiring layer 112 in the recessed sections 106 and 107 of the insulating films 103, 104, and 105. The process of forming the upper wiring layer 112 includes a step of depositing a carbon- containing TaN layer 109 on the internal side faces and bottoms of the recessed sections 106 and 107, a step of irradiating the partial surface 109b of the TaN film 9 on the bottoms of the recessed sections 106 and 107 with ions, and a step of depositing copper films 110 and 111 on the TaN film 109.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the increase in the degree of integration of semiconductor devices, the distance between adjacent wiring layers has been reduced, and the increase in capacitance between wiring layers cannot be ignored. When the capacitance between wiring layers increases, the operation speed of the semiconductor device decreases due to wiring delay. In order to prevent this, a technique of forming a low-resistance wiring layer using copper (Cu) has been actively studied in recent years.

Hereinafter, referring to FIGS. 15 to 19,
A conventional technique of a semiconductor device in which a wiring layer is formed using Cu will be described.

[0004] As shown in FIG.
The semiconductor device includes a semiconductor substrate 1, a lower wiring layer 2 formed on the surface of the semiconductor substrate 1, and a silicon dioxide (SiO ₂ ) film 3 deposited on the semiconductor substrate 1 so as to cover the lower wiring layer 2. Tri-silicon tetranitride (Si ₃ N ₄ ) on the SiO ₂ film 3
A film 4 is deposited, and an SiO ₂ film 5 is deposited on the Si ₃ N ₄ film 4. An interlayer insulating film is formed by the SiO ₂ film 3, the Si ₃ N ₄ film 4, and the SiO ₂ film 5.
In this interlayer insulating film, a through hole 6 reaching the lower wiring layer 2 and a groove-shaped concave portion (wiring groove) connected to the through hole 6 are formed.
7 are formed, and a through hole 6 is formed in the wiring groove 7.
Upper wiring layer 12 electrically contacting the lower wiring layer through
Is provided.

[0005] The upper wiring layer 12 is formed of a titanium (Ti) film 8 covering the inner side wall and the bottom surface of the through hole 6 and the wiring groove 7.
And a tantalum nitride (TaN) film 9 deposited on the Ti film 8, a Cu film 10 deposited on the TaN film 9, and a Cu film 11 deposited on the Cu film 10.

A method for manufacturing such a semiconductor device is as follows.

First, as shown in FIG.
Is formed on the surface of the lower wiring layer 2. Next, as shown in FIG. 16, the SiO2 film 3, the Si3N4 film 4, the SiO2 film 5
Are sequentially deposited, and then the lithography method and the dry etching method are alternately applied twice, so that S
A through hole 6 is formed inside the iO2 film 3 and the Si3N4 film 4, and a wiring groove 7 is formed inside the SiO2 film 5. Next, as shown in FIG. 17, after cleaning the bottom of the through hole 6 by dry etching, a Ti film 8 is formed by a physical vapor deposition method, and then a TaN film is formed by a chemical vapor deposition method. 9 is deposited. Next, as shown in FIG. 18, a Cu film 10 is deposited on the surface of the TaN film 9 by a physical vapor deposition method. Next, sulfuric acid (H2
After cleaning with SO4), the Cu film 1 is formed by electrolytic plating.
A Cu film 11 is deposited on the surface of the “0”. Finally, the Ti film 8, TaN film 9, Cu film 10, and Cu film on the SiO2 film 5
By removing the film 11 by a chemical mechanical polishing method,
A semiconductor device as shown in FIG. 19 is created.

[0008]

When a semiconductor device is manufactured by the above method, the following problems occur.

First, since the specific resistance of the TaN film 9 deposited by the chemical vapor deposition method is high, the connection resistance between the lower wiring layer 2 and the upper wiring layer 12 increases. This causes a reduction in the operation speed of the semiconductor device. It is considered that the high specific resistance of the TaN film 9 results from the fact that the TaN film 9 contains a large amount of carbon (C).

The TaN film 9 is made of Cu film 10 and Cu film.
Since the ability to prevent the diffusion of Cu atoms contained in the film 11 is not sufficient, Cu atoms are converted to SiO2 through the TaN film 9.
The point is that it reaches the film 3 and the SiO 2 film 5. S
Cu atoms reaching the iO 2 film 3 and the SiO 2 film 5
Mobile ions are formed inside the SiO 2 film 3 and the SiO 2 film 5 to increase leakage current between the through holes 6 and between the upper wiring layers 12. This causes a malfunction of the semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device which does not cause a reduction in operation speed or malfunction, and a method for manufacturing the same.

[0012]

A semiconductor device according to the present invention comprises a substrate, a first conductive film supported by the substrate, and an insulating film formed on the substrate so as to cover the first conductive film. A semiconductor device comprising: a film; a concave portion formed in the insulating film; and a second conductive film formed in the concave portion of the insulating film and in electrical contact with the first conductive film. The second conductor film includes a carbon-containing metal nitride film formed inside a concave portion of the insulating film, and a metal film formed on the carbon-containing metal nitride film. A portion of the film formed on the bottom surface of the recess of the insulating film has a lower carbon concentration than a portion of the metal nitride film formed on the inner side wall of the recess of the insulating film.

The thickness of a portion of the metal nitride film formed on the bottom surface of the concave portion of the insulating film is equal to the thickness of a portion of the metal nitride film formed on the inner wall of the concave portion of the insulating film. It is preferably smaller than the thickness.

The specific resistance of a portion of the metal nitride film formed on the bottom surface of the concave portion of the insulating film is different from that of a portion of the metal nitride film formed on the inner wall of the concave portion of the insulating film. It is preferably smaller than the specific resistance.

Preferably, the metal nitride film is a tantalum nitride film.

[0016] The metal nitride film may be a tungsten nitride film.

[0017] The metal nitride film may be a molybdenum nitride film.

It is preferable that the metal film is made of copper.

[0019] The concave portion of the insulating film may have a through hole reaching the first conductive film, and a wiring groove connected to the through hole.

Another semiconductor device according to the present invention comprises a substrate,
A first conductive film supported by the substrate, an insulating film formed on the substrate so as to cover the first conductive film, a recess formed in the insulating film, and a recess formed in the insulating film. And a second conductor film electrically connected to the first conductor film, wherein the second conductor film is formed inside a concave portion of the insulating film. A metal nitride film; a metal silicide nitride film formed on the metal nitride film; and a metal film deposited on the metal silicide nitride.

The thickness of a portion of the metal silicide nitride film formed on the bottom surface of the concave portion of the insulating film is formed on the inner wall of the concave portion of the insulating film of the metal silicide nitride film. It is preferable that the thickness is smaller than the thickness of the portion.

Preferably, the metal silicide nitride film is a tantalum silicide nitride film.

The metal silicide nitride film may be a tungsten silicide nitride film.

The metal silicide nitride film may be a molybdenum silicide nitride film.

[0025] The concave portion of the insulating film may have a through hole reaching the first conductive film, and a wiring groove connected to the through hole.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a first conductor film on a substrate, a step of depositing an insulating film covering the first conductor film on the substrate, Forming a concave portion reaching the first conductive film in the insulating film, and forming a second conductive film inside the concave portion of the insulating film, The step of forming the second conductor film includes the steps of: depositing a carbon-containing metal nitride film covering inner walls and a bottom surface of a concave portion of the insulating film by a chemical vapor deposition method; Irradiating the surface of the carbon-containing metal nitride film with ions, comprising: exposing the surface of the carbon-containing metal nitride film to a plasma; and exposing the surface of the carbon-containing metal nitride film to a plasma. May be included.

[0027] The step of forming the concave portion in the insulating film may include a step of forming a through hole in the insulating film and a step of forming a wiring-like groove connected to the through hole.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a first conductive film on a substrate,
Depositing an insulating film covering the conductor film on the substrate;
A method of manufacturing a semiconductor device, comprising: a step of forming a recess in the insulating film at least partially reaching the first conductor film; and a step of forming a second conductor film inside the recess of the insulating film. The step of forming the second conductor film includes:
Depositing a metal nitride film covering the inner wall and the bottom surface of the concave portion of the insulating film by a chemical vapor deposition method, irradiating ions to the surface of the metal nitride film, Forming a metal silicide nitride film by exposing the surface to a silicon compound; and depositing a metal layer on the surface of the metal silicide nitride film.

[0029] The step of irradiating the ions may include a step of exposing the surface of the metal nitride film to plasma.

[0030] The step of forming the concave portion in the insulating film may include a step of forming a through hole in the insulating film and a step of forming a wiring groove connected to the through hole.

In the step of depositing the metal nitride film, any of a tantalum amide complex and a tantalum imide complex may be used as a material.

In the step of depositing the metal nitride film, any of a tungsten amide complex and a tungsten imide complex may be used as a material.

In the step of depositing the metal nitride film, any of a molybdenum amide complex and a molybdenum imide complex may be used as a material.

In the step of exposing the metal nitride film to plasma, any one of nitrogen, ammonia and hydrazine may be used.

In the step of forming the metal silicide nitride film, any one of silane, disilane, and trisilane may be used as a silicon compound.

A semiconductor device manufacturing apparatus according to the present invention includes a vacuum chamber, a susceptor installed inside the vacuum chamber, a heating mechanism installed inside the susceptor, and an interior installed inside the vacuum chamber. An exhaust port, an inlet installed inside the vacuum chamber, an electrode installed inside the vacuum chamber, a power supply connected to the susceptor and the electrode, and an organometallic compound from the inlet. , Nitrogen compounds, and silicon compounds can be introduced.

It is preferable that either an amide complex of tantalum or an imide complex of tantalum can be used as the organometallic compound.

It is preferable that either an amide complex of tungsten or an imide complex of tungsten can be used as the organometallic compound.

It is preferable that either an amide complex of molybdenum or an imide complex of molybdenum can be used as the organometallic compound.

As the nitrogen compound, nitrogen, ammonia,
Preferably, either hydrazine or hydrazine can be used.

It is preferable that any one of silane, disilane and trisilane can be used as the silicon compound.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device according to the present invention will be described with reference to FIGS. As shown in FIG. 6, the semiconductor device of this embodiment includes a semiconductor substrate 1 on which an integrated circuit element such as a transistor (not shown) is formed.
01, a lower wiring layer 102 formed on the surface of the semiconductor substrate 101, and a silicon dioxide (SiO ₂ ) film 103 deposited on the semiconductor substrate 101 so as to cover the lower wiring layer (first conductive film) 102. It has. In the present specification, the “semiconductor substrate 101” refers to a single crystal silicon substrate, an integrated circuit element such as a transistor formed on the surface thereof, an insulating film formed on the surface of the single crystal silicon substrate so as to cover the integrated circuit element, or the like. Are expressed in a lump. The lower wiring layer 102 is formed using a conductive material such as tungsten (W), aluminum (Al), and copper (Cu).

[0043] A four nitriding three silicon on the SiO ₂ film 103 (Si ₃ N ₄₎ film 104 is deposited, Si ₃ N ₄ film 1
_{On the} substrate 04, an SiO ₂ film 5 is deposited. SiO ₂ film 1
03, an interlayer insulating film is formed by the Si ₃ N ₄ film 104 and the SiO ₂ film 105. In this interlayer insulating film,
A recess is formed. This recess is formed in the lower wiring layer 102.
, And a groove-like concave portion (wiring groove) 107 connected to the through hole 106. The wiring groove 107 is in electrical contact with the lower wiring layer 102 via the through hole 106. An upper wiring layer 112 is provided. The groove width of the wiring groove 107 is, for example, about 10
0 to 2000 nm, and the depth is, for example, about 100 to 10 nm.
00 nm. In the present embodiment, the inner diameter of the through hole 106 is set equal to the groove width of the wiring groove 107. The plurality of through holes 106 are, for example, 0.1 to 2
It is formed in each wiring groove 107 at intervals of about μm.

The upper wiring layer 112 is formed in the through hole 106.
And a titanium (Ti) film 108 to cover the inner side wall and the bottom surface of the wiring groove 107, a tantalum nitride (TaN) film 109 deposited on the surface of the Ti film 108, and a TaN film 109.
It includes a Cu film 110 formed thereon and a Cu film 111 deposited on the Cu film 110.

The TiN film 109 has a vertical portion (a portion formed on a surface substantially perpendicular to the semiconductor substrate 101) 109 a formed on the inner side wall of the through hole 106 and the wiring groove 107, Wiring groove 10
And a horizontal portion (portion formed on a plane substantially parallel to the semiconductor substrate 101) 109b formed on the bottom surface of the semiconductor device 101 as necessary. Horizontal portion 109 of TiN film 109
The concentration of C in b is lower than the concentration of C in the vertical portion 109a.

Note that the lower wiring layer is not limited to the first-level wiring, and may be at the i-th level (i is an integer of 1 ≦ i <N) of the N-level wiring (N is an integer of 3 or more). I just want it. At this time, the upper wiring is at the j-th layer level (j is i <j ≦
(An integer of N).

With the above configuration, the lower wiring layer 10
The connection resistance between the second wiring layer 112 and the upper wiring layer 112 can be reduced as compared with the related art. The reason is as follows.

The connection resistance between the lower wiring layer 102 and the upper wiring layer 112 is actually determined by the specific resistance of the TaN film deposited on the bottom of the through hole 106. In the present embodiment, the horizontal portion 109b of the TaN film exists at the bottom of the through hole 106, the vertical portion 109a of the TaN film 109 exists on the side wall of the through hole 106, and the concentration of C contained in the horizontal portion 109b. Is lower than the concentration of C contained in the vertical portion 109a. The lower the concentration of C contained in the film, the lower the specific resistance of the TaN film. Therefore, by decreasing the amount of C contained in the TaN film 109b, the lower wiring layer 102 and the upper wiring layer 112 are reduced.
And the connection resistance between them can be made lower than in the prior art.

The method of manufacturing the semiconductor device according to the present embodiment is as follows.

First, as shown in FIG.
The lower wiring layer 102 is formed on the surface of the substrate 1. Lower wiring layer 1
02 is formed by depositing an Al film on the surface of the semiconductor substrate 101 by a sputtering method, and then processing the Al film into a predetermined shape by a lithography method and a dry etching method.

Next, as shown in FIG. 2, an SiO 2 film (thickness: about 10
0 to 2000 nm) 103, Si3N4 film (film thickness: about 5
), SiO2 film (film thickness: about 100-1)
000 nm) 105 are sequentially deposited, and a lithography method and a dry etching method are alternately applied twice each so that a through hole 106 is formed inside the SiO 2 film 103 and the Si 3 N 4 film 104 to form the SiO 2 film 10.
5, a wiring groove 107 is formed.

Next, as shown in FIG.
r), the bottom of the through hole 106 is cleaned by a dry etching method using hydrogen (H2) or the like, and then a Ti film (thickness: about 0.5 to
10 nm) 108, and then a TaN film 109 having a thickness of 20 nm is deposited by a chemical vapor deposition method. The TaN film 109 is deposited by the chemical vapor deposition method as follows. The semiconductor substrate 101 on which the Ti film 108 has been deposited is heated to 400 ° C. in a vacuum chamber. Semiconductor substrate 10
When 1 reaches the steady-state temperature, pentakisdimethylamide tantalum (Ta (NMe2) 5) is placed inside the vacuum chamber.
Is introduced together with ammonia (NH3). The introduced Ta (NMe2) 5 and NH3 react on the surface of the Ti film 108, and a TaN film 109 is deposited.

Next, as shown in FIG.
Is exposed to a plasma generated in ammonia (NH3). The plasma contains cations such as NH 2 ions. The plasma generation conditions are adjusted such that these cations are accelerated in the vertical direction toward the semiconductor substrate 101. Thus, the TaN film 109b deposited on a plane parallel to the semiconductor substrate 101
Is densified due to the impact of cations, and accordingly, C contained in the TaN film 109b is desorbed into the gas phase. On the other hand, the vertical portion 109a of the TaN film 109 deposited on a plane perpendicular to the semiconductor substrate 101 is not densified because it is not impacted by cations. as a result,
The TaN film 109b is thinner than the TaN film 109a,
The carbon concentration of the TaN film 109b is
Lower than the carbon concentration. The plasma exposure uses, for example, a parallel plate type plasma generation device or the like, and the pressure of NH 3 gas is set to about 10 to 1000 Pa in the chamber.
Plasma generated by applying power of 200 to 2000 W can be used.

Next, as shown in FIG.
A Cu film 110 is deposited on the surface of the substrate by a physical layer growth method. After cleaning the surface of the Cu film 110 with sulfuric acid (H 2 SO 4), the surface of the Cu film
A film 111 is deposited.

Finally, the Ti film 10 on the SiO 2 film 105
8. By removing the TaN film 109, the Cu film 110, and the Cu film 111 by a chemical mechanical polishing method, a semiconductor device as shown in FIG. 6 is manufactured.

(Embodiment 2) Another embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 7 to 13, the same components as those shown in FIGS. 1 to 6 are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIG. 13, the semiconductor device of this embodiment includes a semiconductor substrate 101 on which an integrated circuit element such as a transistor (not shown) is formed, and a lower wiring layer 102 formed on the surface of the semiconductor substrate 101. And a silicon dioxide (SiO ₂ ) film 103 deposited on the semiconductor substrate 101 so as to cover the lower wiring layer 102. Lower wiring layer 1
02 is tungsten (W), aluminum (Al),
It is formed using a conductive material such as copper (Cu).

[0058] A four nitriding three silicon on the SiO ₂ film 103 (Si ₃ N ₄₎ film 104 is deposited, Si ₃ N ₄ film 1
_{On the} substrate 04, an SiO ₂ film 5 is deposited. SiO ₂ film 1
03, an interlayer insulating film is formed by the Si ₃ N ₄ film 104 and the SiO ₂ film 105. In this interlayer insulating film,
A through-hole 106 reaching the lower wiring layer 102 and a groove-like concave portion (wiring groove) 107 connected to the through-hole 106 are formed.
An upper wiring layer 112 that is in electrical contact with the lower wiring layer 102 via the reference numeral 06 is provided. The upper wiring layer 112
A titanium (Ti) film 108 and a Ti film 10 so as to cover the inner side wall and the bottom surface of the through hole 106 and the wiring groove 107;
8, a tantalum nitride (TaN) film 109 deposited on the surface
And a tantalum silicide nitride (TaSiN) film 113 formed on the TaN film 109, a Cu film 110 formed on the TaSiN film 113, and a Cu film 111 deposited on the Cu film 110. .

The TaN film 109 includes a vertical portion (a portion formed on a surface substantially perpendicular to the semiconductor substrate 101) 109 a formed on the inner side wall of the through hole 106 and the wiring groove 107, Wiring groove 10
And a horizontal portion (portion formed on a plane substantially parallel to the semiconductor substrate 101) 109b formed on the bottom surface of the semiconductor device 101 as necessary. Similarly, the TaSiN film 113 is
A vertical portion (a portion formed on a surface substantially perpendicular to the semiconductor substrate 101) 113a formed on the inner wall of the through hole 106 and the wiring groove 107;
6 and a horizontal part (part formed on a plane substantially parallel to the semiconductor substrate 101) 113b formed on the bottom surface of the wiring groove 107, if necessary.

The configuration of the semiconductor device in this embodiment is
The difference from the structure of the first embodiment is that the TaSiN film 113 is formed on the surface of the TaN film 109 as shown in FIG.
Is formed. TaSiN film is TaN
Since the ability to prevent the diffusion of Cu atoms is higher than that of the film, the configuration according to the present embodiment reduces the leakage current between the through holes 106 and between the upper wiring layers 112 according to the first embodiment. Can be reduced.

Here, the thickness of the TaSiN film 113b will be described. The resistivity of the TaSiN film 113b is NH
3 is higher than the resistivity of the TaN film 109b after exposure to the plasma. Therefore, if the thickness of the TaSiN film 113b is too large, the lower wiring layer 102 and the upper wiring layer 112
, The connection resistance increases, and the operating speed of the semiconductor device decreases. For the above reasons, it is desirable that the thickness of the TaSiN film 113b be smaller than the thickness of the TaSiN film 113a.

The method of manufacturing the semiconductor device according to the present embodiment is as follows.

First, as shown in FIG.
The lower wiring layer 102 is formed on the surface of the substrate 1. Next, as shown in FIG. 8, the SiO2 film (thickness: about 100 to 2000 n)
m) 103, Si3N4 film (thickness: about 5 to 50 nm) 1
04 and a SiO2 film (thickness: about 100 to 1000 n)
m) After depositing 105 in order, a lithography method and a dry etching method are alternately applied twice each so that a through hole 106 is formed inside the SiO2 film 103 and the Si3N4 film 104, and a wiring groove 107 is formed inside the SiO2 film 105. To form Next, as shown in FIG.
After cleaning the bottom of the through hole 106 by dry etching, a Ti film 108 is formed by physical vapor deposition, and a TaN film (thickness: about 1 to 50 nm) 109 is subsequently formed by chemical vapor deposition. Is deposited. Next, FIG.
As shown in FIG. 7, the surface of the TaN film 109 is exposed to NH3 plasma. As a result, the TaN film 109b deposited on a plane parallel to the semiconductor substrate 101 is densified to receive the impact of cations.
C contained in 09b is desorbed into the gas phase. On the other hand, a TaN film 1 deposited on a plane perpendicular to the semiconductor substrate 101
The 09 vertical portion 109a is not densified because it is not impacted by cations. As a result, the TaN film 109b becomes thinner than the TaN film 109a.
The carbon concentration of 9b is lower than the carbon concentration of the TaN film 109a.

Next, as shown in FIG.
The surface of No. 9 is exposed to disilane (Si2H8). This processing is performed on the semiconductor substrate 1 that has been exposed to the NH3 plasma.
01 is heated to 400 ° C. in a vacuum chamber, and Si 2 H 6 is introduced into the vacuum chamber. Thereby, the TaSiN film 1 is formed on the surface of the TaN film 109a.
13a is a TaSiN film 1 on the surface of the TaN film 109b.
13b is formed, but the thickness of the TaSiN film 113b is smaller than the thickness of the TaSiN film 113a. This is because the TaN film 109b is densified by exposure to NH ₃ plasma, and thus the Si2H6 is
This is due to the fact that it is difficult to diffuse into the inside.

Next, as shown in FIG. 12, a Cu film (film thickness:
(About 5 to 200 nm) 110 is deposited. After depositing the Cu film 110, the surface of the Cu film 110 is washed with H2SO4, and then the Cu film (film thickness: about 100
(~ 1000 nm) 111 is deposited. Finally, SiO2
Ti film 108, TaN film 109, Cu film 1 on film 105
By removing 10 and Cu film 111 by a chemical mechanical polishing method, a semiconductor device as shown in FIG. 13 is realized.

The semiconductor device of this embodiment can be manufactured using a manufacturing apparatus as shown in FIG. The apparatus includes a vacuum chamber 114 and a vacuum chamber 114.
Susceptor 115 installed inside the susceptor 115
, A heating mechanism 116 such as a heater installed inside the vacuum chamber 114, an exhaust port 117 installed in the vacuum chamber 114, and a Ta (NMe 2) 5 inlet 11 installed in the vacuum chamber 114.
8 and the NH3 inlet 1 installed in the vacuum chamber 114
19, a Si2H6 inlet 120 installed in the vacuum chamber 114, an upper electrode 121 installed inside the vacuum chamber 114 so as to face the susceptor 115, and a high-frequency power supply 122 connected to the sceptor 115 and the upper electrode 121. It has.

The operation of the semiconductor device manufacturing apparatus is as follows. First, the inside of the vacuum chamber 114 is opened to the atmosphere, the semiconductor substrate 101 on which the Ti film 108 has been deposited is set on the susceptor 115, and then the inside of the vacuum chamber 114 is exhausted through the exhaust port 117. When the evacuation is completed, the heating mechanism 116 is operated to heat the semiconductor substrate 101 through the susceptor 115. Semiconductor substrate 101
Heating mechanism 1 such that the steady temperature of
Adjust the 16 outputs. When the temperature of the semiconductor substrate 101 reaches the steady temperature, Ta (NMe2) 5 is introduced from the Ta (NMe2) 5 inlet 118 and NH3 is introduced from the NH3 inlet 119.
3 is introduced. As a result, Ta (NMe2) 5 and NH3
Reacts on the surface of the Ti film 108, and a TaN film 109 is deposited. After a predetermined time has elapsed, Ta (NMe2) 5
Stop introducing. When the partial pressure of Ta (NMe 2) 5 remaining in the vacuum chamber 114 becomes sufficiently small, high frequency power is supplied to the susceptor 115 and the upper electrode 121 by the high frequency power supply 122, and NH 3 plasma is generated inside the vacuum chamber 114. Generate. Thus, the TaN film 109 deposited on a plane parallel to the semiconductor substrate 101
a is densified to receive cation bombardment. When a predetermined time has elapsed, the high-frequency power supply 122 is stopped,
Stop the introduction of NH3. Next, the Si2H6 inlet 12
From 0, Si2H6 is introduced. Thereby, the TaN film 10 is formed.
9, a TaSiN film 113 is formed. Finally,
The operation of the heating mechanism 116 is stopped, and the vacuum chamber 114 is stopped.
Is released to the atmosphere, and then the semiconductor substrate 101 is discharged.

Although the present invention has been described with respect to two embodiments, the present invention is not limited to these embodiments. For example, in the above-described embodiment, the “dual damascene method” in which the through hole 106 and the wiring groove 107 are continuously formed and then the inside thereof is filled with a metal material such as the Cu film 111 is applied. A “single damascene method” in which either the wiring 106 or the wiring groove 107 is formed and then the inside thereof is filled with a metal material such as the Cu film 111 can be applied instead. In the above-described embodiment, SiO2 and Si3N4 are used as materials for insulating between wiring layers, but other materials can be used instead of these. Examples of such a material include SiO2 containing impurities such as fluorine (F) and an organic compound having an insulating property. Further, in the above embodiment, S
Although the Ti film 108 is deposited on the surface of the iO2 film 105 and inside the through hole 106, the deposition of the Ti film 108 becomes unnecessary depending on the type of conductive material forming the lower wiring layer 102. Further, in the above-described embodiment, tantalum nitride is used as a metal for preventing diffusion of Cu atoms, but any metal nitride can be used instead. Examples of such metal nitrides include tungsten nitride (WN) and molybdenum nitride (MoN). WN can be synthesized by using a tungsten amino complex or imide complex instead of Ta (NMe2) 5 as a raw material. An example of such a complex is bis (tertiary butyl imide) bis (tertiary butyl amide) tungsten. WN can be synthesized by using a molybdenum amino complex or imide complex instead of Ta (NMe2) 5 as a raw material. An example of such a complex is bis (dimethylamido) bis (tert-butylimido) molybdenum. In the above embodiment, the TaN film 10
9 was exposed to plasma generated in NH3,
If it is a nitrogen compound, it can be used instead. Examples of such gases include nitrogen (N2) and hydrazine (N2H4). Further, in the above-described embodiment, Si2H6 is used for forming the TaSiN film 113, but a silicon compound can be used instead. Examples of such compounds include silane (S
iH4) and trisilane (Si3H8). In the above-described embodiment, the physical vapor deposition method is used for depositing the Cu film 110. However, the Cu film 110 can be deposited by, for example, a chemical vapor deposition method. Further, in the above-described embodiment, the electrolytic plating method is used for depositing the Cu film 111, but any other depositing method that can fill the through hole 106 and the wiring groove 107 can be used. An example of such a deposition method is an electroless plating method.

Further, as a method of applying ion bombardment to the thin film, plasma irradiation is performed on the thin film, but another method, for example, an ion implantation method may be used.

[0070]

According to the semiconductor device of the present invention, the concentration of carbon contained in the metal nitride film deposited on the bottom of the recess is lower than the concentration of carbon contained in the metal nitride film deposited on the sidewall of the recess of the insulating film. Concentration is lower. The lower the concentration of carbon contained, the lower the specific resistance of the metal nitride,
By adjusting the amount of carbon contained in the metal nitride film deposited at the bottom of the recess such as a through hole, the connection resistance between the lower wiring layer and the upper wiring layer can be reduced as compared with the conventional technology. it can.

According to another semiconductor device of the present invention, the side wall of the through hole and the side wall of the upper wiring layer are covered with the metal silicide nitride film. Since the metal silicide nitride film has a higher ability to prevent the diffusion of copper atoms than the metal nitride, the above structure reduces the concentration of copper atoms contained in the insulating film. Can be.
For this reason, the leak current between the through holes and between the upper wiring layer (second conductive film) can be reduced as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a process sectional view for describing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a process cross-sectional view for explaining a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a process sectional view for describing the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a process sectional view for describing the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a process sectional view for describing the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a sectional view of the first embodiment of the semiconductor device according to the present invention;

FIG. 7 is a process sectional view for describing the second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a process sectional view for explaining the second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a process sectional view for describing the second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 10 is a process sectional view for describing the second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 11 is a process cross-sectional view for explaining the second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 12 is a process sectional view for describing the second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 13 is a cross-sectional view for explaining a second embodiment of the semiconductor device according to the present invention.

FIG. 14 is a cross-sectional view of an example of an apparatus for manufacturing a semiconductor device used in the present invention.

FIG. 15 is a process sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 16 is a process sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 17 is a process cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 18 is a process sectional view illustrating the method for manufacturing the conventional semiconductor device.

FIG. 19 is a cross-sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Lower wiring layer 3 Silicon dioxide film 4 Trisilicon tetranitride film 5 Silicon dioxide film 6 Through hole 7 Wiring groove 8 Titanium film 9 Tantalum nitride film 10 Copper film 11 Copper film 12 Upper wiring layer 101 Semiconductor substrate 102 Lower wiring Layer 103 Silicon dioxide film 104 Trisilicon tetranitride film 105 Silicon dioxide film 106 Through hole 107 Wiring groove 108 Titanium film 109 Tantalum nitride film 109a Tantalum nitride film 109b Tantalum nitride film 110 Copper film 111 Copper film 112 Upper wiring layer 113 Silicide nitride Tantalum film 113a Tantalum silicide nitride film 113b Tantalum silicide nitride film 114 Vacuum chamber 115 Susceptor 116 Heating mechanism 117 Exhaust port 118 Pentakisdimethylamidantalum tantalum inlet 119 Ammonia inlet 120 Disilane inlet 1 1 upper electrode 122 high frequency power source

Claims (20)

[Claims] A substrate, a first conductive film supported by the substrate, an insulating film formed on the substrate so as to cover the first conductive film, and a recess formed in the insulating film. And a second conductor film formed in a concave portion of the insulating film and electrically contacting the first conductor film, wherein the second conductor film is A carbon-containing metal nitride film formed inside a concave portion of the film; and a metal film formed on the carbon-containing metal nitride film, wherein a bottom surface of the concave portion of the insulating film in the metal nitride film A semiconductor device, wherein a carbon concentration of a portion formed thereon is lower than a carbon concentration of a portion of the metal nitride film formed on an inner side wall of a concave portion of the insulating film. 2. A thickness of a portion of the metal nitride film formed on a bottom surface of the concave portion of the insulating film is formed on an inner wall of the concave portion of the insulating film of the metal nitride film. The semiconductor device according to claim 1, wherein the thickness is smaller than a thickness of the portion. 3. The specific resistance of a portion of the metal nitride film formed on the bottom surface of the concave portion of the insulating film is formed on the inner wall of the concave portion of the insulating film of the metal nitride film. The semiconductor device according to claim 1, wherein the specific resistance is smaller than a specific resistance of the portion. 4. The semiconductor device according to claim 1, wherein said metal nitride film is a tantalum nitride film. 5. The semiconductor device according to claim 1, wherein said metal nitride film is a tungsten nitride film. 6. The semiconductor device according to claim 1, wherein said metal nitride film is a molybdenum nitride film. 7. The metal film according to claim 1, wherein said metal film is copper.
The semiconductor device according to any one of the above. 8. The semiconductor device according to claim 1, wherein the concave portion of the insulating film has a through hole reaching the first conductive film, and a wiring groove connected to the through hole. 9. A substrate, a first conductive film supported by the substrate, an insulating film formed on the substrate so as to cover the first conductive film, and a concave portion formed in the insulating film And a second conductor film formed in a concave portion of the insulating film and electrically contacting the first conductor film, wherein the second conductor film is Semiconductor having a metal nitride film formed inside a concave portion of a film, a metal silicide nitride film formed on the metal nitride film, and a metal film deposited on the metal silicide nitride apparatus. 10. A thickness of a portion of the metal silicide nitride film formed on a bottom surface of the concave portion of the insulating film is equal to a thickness of the metal silicide nitride film on an inner side wall of the concave portion of the insulating film. The semiconductor device according to claim 9, wherein the thickness is smaller than a thickness of a portion formed in the semiconductor device. 11. The semiconductor device according to claim 9, wherein said metal silicide nitride film is a tantalum silicide nitride film. 12. The semiconductor device according to claim 9, wherein said metal silicide nitride film is a tungsten silicide nitride film. 13. The semiconductor device according to claim 9, wherein said metal silicide nitride film is a molybdenum silicide nitride film. 14. The semiconductor device according to claim 9, wherein the concave portion of the insulating film has a through hole reaching the first conductive film, and a wiring groove connected to the through hole. 15. A step of forming a first conductor film on a substrate, a step of depositing an insulating film covering the first conductor film on the substrate, at least a part of the first conductor film is formed on the first conductor film. A method for manufacturing a semiconductor device, comprising: forming a concave portion reaching the insulating film; and forming a second conductive film inside the concave portion of the insulating film, wherein the second conductive film is Forming a carbon-containing metal nitride film covering an inner wall and a bottom surface of the concave portion of the insulating film by a chemical vapor deposition method; and irradiating ions to a surface of the carbon-containing metal nitride film. And a step of depositing a metal layer on the surface of the carbon-containing metal nitride film. 16. The method according to claim 15, wherein the step of irradiating the ions includes exposing a surface of the carbon-containing metal nitride film to plasma. 17. The step of forming a concave portion in the insulating film,
17. The method according to claim 15, further comprising: forming a through hole in the insulating film; and forming a wiring groove connected to the through hole. 18. A step of forming a first conductor film on a substrate, a step of depositing an insulating film covering the first conductor film on the substrate, at least a part of the first conductor film is formed on the first conductor film. A method for manufacturing a semiconductor device, comprising: forming a concave portion reaching the insulating film; and forming a second conductive film inside the concave portion of the insulating film, wherein the second conductive film is Forming a metal nitride film covering an inner wall and a bottom surface of the concave portion of the insulating film by a chemical vapor deposition method; irradiating ions to a surface of the metal nitride film; A method for manufacturing a semiconductor device, comprising: forming a metal silicide nitride film by exposing the surface of a metal nitride film to a silicon compound; and depositing a metal layer on the surface of the metal silicide nitride film. . 19. The method according to claim 13, wherein the step of irradiating the ions includes exposing a surface of the metal nitride film to plasma. 20. The step of forming a recess in the insulating film,
The method of manufacturing a semiconductor device according to claim 18, further comprising: forming a through hole in the insulating film; and forming a wiring-shaped groove connected to the through hole.