JP2000058606A - Standard sample for inspection - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the yield of products by quantifying the depth and width of a scratch by the standard sample for a false machined trace, calibrating the detection of the scratch by the scattered-light detector of semiconductor inspection and feeding back the calibrated detection to a semiconductor-device manufacturing process. SOLUTION: A plurality of blocks of collective patterns 65 consisting of a plurality of rows of pits 70-119, in which width and depth in various size are combined on a substrate surface, are worded and arrayed. The longitudinal direction of the pits 70-119 of the collective pattern 65 is set in length of the size or more of irradiation beams, the collective pattern 65 is extended from a wafer center of the outer circumference, and a plurality of blocks of the collective patterns 65 are arranged at radiant arbitrary radial places at arbitrary angles. Regular pitches are formed among the pits 70-119, and square-shaped pits 70, 72... composed of the width and depth of each pit are formed at the heads of the pits 70-119. Standard flaws are machined and prepared to product wafers from the combination of width and depth in various size, and calibrated at all times by the detection of scattered light.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standard sample used for calibrating a scattered light detecting device for semiconductor inspection for detecting scattered light in a semiconductor process.

2. Description of the Related Art The prior art is disclosed in Japanese Patent Application Laid-Open No. 6-283593.
In the calibration and testing of the detection capability of various types of optical inspection devices, a test pattern of a point element on a wafer surface is arranged, and the amount of light scattered from the element is cracked like a crack as disclosed in Japanese Patent Application Publication No. There is a method of simulating the amount of light scattered from various defects or particles. FIG. 1 shows a plan view of a reference according to the prior art. Regular groups of light-scattering elements (11,3
1, 33, 35, 37, 47, 57) are arranged in each concentric annular band (15, 25, 43, 53), and the groups are spaced around each annular band (17, 39, 49). Filled with the reference wafer (13). Groups of features that scatter light of the same size are aligned to receive the scanning beam at the same scan location, but at different scans. With this arrangement, the scanner sees the same group of features in different scans and scatters the same amount of light at the same relative position. The shape structure of the point element consists of pits of a predetermined depth and size. In the prior art, the inspection and calibration of the particle detection ability of an optical inspection apparatus (as disclosed in Japanese Patent Publication No. 4-35025) are executed in the above-described pattern.

With the progress of high integration and miniaturization of semiconductor devices, major changes have been made in basic technologies such as device processes, circuit designs, manufacturing apparatuses, and materials. In particular, the depth of focus of lithography for forming a fine pattern has become shallow with the increase in the number of layers in a semiconductor process, and the process margins such as the fine RIE of an interlayer insulating film and a wiring have been reduced. For this reason, it has become necessary to establish a technique that can achieve both the partial planarization at the pattern size level and the overall planarization at the lithography exposure area level within the wafer surface. Under such circumstances, as a new planarization technique, a chemical mechanical polishing method (CMP: Chem)
Ical Mechanical Polish
g) is attracting attention. CMP technology for semiconductors has been used for mirror finishing of wafers for a long time,
The novelty of CMP lies in the application of this technology to device manufacturing processes. For example, the present invention is applied to flattening of PoySi, an interlayer insulating film, and metal wiring buried in a trench (a groove formed for element isolation or a memory cell). A scratch is generated on the film on the wafer surface after the above-mentioned CMP. Causes include falling off of the diamond used for the dresser of the polishing pad and foreign matter in the slurry. For example, after metal CMP, if a small amount of metal remains inside the flaw, there is a problem that a short circuit occurs between lines and the yield is reduced. So, CM
It is necessary to inspect the flaw generated by the P processing. The scratch is a fine, continuous processing mark having a small depth called a scratch. When considering the damage to the semiconductor device manufacturing process due to scratching, it is important to clarify the depth and width of the scratch. In general, S
EM (Scanning Electron Micror)
oscopy) is used, and since the scratch has a depth of, for example, 0.2 μm or less and a width of 1 μm or more, it is difficult to observe the shape by SEM. Further, the standard sample according to the conventional point cannot be used for long defects such as scratches. The object of the present invention has been made in consideration of the above situation, and it is possible to improve the product yield by quantitatively inspecting the depth and width of the scratch and feeding it back to the semiconductor device manufacturing process. It is to provide a test standard sample that can be used.

In order to achieve the above object, the present invention provides a scattered light detecting device for semiconductor inspection,
A set pattern consisting of a plurality of rows (long lines) of pits combining various widths and depths on the substrate surface is processed and arranged in a plurality of blocks, and the longitudinal direction of the pits in each row of the set pattern is The length of the irradiation pattern should be longer than the dimension of the irradiation beam, the set pattern extends from the center of the wafer to the outer periphery of the wafer, and a plurality of blocks are arranged at any radial position at an arbitrary angle in a radial direction. There are intervals, and at the beginning of each row of pits, square pits consisting of the width and depth of each pit are formed, and standard scratches consisting of combinations of widths and depths of various dimensions are processed and manufactured on product wafers Then, it is constantly calibrated by scattered light detection, and standard scratches consisting of combinations of widths and depths of various dimensions are processed and manufactured on bare wafers and wafers in each process step of semiconductor manufacturing. It is achieved by the. That is, in the present invention, it is possible to quantify the depth and width of a scratch with a standard sample of a simulated processing mark manufactured by a processing method such as an ion beam, and to calibrate the scratch detection ability in a scattered light detection device for semiconductor inspection. it can.

FIG. 2 shows an embodiment of the present invention.
Combination of depth and width of various dimensions on the substrate surface during the semiconductor manufacturing process, for example, 5 vertical (depth), 5 horizontal (width)
A set pattern (basic form) of an array group of pits in a total of 25 (odd numbers from 71 to 119) is formed. Various depths and widths of the pits in each row are combinations in a range of 0.025 μm or more and 0.4 μm or less. Further, the longitudinal direction of the pits in each row is longer than the detection resolution in the inspection system imaging system, and longer than the size of the irradiation beam in the illumination range (for example, generally 200 μm in the larger size light amount detection system) in the light amount detection system. Have a One square pit (even number from 70 to 118) representing the depth and width of each pit is formed at the head of each row of pits. The interval between pits in each row in the set pattern is wider than the resolution, and has a constant interval so that only one pit can be detected. The constant spacing between the pits in the row is, for example, 0.2 mm or more in the longitudinal direction and the adjacent parallel direction, respectively. The basic form of the collective pattern according to the present invention has the above configuration. FIG. 3 is a standard sample in which the basic form of the collective pattern according to the present invention is arranged in a wafer plane. The set pattern of the pits in each row extends from the center of the wafer to the outer periphery of the wafer and extends at an arbitrary angle and at an arbitrary radial position radially, for example, at an intersection near the center of the wafer size, near the outer periphery, or near the middle thereof. Arrange multiple blocks. In FIG. 3, in the case of a 5-inch wafer,
The angles with the horizontal axis in the figure are 0 °, 45 °, 90 °, 12 °.
Diameter 30mm, 70mm, 1 that intersects 0 ° and 150 °
Eight aggregate patterns were arranged at a position of 05 mm. In this way, when inspecting while rotating the wafer,
When viewed from the lighting side, a state in which the flaw can be changed at any angle has been realized. The scratches generated by the CMP process have no direction. On the other hand, scattered light from a line pattern such as a scratch has directionality regardless of the illumination method, and C
In order to calibrate the inspection capability for MP flaw detection, unlike a point defect or foreign matter, such an aggregate pattern arrangement having an angle with respect to the detection direction is provided. FIG. 4 shows another type of standard sample in which the basic form of the collective pattern according to the present invention is arranged in a wafer plane. In this type, a set pattern is arranged in a line extending at an arbitrary angle (10 °) from the center of the wafer to the outer periphery of the wafer. FIG. 5 shows another example in which the basic form of the collective pattern according to the present invention is arranged in the wafer plane.
Two other types of standard samples. A set pattern is arranged in a line extending at an arbitrary angle (36 °) from the center of the wafer to the outer periphery of the wafer and arranged at different inclination angles with respect to the wafer. The standard sample shown in FIG. 3 is suitable for an inspection apparatus for scanning a θ-rotation stage, and the standard samples shown in FIGS. 4 and 5 are suitable for an inspection apparatus for scanning an XY stage. still,
One 20 μm square pit (66) was formed at the end of each set pattern to facilitate the search of the set pattern position. Calibrate the performance of the inspection device using this standard sample as follows. When a normal wafer is set and detected in the same way,
Arrangement on the wafer from the pattern arrangement described above, or
The detection values can be summarized for each angle, for each depth, or for each function (for example, product) of width and depth by the mark pit of 20 μm square. In the detection result example using the standard sample of the present invention in FIG. 6, the detection capability is 0.025 μm depth,
It can be understood that the width is 0.5 μm as the maximum sensitivity. We also know the pattern angle and the detection capability, and in the inspection data of scratches on the actual wafer,
If the direction is found from the detected map, the size of the flaw can be estimated. It goes without saying that the square pits and the pits in a row are not only concave but also convex. The pits arranged in a row with a plurality of square pits formed in this way will form dents in the wafer surface corresponding to non-directional scratches, and are used as standard samples of pseudo defects as described above. Can do it. The standard sample of the pseudo flaw according to the present invention is an ion beam processing method (Japanese Patent Publication No. 4-2753).
No. 9). The ion beam processing method is most suitable for producing different pits having different flaw sizes (particularly, the depth of the dents). The size of the flaw is checked by observing the shape of the cross-sectional SEM, but the shape observation is easy because the arrangement size and positional relationship of the pseudo flaws in the wafer surface are known. As a method of processing a pseudo mark having a finer (several nm) shape, there is EBAE (Electron Beam Assisted Etching). Anisotropic etching by lithography may be used instead of the ion beam processing. This standard sample is not limited to a bare wafer, and may be processed into chips on an actual semiconductor device manufacturing process wafer. In an actual product wafer, an inspection output from a scratch changes due to a film thickness underlayer or the like. For this reason, the present invention can also constantly calibrate the scratches on the wafer by processing the pit row in the TEG portion, the scribe area, and the peripheral portion of the product wafer. Thereby, the semiconductor device manufacturing process (interlayer insulating film, damascene, plug, through hole complete, S
GI) can be checked from what level of flaws adversely affect GI and the type of flaw to be detected. It goes without saying that the object of the present invention can be applied not only to semiconductor substrates but also to magnetic disks and glass substrates.

As described above, since the depth and width of the scratch can be quantified by referring to the standard sample, it is possible to inspect the fine scratches. Can contribute to the improvement of product yield.

[Brief description of the drawings]

FIG. 1 is a plan view of a reference standard according to the prior art.

FIG. 2 shows an aggregation pattern according to the present invention.

FIG. 3 is a plan view showing a standard sample in which basic shapes of an aggregate pattern according to the present invention are arranged in a wafer plane.

FIG. 4 is a plan view showing another type of standard sample in which basic shapes of an aggregate pattern according to the present invention are arranged in a wafer plane.

FIG. 5 is a plan view showing another standard sample of another type in which the basic shape of the collective pattern according to the present invention is arranged in the plane of the wafer.

FIG. 6 is a characteristic diagram showing a detection result using a standard sample of the present invention.

[Explanation of symbols]

13. Reference wafer, 11, 31, 33, 35, 37, 4
7,57… Concentric annular band group, 15,25,43,5
3, concentric annular band, 17, 39, 49, interval, 60, standard wafer, 65, collective pattern (basic form), odd number of 71 to 119, array group of pits in rows, even number of 70 to 118, square pits.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yuichi Hamamura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside of Hitachi, Ltd. (72) Inventor Yukio Mibo 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term (reference) 2F065 AA18 AA22 AA25 BB18 BB28 CC19 FF41 FF61 PP12 2G051 AA51 AA90 AB20 CB05 DA07 4M106 AA01 AA07 AB17 AB18 BA02 BA03 CA38 CA48 CB20 DB18 DH60

Claims (7)

[Claims] 1. A scattered light detecting device for semiconductor inspection, wherein a plurality of blocks of pits in a plurality of rows each having a combination of widths and depths of various dimensions are processed and arranged in a plurality of blocks on a substrate surface. Standard sample for detection. 2. A scattered light detecting device for semiconductor inspection, wherein the longitudinal direction of each row of pits of the aggregate pattern has a length equal to or larger than the dimension of the irradiation beam, and the aggregate pattern extends from the center of the wafer to the outer periphery of the wafer. 2. The detection standard sample according to claim 1, wherein a plurality of blocks are arranged at an arbitrary radial position radially at an angle. 3. The method according to claim 1, wherein there is a certain interval between the pits in each row in the set pattern, and square pits having the width and depth of each pit are formed at the head of each pit in each row. The standard sample for detection according to claim 2, wherein 4. The various widths, depths, and lengths of the pits in each row in the aggregate pattern are combinations within the range of μm, and the longitudinal direction and the adjacent parallel direction are μm.
4. The standard sample for detection according to claim 3, wherein the standard sample is at least m order. 5. A combination of pits of various rows and depths within a set pattern within a range of not less than 0.025 μm and not more than 0.4 μm and a length of not less than 50 μm. The standard sample for detection according to claim 4, wherein the interval is a plurality of rows of pits formed in the longitudinal direction and adjacent parallel intervals having a dimension of 0.2 mm or more. 6. A scattered light detection apparatus for semiconductor inspection, wherein a standard flaw having a combination of widths and depths of various dimensions is processed and manufactured on a product wafer, and is constantly calibrated by scattered light detection. Standards for detection. 7. The other detection standard according to claim 6, wherein the standard flaw having a combination of widths and depths of various sizes is processed and formed on a wafer in each process step of semiconductor manufacturing in addition to a bare wafer. sample.