JP2000058547A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently inspect a wiring layer of a semiconductor device where a dummy part is provided at a wiring layer which is covered with an insulating layer, through the insulating layer. SOLUTION: The device 10 comprises an insulating layer 15 for filling a wiring part 12 so that the part 12 formed in protruding form on a semiconductor substrate 11' is covered, and a protruding dummy part 13 filling the insulating layer 15 so that a surface is flattened when the surface of the insulating layer 15 is polished chemically/mechanically. Here, the dummy part 13 is provided with a top-view form discriminable from the wiring part 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device such as a semiconductor IC device, and more particularly, to a semiconductor device having an insulating film for covering a wiring portion formed on a semiconductor substrate.

[0002]

2. Description of the Related Art As a technique for increasing the degree of integration of semiconductor IC devices, there is a multilayer wiring technique. According to the multilayer wiring technology, a wiring portion on a semiconductor substrate is covered with an insulating layer called an interlayer insulating film, and an upper wiring portion is formed on the insulating layer by using a photolithography technology. By the way, the insulating layer is formed so as to protrude in a region where the wiring portion exists inside. On the other hand, the photolithography technique used for forming the upper wiring portion on the insulating layer requires that the surface of the insulating layer be flat for processing accuracy. To meet this requirement, the surface of the insulating film covering the wiring portion on the semiconductor substrate must be chemically mechanically polished (Chemic polishing) prior to forming the upper wiring portion.
al Mechanical Polish Hereinafter, simply referred to as CMP. )
As a result, the surface of the insulating layer is flattened.

In the polishing of an insulating film by CMP, if the arrangement of wiring under the insulating layer becomes uneven, the polishing rate tends to be higher in a coarsely arranged region than in a densely arranged region. Accordingly, the density of the wiring hinders the flattening of the insulating layer with high accuracy. Therefore, conventionally, a dummy wiring is formed of the same material as the wiring in a region where the wiring arrangement on the semiconductor substrate is coarse, and apparently, the wiring arrangement is made uniform in density, thereby achieving the CMP. The accuracy of flattening the insulating film was improved.

[0004]

However, in the conventional semiconductor device, when the wiring under the insulating layer is visually observed through the insulating layer in the inspection step of the wiring layer of the semiconductor device, the wiring is true. It is not easy to determine whether the wiring is a dummy wiring or a dummy wiring. For example, even if a short-circuited portion can be visually observed, if it is a true wiring, it will cause various electrical problems, so that a more detailed inspection is required. However, if the short-circuit portion is a dummy wiring, the visual inspection can be transferred to another portion without any problem.
As described above, if it is possible to easily determine whether the short-circuited portion is a true wiring or a dummy wiring, the inspection process of the wiring layer can be performed extremely efficiently. There has been a demand for a technique that can easily determine whether the above is true.

[0005]

The present invention adopts the following constitution in order to solve the above points. <Structure> The present invention provides an insulating layer for burying a wiring portion formed on a semiconductor substrate and a dummy buried in the insulating layer for planarizing the surface of the insulating layer. And wherein the dummy portion is provided with a planar shape that can be distinguished from the wiring portion.

<Operation> The dummy portion according to the present invention is composed of:
Since it is possible to determine whether or not it is a dummy portion from the planar shape, a problematic portion is observed when the wiring layer below the insulating layer is visually observed through the insulating layer in the inspection step of the wiring layer of the semiconductor device. Is easy to determine whether it is a true wiring or a dummy wiring. Therefore, when the short-circuit portion can be visually observed, for example, it is possible to easily determine whether or not the short-circuit portion due to a foreign substance or the like is a dummy portion that does not need to be a problem. It is possible to do.

One specific example of the planar shape of the dummy portion is to form a gap in a region surrounded by the outer shape of the dummy portion. The true wiring has, for example, a solid planar shape in the shape of a bar, and since no void portion is provided in the planar shape, by visual observation of the planar shape,
It can be easily determined whether or not it is a dummy portion. This void portion can be formed, for example, by extracting a desired shape such as a rectangle, a circle, or a character in a solid portion having a rectangular planar shape.

Another specific example of the planar shape of the dummy portion that enables visual discrimination is an annular planar shape. As a modified example of this annular planar shape, it is conceivable that the annular planar shape is cut out, for example, into a C shape. As still another specific example of the dummy portion that enables visual discrimination, a dummy portion is configured by a plurality of divided portions having a rectangular planar shape, and the divided portions are dispersed at intervals from each other. it can.

The above-described dummy portion provided with the void portion or the dummy portion formed by dispersing the divided portions facilitates visual discrimination, and furthermore, is provided between the wiring on both sides sandwiching the dummy portion. To reduce the parasitic capacitance of
Further, it is more advantageous in that partial see-through of a wiring portion and the like below the dummy portion is allowed.

Further, as another specific example of the dummy portion which enables visual identification, the dummy portion has a property different from that of a wiring made of a conductive material and has a light-transmitting property such as a non-conductive material. It can be composed of materials. The dummy portion made of such a non-conductive material is not only capable of visually discrimination based on its planar shape, but also has the same parasitic capacitance as described above and a point of permitting see-through of a lower wiring portion and the like. This is more advantageous. One of such non-conductive materials is silicon oxide.
When the insulating layer and the dummy portion are made of a similar non-conductive material, for example, when the insulating layer is made of silicon oxide and the dummy portion is made of the same kind of silicon oxide, the shape of the dummy portion is mixed with the background insulating layer. Therefore, it may not be easy to identify the shape of the dummy portion. However, in such a case, the wiring portion can be clearly identified, as opposed to the dummy portion, so that the dummy portion can be easily distinguished from the wiring portion.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. <Embodiment 1> FIGS. 1 and 2 show Embodiment 1 of the present invention.
Are schematically shown, respectively.

As shown in FIGS. 1 and 2, a semiconductor device 10 according to the present invention has a semiconductor substrate 11 made of, for example, silicon crystal and an M substrate formed on the substrate.
And a wiring portion 12 extending from a functional circuit portion (not shown) including a functional circuit such as an OS transistor.

In the illustrated example, the wiring portion 12 is an interlayer covering an element portion such as a transistor formed on the semiconductor substrate 11 and an electrode made of polysilicon (omitted for simplification of the drawing). It is formed on the insulating film 11 '. As is well known in the art, the wiring portion 12 is made of a metal layer such as aluminum, for example.
After forming on 1 ', this metal layer is patterned by using photolithography and etching processing techniques. In the step of forming the wiring portion 12 by this patterning, the dummy portion 13 is formed between the wiring portions simultaneously with the formation of the wiring portion 12 by utilizing the patterning on the metal layer. Therefore, in the specific example 1, the dummy portion 13 is made of the same conductive material as the wiring portion 12.

The wiring portion 12 formed in a convex shape on the interlayer insulating film 11 'on the semiconductor substrate 11 is the same as that shown in FIG.
As can be seen from FIG. 5, it extends along a straight line, and its planar shape is a rod-like shape whose interior has a solid rectangular shape.
On the other hand, as shown in FIG.
When viewed in its planar shape, it has a square outer shape, and by defining a square void portion 14 inward, it has a generally rectangular ring shape. An interval d1 and d2 is maintained between the wiring portion 12 and the dummy portion 13, and an interval d3 is maintained in the void portion 14 of the dummy portion 13 when viewed in a direction crossing between the two wiring portions 12. I have.

The dummy portions 13 between the wiring portions 12 are located between the wiring portions 12, thereby increasing the apparent wiring density of the region where the wiring portions 12 are rough, thereby forming the wiring portions on the semiconductor substrate 11. 12 is made uniform. Therefore, when, for example, a silicon oxide film is formed as the insulating layer 15 to bury the wiring layer (12 and 13) including the wiring portion 12 and the dummy portion 13, the wiring portion 12 is formed on the surface of the silicon oxide film (15). The density of the silicon oxide film does not cause many projections having a small cross-sectional area, and as is well known, the surface of the silicon oxide film can be ground at a uniform grinding speed by CMP. As shown in FIG. 2, a flat surface is formed on the insulating layer 15 covering the wiring layers (12 and 13). On the flat surface of the insulating layer 15, a new wiring as an upper layer is provided as necessary.

One method of inspecting the wiring layers (12 and 13) of the semiconductor device 10 is to visually inspect the wiring portion 12 through the insulating layer 15 using an optical microscope. According to the semiconductor device 10 of the present invention, since the dummy portion 13 is provided with the void portion 14 that is not provided in the wiring portion 12, the wiring portion 12 is not provided in the above-described visual inspection.
The dummy portion 13 given a different planar shape can be easily identified as the wiring portion 12.

Therefore, for example, when a foreign substance 16 is observed between the wiring part 12 and the dummy part 13, at least one of the parts (12 or 1) related to the foreign substance 16 is observed.
If it can be determined that 3) is the dummy portion 13, the inspection portion can be moved to another portion without causing the foreign matter 16 as a problem because the foreign matter 16 does not cause an electrical problem. Therefore, according to the semiconductor device 10 of the present invention, the inspection process of the wiring layers (12 and 13) can be performed quickly.

In the above-described visual inspection, observation on the semiconductor substrate 11 through the gap 14 is permitted.
Observation of a wider portion is possible as compared with a conventional dummy portion having no void portion 14.

Further, the distance d as shown in FIG.
The parasitic capacitance between the pair of wiring portions 12 sandwiching the dummy portion 13 in which the three void portions 14 are defined is substantially d1, d
The value is inversely proportional to the sum of 2 and d3. In contrast,
A pair of wiring portions 12 sandwiching a dummy portion having the same outer shape as the dummy portion 13 in which the void portion 14 is not provided.
The parasitic capacitance between them has a value inversely proportional to the sum of d1 and d2. Accordingly, the provision of the gap portion 14 reduces the parasitic capacitance between the two wiring portions 12 by a value substantially corresponding to the value of d3. Therefore, it is possible to effectively prevent a decrease in electrical characteristics due to the parasitic capacitance. can do.

<Embodiment 2> FIG. 2 shows a semiconductor device 10 of Embodiment 2 according to the present invention. Semiconductor device 10 of specific example 2
In this embodiment, a cut-out portion 13a that opens the gap portion 14 is provided in a part of the dummy portion 13 that defines the gap portion 14, and the dummy portion 13 presenting an annular shape as a whole has a substantially C-shaped planar shape. .

As in the first embodiment, the C-shaped dummy portion 13 facilitates discrimination from the wiring portion 12 by the above-described visual inspection, so that the wiring layer (12 and 1)
3) It is possible to speed up the inspection process. Further, since observation on the conductive substrate 11 is permitted through the gap portion 14 and the notch portion 13a, it is possible to observe a wide portion similar to that in the first embodiment, and it is possible to reduce a decrease in electric characteristics due to parasitic capacitance. It can be effectively prevented.

The outer shape of the dummy portion 13 in plan view is not limited to the above-described square, but may be a circle or a rectangle.
A desired shape can be obtained. In addition, the planar shape of the gap portion 14 is not limited to a square, but may be a punched shape having a desired shape such as a letter such as an alphabet in addition to a circle and a rectangle.

FIG. 3 shows a semiconductor device 10 according to a third embodiment of the present invention. As shown in FIG. 3, the dummy portion 13 is divided into a plurality of divided portions 13 each having a square planar shape, for example, and these divided portions 13 are divided into regions where the arrangement density of the wiring portions 12 is low. ,
It can be dispersed in the form of dots. Fig. 3 dispersed in a point shape
Of the first and second examples by the four dummy portions 13 of FIG.
The same effect as each dummy portion 13 shown in FIG.

In the above description, the example in which the dummy portion 13 is made of the same material as the wiring portion 12 has been described.
The dummy portion 13 can be formed of, for example, an insulating material having a light-transmitting property similar to the insulating layer 15, that is, a non-conductive material. The dummy portion made of a non-conductive material as described above allows visual discrimination based on the planar shape thereof, and allows the same parasitic capacitance and the lower wiring portion as described above to be seen through. In that respect, it is more advantageous.

The dummy portion 13 made of the same material as the insulating layer 15 may not be easy to identify the shape of the dummy portion because its planar shape is hidden by the insulating layer 15 which is the background. If it is, the wiring part 12
Can be clearly identified, so that a clearly visible portion can be determined to be the wiring portion 12, and conversely, an unclear portion can be determined to be the dummy portion 13. Therefore, even in the case of the dummy portion 13 made of the same material as the insulating layer 15, the dummy portion 13 and the wiring portion 12 can be easily visually distinguished.

[0026]

According to the present invention, as described above, when the wiring under the insulating layer is visually observed through the insulating layer in the inspection step of the wiring layer of the semiconductor device, a problematic portion is a true wiring. Since it is easy to determine whether a part is a dummy part or not, when a short-circuited part is visible, it can be easily determined whether or not the short-circuited part is a dummy part that does not need to be considered. Thereby, the inspection process of the wiring layer becomes remarkably efficient.

[Brief description of the drawings]

FIG. 1 is a plan view partially showing a semiconductor device according to the present invention.

FIG. 2 is a sectional view taken along the line II-II shown in FIG.

FIG. 3 is a view similar to FIG. 1, showing another semiconductor device according to the present invention.

FIG. 4 shows still another semiconductor device according to the present invention.
FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor substrate 12 Wiring part 13 Dummy part 14 Void part 15 Insulating layer

Claims (5)

[Claims] An insulating layer for burying a wiring portion formed on a semiconductor substrate so as to cover the wiring portion, and a dummy portion buried in the insulating layer for planarizing a surface of the insulating layer. Wherein the dummy portion has a planar shape that can be distinguished from the wiring portion. 2. The semiconductor device according to claim 1, wherein the dummy portion defines a void portion in a region surrounded by an outer shape of the dummy portion when viewed in plan view. 3. The semiconductor device according to claim 1, wherein the dummy portion has an annular planar shape as a whole. 4. The semiconductor device according to claim 1, wherein said dummy portion comprises a plurality of divided portions having a rectangular planar shape, and each of the divided portions is dispersed with an interval therebetween. 5. The semiconductor device according to claim 1, wherein said dummy portion is made of a light-transmitting non-conductive material.