JP2000057784A - Semiconductor memory apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory apparatus which can prevent incorrect writing without increasing a time required for writing. SOLUTION: The semiconductor memory apparatus has a memory cell array 101 in which nonvolatile memory cells are arranged in matrix, a data latch 102 working also as a sense amplifier, decoders 105, 103 for selecting memory cells, a write voltage generation circuit 108 for generating a higher write voltage than a source voltage which is to be fed when data is written to the selected memory cell, and an intermediate voltage generation circuit 109 for generating an intermediate voltage higher than the source voltage and lower than the intermediate voltage which is to be fed when data is written to the non-select memory cell. An output control circuit 111 is provided so that an output voltage of the intermediate voltage generation circuit 109 follows an output voltage of the write voltage generation circuit 108 before reaching a predetermined level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that is useful when applied to an EEPROM or the like that performs data write control using a boosted write voltage.

[0002]

2. Description of the Related Art Conventionally, as one of the semiconductor memory devices, an EEPOM capable of electrically rewriting has been known. Above all, NAN by connecting a plurality of memory cells in series
The NAND cell type EEPROM constituting the D cell is attracting attention as a device that can be highly integrated. NAND type EE
A PROM memory cell has an FETM in which a charge storage layer (floating gate) and a control gate are stacked on a semiconductor substrate.
An OS structure is used. This memory cell stores data “0” and “1” according to the amount of charge stored in the floating gate.

FIG. 25 shows two adjacent NAND cells. Eight memory cells M1 to M1 connected in series
One end of M8 is connected to a bit line BL via a selection gate S1, and the other end is connected to a common source line via another selection gate S2. The control gate of each memory cell in the NAND type cell is connected to control gate lines CG1, CG2,.
Commonly provided as CG8, this becomes a word line.
The gate electrodes of the selection gates S1 and S2 are also commonly connected in the horizontal direction as selection gate lines SG1 and SG2.

To write data in such a NAND type cell, a boosted write voltage of about 20 V is applied to a selected word line (control gate line), and an intermediate voltage of about 8 to 10 V is applied to a non-selected word line. A voltage is applied to control the channel voltage of the selected memory cell according to data "0" and "1". For example, in FIG.
Data "1" and "0" are given to L1 and BL2, respectively.
A case is shown in which the write voltage VPGM is applied to the control gate line CG2, and the intermediate voltage VMWL is applied to the other non-selection control gate lines CG1, CG3 to CG8, and "1" is written to the memory cell M21.

That is, the bit line B for writing “1” data
L1 is set to 0 V, and this bit line voltage is transferred to the channel of the selected memory cell. Thereby, the selected memory cell M2
In the case of 1, electrons are injected into the floating gate by the tunnel current, and the threshold value becomes positive. VCC is applied to the bit line BL2 for writing "0" data, VCC is applied to the selection gate line SG1, and the selection gate S11 is turned off. Therefore, the channel of the memory cell along the bit line to which "0" data is applied becomes floating. As a result, the potential of the channel rises due to capacitive coupling from the control gate and reaches about 8 V, so that the write voltage VPGM
Cell M along the control gate line CG2
Even at 22, there is no change in the threshold value, and a negative threshold value state, that is, "0" data is written.

[0006] Data erasing in a NAND type cell is performed, for example, by applying 0 V to all word lines in the entire memory cell array.
Is applied to the substrate or well to apply an erasing voltage of about 20 V to discharge the charge of the floating gate to the substrate side in all the memory cells. As a result, all the memory cells are erased to the state where the threshold value is negative data "0". When there are a plurality of memory cell arrays, data may be erased in block units. In this case, a well may be formed for each block, the above conditions may be given to the selected block, and all the word lines may be left floating for the unselected block.

For data reading, 0 V is applied to the selected word line, and an intermediate voltage for turning on the memory cell irrespective of data "0" or "1" is applied to the remaining word lines to determine whether or not the NAND cell becomes conductive. Is detected by a bit line.

[0008]

The above-mentioned conventional EEP
In a ROM, a write voltage VP for writing data is used.
A separate booster circuit is required to generate the GM and the intermediate voltage VMWL. However, the boosting times of the write voltage boosting circuit and the intermediate voltage boosting circuit vary depending on manufacturing conditions, temperature, and other conditions. This variation in the boosting time causes erroneous writing.

The reason why the erroneous writing occurs will be described in detail with reference to FIG.
This will be described with reference to FIG. In FIG. 26, in the above-described example of data writing, boosting is started at timing t0, and when the write voltage VPGM is applied to the control gate line CG2 and the intermediate voltage VMWL is applied to the remaining control gate lines, the intermediate voltage VMWL rise is equal to the write voltage VP
This shows a case where the speed is slower than that of GM. Such a delay in the boosting time of the intermediate voltage VMWL is not only due to the above-described variation in the manufacturing conditions, but also due to the difference in the magnitude of the load of each boosting circuit. That is, the write voltage VPGM is applied to one selected control gate line, and the intermediate voltage VMWL is applied to all remaining control gate lines. As a result, there is a delay in boosting the intermediate voltage as shown in FIG.

At this time, in the above-described example of data writing, the potential Vchannel of the floating channel along the bit line BL2 to which "0" data is applied is set to the level shown in FIG.
As shown in (5), since the capacitive coupling with the non-selection control gate line becomes dominant, it rises almost following the intermediate voltage VMWL. Looking at the timing t1 when the write voltage VPGM has become almost the desired 20V, the intermediate voltage VMWL has not yet reached the desired 10V. At this time, along the control gate line CG2 to which the write voltage VPGM is applied,
“1” writing is performed in the memory cell M21 to which the data “1” is given to the bit line BL1, but attention is paid to the memory cell M22 to which “0” data is given to the bit line BL2 along the same control gate line CG2. Then, at timing t1
In this case, since the voltage of the channel has not reached 8 V, a voltage higher than the desired voltage of 20 V-8 V = 12 V required to prevent electron injection is applied between the control gate and the channel. As a result, electron injection may occur erroneously in the memory cell M22, and “1” writing may be performed.

In particular, when the charging operation of the write voltage VPGM and the intermediate voltage VMWL is accelerated in order to shorten the data write time, it becomes difficult to finely control the charge required time, and the above-described erroneous write operation is performed. The danger is greater. On the other hand, in order to prevent the erroneous writing described above, a method in which the charging of the intermediate voltage precedes that of the writing voltage may be considered. However, this method has a drawback that the total time required for writing data is lengthened. A similar problem is the EEPR using NAND cells.
Not only OM, but also other EEs that selectively write data by using a write voltage and a lower intermediate voltage together
It also exists in PROM.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to provide a semiconductor memory device capable of preventing erroneous writing without increasing the time required for writing.

[0013]

A semiconductor memory device according to the present invention comprises a memory cell array in which memory cells which are electrically rewritable and store data in a nonvolatile manner are arranged in a matrix, and data read from the memory cell array is sensed. A sense amplifier / data latch for latching write data, a decoder for selecting a memory cell of the memory cell array, and generating a write voltage higher than a power supply voltage applied to a selected memory cell of the memory cell array when writing data. A write voltage generator circuit, an intermediate voltage generator circuit for generating an intermediate voltage higher than a power supply voltage and lower than the write voltage, which is provided when data is written to unselected memory cells of the memory cell array, and an output of the intermediate voltage generator circuit. Voltage and the output of the write voltage generation circuit. To limit the difference in voltage until the output voltage of the intermediate voltage generating circuit reaches a predetermined level, an output control circuit to continue to rise in the output voltage of the write voltage generation circuit in a subsequent state in which the difference of the output voltage is not limited,
It is characterized by having.

According to the present invention, for example, the write voltage generating circuit includes a first booster circuit that boosts a power supply voltage to generate the write voltage, and that the output voltage of the first booster circuit reaches a predetermined value. A first limit circuit for detecting and outputting a limit signal, the intermediate voltage generating circuit boosting a power supply voltage to generate the intermediate voltage, and a second booster circuit And a second limit circuit for detecting that the output voltage has reached a predetermined value and outputting a limit signal. The output control circuit includes, for example, a short circuit for selectively shorting an output node of the write voltage generation circuit and an output node of the intermediate voltage generation circuit, and a rising edge of a boost control signal of the first and second boost circuits. And a bias circuit that controls the short circuit to be turned on for a certain period of time by an output pulse of the edge detection circuit, and controls the intermediate voltage to follow the write voltage.

In order to control the bias circuit, for example, (a) a flip-flop which is set by an output of the edge detection circuit and is reset by a limit signal obtained from a second limit circuit, or (b)
The time width of the output pulse of the edge detection circuit is set to the time from when the output of the first booster circuit reaches the time immediately before the boosting start value of the intermediate voltage until the output of the first booster circuit. The short circuit is turned on at the rising edge of the signal, and the short circuit is turned off at the falling edge of the signal. In the present invention, preferably, the memory cell array is configured by arranging NAND cells each configured by serially connecting a plurality of memory cells each having a floating gate and a control gate stacked on a substrate. The write voltage is applied to the control gate of the memory cell
It is assumed that a data write mode for applying the intermediate voltage to a control gate of a non-selected memory cell in the D cell is provided.

The semiconductor memory device according to the present invention further comprises a memory cell array in which memory cells are arranged in a matrix,
A sense amplifier / data latch for sensing read data of the memory cell array and latching write data; a decoder for selecting a memory cell of the memory cell array; and a power supply voltage applied to a selected memory cell of the memory cell array. A first boosted voltage generation circuit for generating a high first boosted voltage; and a second boosted voltage higher than a power supply voltage and lower than the first boosted voltage, which is supplied to unselected memory cells of the memory cell array. And a difference between the output voltage of the second boosted voltage generating circuit and the output voltage of the first boosted voltage generating circuit, wherein the output voltage of the second boosted voltage generating circuit is a predetermined level. And then the output voltage of the first boosted voltage generation circuit is continuously increased in a state where the difference between the output voltages is not limited. An output control circuit that, characterized by comprising a.

According to the present invention, the difference between the write voltage applied to the selected memory cell and the intermediate voltage applied to the non-selected memory cells is limited by the output control circuit until the intermediate voltage reaches a predetermined level. ing.
Specifically, the intermediate voltage is made to follow the write voltage until it reaches a certain level. This prevents erroneous writing due to the rise of the intermediate voltage being delayed as compared with the writing voltage.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block configuration of a NAND cell type EEPROM according to one embodiment of the present invention.
As described later, the memory cell array 101 is configured by arranging NAND cells in which nonvolatile memory cells are connected in series. A sense amplifier / data latch 102 is provided to sense bit line data of the memory cell array 101 or hold write data. The sense amplifier / data latch 102 also performs bit line potential control when verify reading after data writing and rewriting to insufficiently written memory cells, and is mainly configured by, for example, a CMOS flip-flop.

The sense amplifier / data latch 102 is connected to a data input / output buffer 106. Sense amplifier / data latch 102 and data input / output buffer 10
6 is controlled by the output of the column decoder 103 that receives the address signal from the address buffer 104. A row decoder 105 is provided for the memory cell array 101 to select a memory cell, more specifically, to control a control gate and a selection gate. The substrate potential control circuit 107 is provided for controlling the potential of the p-type substrate (or p-type well) on which the memory cell array 101 is formed.

A write voltage generation circuit 108 is provided to generate a write voltage higher than a power supply voltage when writing data to a selected memory cell of the memory cell array 101. In addition to write voltage generation circuit 108, an intermediate voltage generation circuit 109 for generating an intermediate voltage applied to unselected memory cells at the time of data writing is provided. Intermediate voltage generation circuit 1
09 generates an intermediate voltage lower than the above-mentioned write voltage but higher than the power supply voltage.

A drive signal control circuit 110 is provided to control the write voltage generation circuit 108 and the intermediate voltage generation circuit 109. In addition, an output control circuit 111 is provided to perform control to make the output voltage of the intermediate voltage generation circuit 109 follow the output of the write voltage generation circuit 108 under certain conditions. Specifically, the output control circuit 111 determines the maximum value of the difference between the output voltage of the intermediate voltage generation circuit 109 and the output voltage of the write voltage generation circuit 108 until the output voltage of the intermediate voltage generation circuit 109 reaches a predetermined level. The control is performed so that the output voltage of the write voltage generation circuit 108 continues to increase while the maximum value is not limited.

FIGS. 2A and 2B show the memory cell array 1.
3A and 3B are a plan view and an equivalent circuit diagram of one NAND cell portion of FIG.
It is B 'sectional drawing. The NAND cell is formed in a region surrounded by an element isolation insulating film 12 on a p-type silicon substrate 11. In each memory cell, a floating gate 14 (14 ₁ , 14 ₂ ,..., 14 ₈ ) is formed on a substrate 11 via a gate insulating film 13, and a control gate 16 (16 ₁ ) is provided thereon via an interlayer insulating film 15. , 16 ₂ ,..., 16 ₈ ) are formed. N-type diffusion layers 19 (19 ₀ , 19 ₁ ,..., 1) serving as source and drain diffusion layers of these memory cells.
9 ₁₀ ) are connected so as to be shared between adjacent ones, thereby forming a NAND cell.

The drain of the NAND cell, each of the source, a floating gate, selected simultaneously formed with the control gate gate 14 ₉ of the memory cells, 16 ₉ and 14 _10, 16 ₁₀
Is provided. The substrate on which the elements are formed is covered with a CVD oxide film 17, on which a bit line 18 is provided. The bit line 18 is in contact with the drain-side diffusion layer 19 at one end of the NAND cell. N lined up in the row direction
The control gates 14 of the AND cells are shared by a control gate line CG
1, CG2,..., CG8, which are word lines. Select gate 14 _9, 16 ₉ and 14 _10, 16
₁₀ are also arranged continuously in the row direction and select gate lines S
G1 and SG2.

FIG. 4 shows an equivalent circuit of a memory cell array 101 in which such NAND cells are arranged in a matrix. A NAND cell group in the range surrounded by a broken line that shares the same control gate line (word line) and select gate line is called a block, and the read and write operations are usually performed by selecting one of a plurality of blocks. Done.

FIG. 5 shows a configuration of the write voltage generation circuit 108 and the intermediate voltage generation circuit 109 in FIG. The write voltage generation circuit 108 is a VPGM booster circuit 5 for obtaining a write high voltage VPGM from the power supply VCC.
Similarly, the intermediate voltage generating circuit 109 has a VMWL boosting circuit 53 for obtaining an intermediate voltage VMWL applied to a non-selected word line at the time of writing. These VPGM
The output node N1 of the booster 51 and the VMWL booster 5
Output control circuit 11 connected between output nodes N2
1 controls a short circuit and an open circuit between the output nodes N1 and N2 under a certain condition, which will be described later in a specific example.

The upper limit of the output of the VPGM booster circuit 51 is set, and when the upper limit is reached, the limit signal VPMLMT
Is provided. VMW
A limit circuit 54 that similarly sets the upper limit of the output of L booster circuit 53 and outputs limit signal VMWLLMT.
Is provided.

As the VPGM boosting circuit 51 and the VMWL boosting circuit 53, well-known boosting circuits as shown in FIG. 6 are used. One end of each of the capacitors C1, C2,..., C5 is connected to a diode-connected pull-up N
, Q15 are connected to the power supply VCC via MOS transistors Q11, Q12,..., Q15, and the other ends are supplied with complementary driving clocks CK1, CK2 shown in FIG. 7 through pumping inverters I01, I02,. It is connected to the. The capacitors C1, C2,..., C5 of the respective stages and the NMOS transistors Q11, Q12,
, Q15 are connected between diode-connected charge-transfer NMOS transistors Q21, Q22,.
.., Q25 are connected.

This booster circuit includes driving clocks CK1, C
The charge driven by K2 and charged in each capacitor from the power supply VCC is repeatedly transferred to the next capacitor when the polarity of the drive clocks CK1 and CK2 is inverted, whereby the voltage boosted from the power supply VCC is repeated. VP
GM and VMWL are generated. In general, the higher the number of boosting stages, the higher the boosted voltage is obtained. Therefore, the VPGM boosting circuit 51 that generates the write voltage VPGM of about 20 V
The number of stages is set larger than that of the VMWL boosting circuit 52 that generates the intermediate voltage VMWL of about 0V.

A D-type NMOS transistor Q3 for boost control is connected between the output terminal of the booster circuit and the power supply VCC. The gate of the MOS transistor Q3 has
The boost control signal BOOST is input via the inverter I.
While the control signal BOOST is "L", the MOS transistor Q3 is on and keeps the output terminal at VCC. Control signal BO
When OST becomes "H", the NMOS transistor Q3 is turned off, and when the clocks CK1 and CK2 are input, a boosted voltage gradually rising from VCC is generated.

The boosting drive clocks CK1 and C shown in FIG.
It is the drive signal control circuit 110 of FIG. 1 that generates K2. Specifically, this drive signal control circuit 110
As shown in (1), a ring oscillator 81 is mainly used. The ring oscillator 81 includes chain-connected inverters I1, I2,..., In, capacitors C11, C12,..., C1n provided at each stage, and a NAND gate G1 for controlling ring connection. A control signal BOOST is connected to one end of the NAND gate G1.
Enters. That is, when the control signal BOOST changes to “H”, the ring oscillator 81 is activated and starts oscillating.

The oscillation output of node A of ring oscillator 81 enters one input terminal of each of NAND gates G11 and G12. The other input terminals of the NAND gates G11 and G12 respectively have limit circuits 52 and 5 shown in FIG.
4 limit signals VPGMLMT, VMW
LLMT enters. Write voltage VPGM, intermediate voltage VM
Until WL reaches a certain upper limit, the limit signal VPG
MLMT and VMWLLMT are “L”, and at this time, the output of the ring oscillator 81 is the NAND gate G11,
Output through G12.

The output of the NAND gate G11 becomes one drive clock CK1 (VPGM) for the write voltage via the one-stage inverter I21, and the other drive clock CK2 (VGM) via the two-stage inverters I22 and I23.
PGM). Similarly, the output of the NAND gate G12 becomes one drive clock CK1 (VMWL) for the intermediate voltage via the one-stage inverter I31, and the other drive clock CCK via the two-stage inverters I32 and I33.
K2 (VMWL). When the write voltage VPGM and the intermediate voltage VMWL reach the respective upper limits, the limit signals VPGMLTM and VMWLLMT become “H”, the NAND gates G11 and G12 are closed, and the drive clocks CK1 and CK2 stop.

FIG. 9 shows the configuration of the limit circuit 52 in the write voltage generation circuit 108 shown in FIG. The limit circuit 52 includes resistors R11 and R11 that divide the write voltage VPGM, which is started to be boosted by the control signal BOOST.
It comprises a voltage dividing circuit 521 constituted by R12 and a differential amplifier circuit 522 to which the divided output is inputted.
An activation MOS transistor Q101 activated by BOOST is inserted in the voltage dividing circuit 521. The differential amplifier circuit 522 includes a differential NMOS transistor pair Q1
02, Q103, and a current mirror type differential amplifier circuit comprising a pair of PMOS transistors Q104, Q105 as active loads. When the signal BOOST is “H”,
When the write voltage VPGM reaches a certain level, the differential amplifying circuit 522 detects this and outputs a limit signal VPMLMT which becomes “H”.

FIG. 10 shows the intermediate voltage generating circuit 1 shown in FIG.
This is the configuration of the limit circuit 54 in 09 and is the same as that shown in FIG. That is, the resistors R21 and R22 for dividing the intermediate voltage VMWL and the activation MOS transistor Q1
11 and a differential amplifier circuit 542 that inverts when the divided output exceeds a predetermined level.

FIG. 11 is a structural example of the output control circuit 111 of FIG. The output control circuit 111 functions as a short circuit 134 for selectively short-circuiting the output node N1 of the write voltage generation circuit 108 and the output node N2 of the intermediate voltage generation circuit 109.
D-type NMOS transistor Q100 interposed between
have. In order to control the conductivity of the short-circuiting NMOS transistor Q100, an edge detection circuit 131 for detecting a rising edge of the boost control signal BOOST, a flip-flop 132 set by an output of the edge detection circuit 131, and a flip-flop A bias circuit 133 for controlling the gate of the short-circuiting NMOS transistor Q100 by the output of 132 is provided.

The edge detection circuit 131 outputs a control signal BOO
ST enters one input terminal directly, and the other input terminal receives control signal BO via inverter I131 and delay element τ.
A NAND gate G131 into which a signal delayed by inverting the OST enters and an inverter I132 provided at the output thereof
Consists of Thus, the edge detection circuit 131 outputs a pulse having a time width determined by the delay element τ at the rising edge of the control signal BOOST. Flip-flop 1
32 is configured by combining two NOR gates G132 and G133, and is set by an output pulse from the edge detection circuit 131.

The bias circuit 133 is complementarily driven by the output of the flip-flop 132 and has NMOS transistors Q131 and Q132 whose sources are grounded, the drains of these NMOS transistors Q131 and Q132, and the output node of the VPGM booster circuit 51. It has PMOS transistors Q133 and Q134 connected between N1. The connection node between the NMOS transistor Q132 and the PMOS transistor Q134 is connected to the gate of the short-circuiting NMOS transistor Q100 and the PMOS transistor Q1.
It is connected to 33 gates. The gate of the PMOS transistor Q134 is connected to a connection node between the NMOS transistor Q131 and the PMOS transistor Q133.

In the output control circuit 111 configured as described above, when the control signal BOOST rises and the output Qa of the flip-flop 132 goes to "L", the NMOS transistor Q131 is turned on, and therefore the PMOS transistor Q134 is turned on. Transistor Q132 turns off. Thereby, the short-circuit MOS transistor Q
The gate node CON1H of 100 is short-circuited with the output node N1 of the VPGM booster circuit 51, and rises together with the output node N1. At this time, the short-circuit MOS transistor Q10
0 is on, so that the intermediate voltage VMWL, which originally shows a gentle rise compared to the rise of the write voltage VPGM,
Rises following the write voltage VPGM.

When the flip-flop 132 is reset by the limit signal VMWLLMT obtained from the limit circuit 54 in the intermediate voltage generating circuit 109, the NMOS transistor Q132 turns on and the PMOS transistor Q1
34 is turned off, and the short-circuit MOS transistor Q100
Gate node CON1H attains the ground potential, and short-circuit MOS transistor Q100 is turned off. Accordingly, the output nodes N1 and N2 are disconnected, and the operation is performed such that the intermediate voltage VMWL from the VMWL boosting circuit 53 remains at the upper limit and the write voltage VPGM continues to increase.

The data write operation of the EEPROM according to this embodiment will be specifically described with reference to FIG. A write signal PROGRAM is input, and VCC and VSS (= 0 V) are applied to the bit line BL according to data "0" and "1", and the select gate line S on the drain side of the selected block is provided.
G1 is VCC, and the source side select gate line SG2 is VSS.
Is given. As a result, in the channel along the bit line to which the “1” data is applied, Vchannel = 0 V, and in the channel along the bit line to which the “0” data is applied, Vchannel = Vcc−Vth is floating.

Then, at timing t0, the boost control signal B
When OOST rises, the VPGM booster circuit 51 and V
The MWL boosting circuit 53 starts the boosting operation, and the selected control gate line of the selected block (CG2 in FIG. 12)
Is supplied with the write voltage VPGM, and the remaining unselected control gate line CGi of the selected block is supplied with the intermediate voltage VMWL. As long as the limit circuits 52 and 54 in the write voltage generation circuit 108 and the intermediate voltage generation circuit 109 do not output the limit detection signals VPGMLMT and VMWLLMT,
In the output control circuit 111, as described above, the short-circuit MOS
The gate node CON1H of the transistor Q100 follows the write voltage VPGM. Accordingly, the short-circuit MOS transistor Q100 is on, and during this time, the output node N1 of the VPGM booster circuit 51 and the output node N2 of the VMWL booster circuit 54 are short-circuited. Thereby, as shown in FIG. 12, the intermediate voltage VMWL rises following the write voltage VPGM. As the intermediate voltage VMWL rises,
Floating channel potential Vchanne due to capacitive coupling
l also rises.

At timing t1, the intermediate voltage generation circuit 10
9 outputs the limit signal VMWLLMT = “H” at VMWL = 10 V, which is sent to the drive signal control circuit 110, and the intermediate voltage clocks CK1 (VMWL) and CK2 (VMWL) shown in FIG. Is turned off. As a result, the intermediate voltage VMWL becomes 1
The rise stops at 0V. At the same time, the limit signal VMWLL
By MT = “H”, the flip-flop 132 is reset in the output control circuit 111. Thereby, the gate node CON1H of the short-circuit MOS transistor Q100
Becomes "L" (= VSS), and the output nodes N1 and N2
Since it is CC or more, the short-circuit MOS transistor Q100
Turns off. Thereafter, only the write voltage VPGM is
The increase continues regardless of the intermediate voltage VMWL.

Then, at timing t2, the limit circuit 52 in the write voltage generation circuit 108
When PGMLMT = "H" is output, the write voltage VP
GM stops rising at, for example, 20V. Then, among the memory cells along the control gate line CG2 to which the write voltage VPGM is applied, in the memory cell to which the data “1” is applied to the bit line BL, electron injection from the channel to the floating gate occurs, and “1” "Writing is done. “0”
In a memory cell along a bit line to which data is applied,
The channel potential rises due to capacitive coupling, and no electron injection occurs. In a memory cell along a bit line to which "1" data is applied, an intermediate voltage VMWL is applied to a control gate line.
Is given, no electron injection occurs because the voltage between the control gate and the channel is only 10 V.

Therefore, according to this embodiment, the rising of the intermediate voltage VMWL is different from the writing voltage VP as in the prior art.
As a result, a rise in the channel potential of the memory cell along the bit line to which "0" data is applied is delayed, thereby preventing an erroneous write from occurring.

In FIG. 11, a D-type NMOS transistor Q10 is used as the short circuit 134 of the output control circuit 111.
0 is used, but the short circuit 134 is
It can be deformed as shown in (a) to (f). FIG.
(A) is an example in which an E-type NMOS transistor Q141 is used as a short-circuit MOS transistor. FIG.
FIG. 3B shows an example in which an E-type NMOS transistor Q142 diode-connected to FIG. 13A is further connected in series. FIG. 13C is an example in which a diode-connected E-type NMOS transistor Q143 is further connected in series to FIG. FIG.
(D) shows an E-type NM diode-connected to the D-type NMOS transistor Q100 shown in FIG.
This is an example in which OS transistors Q142 are connected in series.
FIGS. 13E and 13F respectively show FIGS.
This is a configuration in which the upper and lower sides of the transistor of FIG.

13A, 13B, 13D, and 13F, the write voltage VPGM and the intermediate voltage VM that are short-circuited.
A difference in threshold voltage for one MOS transistor occurs between WLs. In FIGS. 13C and 13E, there is a difference in threshold value for two NMOS transistors. For example, FIG.
FIG. 14 shows the write operation timing corresponding to FIG. 12 when the short-circuit MOS transistor Q141 of FIG. 3A is used. The difference from FIG. 12 is that at the timing t1 when the intermediate voltage limit signal VMWLLMT becomes “H” (= VCC), the intermediate voltage VMWL = 10
As V, the write voltage is VPGM = 10V + Vthn1
(Vthn1: the threshold value of the MOS transistor Q141), and the node CON1H and the control gate line CG2, which have the same potential, are also at 10V + Vthn1.

As described above, at the time of boosting the intermediate voltage, the write voltage VPGM and the intermediate voltage VMWL do not necessarily have to be at the same potential. Even if there is a slight potential difference, there is no problem as long as erroneous writing does not occur. This is because the above-described erroneous writing does not occur if the boosting of the intermediate voltage is completed before the charging of the writing voltage is completed. At the time point when the boosting of the intermediate voltage VMWL is completed, the write voltage VPGM
And the intermediate voltage VMWL is set to a small value determined by the threshold value of the MOS transistor, and the write voltage VPGM is at a value lower than the set level 20V, and it takes more time to complete the step-up of the write voltage VPGM.
This is because the completion of the boosting of the VPGM is always after the completion of the boosting of the VMWL.

As described above, by using the configurations shown in FIGS. 13A to 13F, the potential difference between the two when the intermediate voltage VMWL follows the write voltage VPGM can be set appropriately. Accordingly, it is possible to minimize the time required for boosting the write voltage VPGM within a range in which erroneous writing does not occur.

In the above embodiment, the method of applying VCC to the bit line for writing "0" data has been described. However, the same intermediate voltage VMWL as that of the unselected control gate line is applied to the select gate line SG1 on the bit line side. Another intermediate voltage VMBL (for example, VMBL = 8) is applied to the bit line for writing “0” data.
V) can also be used. In this case, the write voltage generation circuit 108 and the intermediate voltage generation circuit 1 of FIG.
In addition to 09, another intermediate voltage generating circuit is required.

Write voltage generating circuit 1 of such an embodiment
08, intermediate voltage generation circuit 109 and output control circuit 111
15 is shown in FIG. 15 corresponding to FIG. In addition to the write voltage generation circuit 108 and the intermediate voltage generation circuit 109, another intermediate voltage generation circuit 109b is provided as shown. This intermediate voltage generation circuit 109
b generates the intermediate voltage VMBL to be applied to the bit line for supplying the “0” data as described above.
Step-up circuit 55 and limit circuit 56 for setting the upper limit
It is composed of

The output control circuit 111 is provided between the write voltage generating circuit 108 and the intermediate voltage generating circuit 109 for the same purpose as that between the write voltage generating circuit 108 and the output nodes N1 and N3 of the intermediate voltage generating circuit 109b. Is provided with an output control circuit 111b. Intermediate voltage generation circuit 1
With the addition of 09b, the drive signal control circuit 110 is also changed. That is, in addition to the circuit shown in FIG. 8, a complementary clock generation unit connected to the node A of the ring oscillator 81 shown in FIG. This clock generation unit is connected to the limit circuit 5 in the intermediate voltage generation circuit 109b.
Stopping clock generation under the control of the limit signal VMBLLMT obtained from the write voltage VP
This is the same as the clock generator for generating the GM and the intermediate voltage VMWL.

The intermediate voltage generating circuit 109b shown in FIG.
The limit circuit 56 is configured as shown in FIG.
The configuration is similar to that of the limit circuit 52 shown in FIGS.
It is basically the same as 54 and includes a resistance voltage dividing circuit 561 and a differential amplifier circuit 562.

FIG. 18 shows the output control circuit 1 in FIG.
11b. This is also basically configured similarly to the output control circuit 111 shown in FIG. That is, VP
A short-circuit NMOS transistor Q100b, which short-circuits under a certain condition, is interposed between the output node N1 of the GM booster circuit 51 and the output node N3 of the VMBL booster circuit 55.
In order to control the S transistor Q100b, an edge detection circuit 131b for detecting a rising edge of the boost control signal BOOST, a flip-flop 132b set by the edge detection circuit 131b, and a bias circuit 13 controlled by the flip-flop 132b
3b.

The write operation timing of this embodiment is
FIG. 19 is shown corresponding to FIG. At timing t10, the boost control signal BOOST rises, and follows the write voltage VPGM so as to follow the two intermediate voltages VMWL and VMBL.
Rises. At timing t11, when VMBL = 8V and the limit signal VMBLLMT = "H" is output, in the output control circuit 111b, the gate node CON2H of the short-circuit MOS transistor Q100b becomes "L" and the MOS transistor Q100b is turned off. . Therefore, the intermediate voltage VMBL is cut off from the write voltage VPGM, and thereafter, the write voltage VPGM and the intermediate voltage VMWL
Continues to rise. At timing t12, the intermediate voltage VMWL becomes 10 V, and the limit signal VMWLLMT
When "H" is output, the intermediate voltage VMWL is cut off from the write voltage VPGM, and thereafter, only the write voltage VPGM rises, as in the previous embodiment. Timing t
At 13, the write voltage VPGM becomes 20 V, and the boosting of the write voltage VPGM also stops.

As described above, also in this embodiment, the intermediate voltages VMWL and VMBL are made to follow the write voltage VPGM until the boosting is completed.
Completion of the boosting of the intermediate voltages VMWL and VMBL can be earlier than completion of the boosting of the write voltage VPGM, and erroneous writing can be prevented as in the previous embodiment. In particular, in the case of this embodiment, the channel of the memory cell connected to the bit line of "0" data is directly connected to the intermediate voltage VMBL from the bit line.
By setting to, erroneous writing can be more reliably prevented.

In the embodiments described above, the output voltage control circuit 111 detects the limit of the intermediate voltage, and controls the separation of the output node N2 of the intermediate voltage and the output node N1 of the write voltage based on the detection result. did. On the other hand, the output voltage control circuit 111 may cause the intermediate voltage output node N2 to follow the write voltage output node N1 for a predetermined period of time. In this case, the two output nodes N1,
It is desirable to set the time for keeping N2 in a short-circuit state to be approximately the time required for charging the intermediate voltage.

When this method is used, the output voltage control circuit 111 can be configured as shown in FIG. 20 instead of FIG. That is, the pulse width determined by the delay element τ of the rising edge detection circuit 131 of the boost control signal BOOST is defined as T1, and this is directly used as the time for short-circuiting the two output nodes N1 and N2. In particular,
When the output of the rising edge detection circuit 131 becomes “H”, the bias circuit 133 outputs the NMOS transistor Q1
32 is turned off, the PMOS transistor Q134 is turned on, the short-circuit MOS transistor Q100 is turned on with the gate node CON1H connected to the output node N1, and the output nodes N1 and N2 are short-circuited. When the output of the edge detection circuit 131 becomes “L” after the elapse of the time T1, the NMO
The S transistor Q132 turns on, the PMOS transistor Q134 turns off, and the short-circuit MOS transistor Q1
00 is off, so the output nodes N1 and N2 are disconnected.

FIG. 21 shows the write operation timing in this embodiment in correspondence with FIG.
The pulse width of the above-described edge detection circuit 131 is from the timing t20 of the start of boosting to the timing t21 of the time T1, and during this time, the intermediate voltage VMWL is the write voltage V
Follow PGM. After the timing t21, the intermediate voltage V
The MWL is cut off from the write voltage VPGM, but continues to rise. Then, the limit signal VMWLLMT
At the timing t22 when the voltage becomes “H”, the intermediate voltage VMWL
Stops boosting. Further, at the timing t23 when the limit signal VPMLMT becomes “H”, the write voltage VPGM
Also stops boosting.

In the case of this embodiment, the write voltage VPGM
Immediately before the intermediate voltage VMWL following the voltage rises to the step-up completion voltage 10V, that is, so that the follow-up operation ends
It is desirable to set the time T1. As a result, the boosting of the intermediate voltage is completed before the boosting of the write voltage VPGM is completed, and the time (t22-t21) during which the write voltage VPGM and the intermediate voltage VMWL are boosted independently is very small, and therefore, there is no risk of erroneous writing. .

The present invention is not limited to the above embodiment. For example, in the embodiment, the NAND cell is constituted by eight memory cells. However, the present invention is similarly applied to a case where the NAND cell is constituted by another appropriate number such as 2, 4, 16, 32, 64. be able to. In the embodiment, the data writing has been described. However, the present invention can be applied to a data erasing operation using a high erasing voltage and a lower intermediate voltage. Further, in the embodiment, only the voltage in the positive direction is considered, but it is needless to say that the present invention can be applied to the case of using the boosted voltage in the negative direction. In addition, N shown in FIG.
EEPROM using OR type cell, DIN shown in FIG.
EEPROM using OR type cell, AND shown in FIG.
The present invention can be applied to an EEPROM using a pattern cell. Further, the present invention is not limited to the EEPROM, but can be applied to various semiconductor memories that require a plurality of boosted voltages higher than the power supply voltage.

[0061]

As described above, according to the present invention, the write voltage and the intermediate voltage, which are boosted voltages used for writing data, are made to follow the write voltage until the intermediate voltage reaches a certain level, thereby enabling the write operation. A semiconductor memory device that can prevent erroneous writing without increasing the time required for the semiconductor memory device can be obtained.

[Brief description of the drawings]

FIG. 1 shows a block configuration of an EEPROM according to an embodiment of the present invention.

FIG. 2 shows a plan view and an equivalent circuit diagram of the NAND cell of the embodiment.

FIG. 3 shows a cross-sectional structure of the NAND cell of the embodiment.

FIG. 4 shows an equivalent circuit of the memory cell array of the embodiment.

FIG. 5 shows a configuration of a write voltage generation circuit and an intermediate voltage generation circuit of FIG.

FIG. 6 shows a configuration of a VPGM booster circuit and a VMWL booster circuit of FIG.

FIG. 7 shows a drive clock used in the booster circuit of FIG.

FIG. 8 shows a configuration of the drive signal control circuit of FIG.

9 shows a configuration of a limit circuit 52 of FIG.

FIG. 10 shows a configuration of a limit circuit 54 of FIG.

11 shows a configuration of the output voltage control circuit 111 of FIG.

FIG. 12 is a timing chart for explaining a write operation of the embodiment.

FIG. 13 shows a modification of the short circuit 134 in FIG.

14 shows a write operation timing when the short circuit of FIG. 13A is used, corresponding to FIG.

FIG. 15 shows a configuration of a boosted voltage generation circuit unit according to an embodiment using two intermediate voltages.

FIG. 16 shows a circuit added to the clock generation circuit of FIG. 8 in the embodiment.

FIG. 17 shows a configuration of a limit circuit of the intermediate voltage VMBL in the embodiment.

FIG. 18 shows a configuration of an output control circuit 111b in FIG.

FIG. 19 shows a write operation timing of the embodiment in FIG.
Are shown in correspondence with.

FIG. 20 shows a configuration of an output control circuit in another embodiment.

FIG. 21 shows a write operation timing of the embodiment in FIG.
Are shown in correspondence with.

FIG. 22 shows an equivalent circuit of a NOR cell type EEPROM.

FIG. 23 shows an equivalent circuit of a DINOR cell type EEPROM.

FIG. 24 shows an equivalent circuit of an AND cell type EEPROM.

FIG. 25 shows a potential relationship when data is written in a conventional NAND cell type EEPROM.

FIG. 26 is a timing chart for explaining erroneous writing in a conventional NAND cell type EEPROM.

[Explanation of symbols]

101: memory cell array, 102: sense amplifier and data latch, 103: column decoder, 104: address buffer, 105: row decoder, 106: data input / output buffer, 107: substrate potential control circuit, 108: write voltage generation circuit, 109 ... Intermediate voltage generating circuit, 11
1. Output control circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazushige Kanda 580-1, Horikawa-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Inside the Toshiba Semiconductor System Technology Center (72) Inventor Ken Takeuchi Horikawa, Saiwai-ku, Kawasaki City, Kanagawa Prefecture F-term (reference) in Toshiba Corporation Semiconductor System Technology Center

Claims (7)

[Claims] 1. A memory cell array in which memory cells which are electrically rewritable and store data in a nonvolatile manner are arranged in a matrix, a sense amplifier and a data latch which sense read data of the memory cell array and latch write data. A decoder for selecting a memory cell of the memory cell array; a write voltage generating circuit for generating a write voltage higher than a power supply voltage, which is given when data is written to a selected memory cell of the memory cell array; and a non-selection of the memory cell array An intermediate voltage generation circuit that is provided at the time of writing data to the memory cell and generates an intermediate voltage that is higher than a power supply voltage and lower than the write voltage; a difference between an output voltage of the intermediate voltage generation circuit and an output voltage of the write voltage generation circuit. The output voltage of the intermediate voltage generation circuit is Limits to reach a constant level, the semiconductor memory device characterized by comprising after which, an output control circuit to continue to rise in the output voltage of the write voltage generation circuit in a state that the difference is not limited to the output voltage. A first booster circuit for boosting a power supply voltage to generate the write voltage; and detecting that an output voltage of the first booster circuit has reached a predetermined value. A first limit circuit for outputting a limit signal, the intermediate voltage generating circuit boosting a power supply voltage to generate the intermediate voltage, and an output of the second boost circuit. 2. The semiconductor memory device according to claim 1, further comprising a second limit circuit for detecting that the voltage has reached a predetermined value and outputting a limit signal. 3. The output control circuit includes: a short circuit for selectively shorting an output node of the write voltage generation circuit and an output node of the intermediate voltage generation circuit; An edge detection circuit that detects a rising edge of the boost control signal; and a bias circuit that controls the short-circuit to be turned on for a certain period of time by an output pulse of the edge detection circuit and controls the intermediate voltage to follow the write voltage. 3. The semiconductor memory device according to claim 2, wherein: 4. The output control circuit includes a flip-flop that is set by an output of the edge detection circuit and is reset by a limit signal obtained from the second limit circuit to control the bias circuit. The semiconductor memory device according to claim 3. 5. The time width of the output pulse of the edge detection circuit is set to the time from when the output of the first boosting circuit reaches the time immediately before the boosting start value of the intermediate voltage reaches the boosting time, and 4. The semiconductor memory device according to claim 3, wherein the circuit turns on the short circuit at the rise of the output pulse of the edge detection circuit and turns off the short circuit at the fall. 6. The memory cell array is configured by arranging NAND cells each formed by serially connecting a plurality of memory cells each having a floating gate and a control gate stacked on a substrate, and selecting one of the NAND cells. 2. The semiconductor memory device according to claim 1, comprising a data write mode in which said write voltage is applied to a control gate of a memory cell and said intermediate voltage is applied to a control gate of a non-selected memory cell in a NAND cell. 7. A memory cell array in which memory cells are arranged in a matrix, a sense amplifier and a data latch for sensing read data of the memory cell array and latching write data, a decoder for selecting a memory cell of the memory cell array, A first step of generating a first boosted voltage higher than a power supply voltage applied to a selected memory cell of the memory cell array;
And a second boosted voltage higher than a power supply voltage and lower than the first boosted voltage applied to unselected memory cells of the memory cell array.
A second boosted voltage generating circuit for generating a boosted voltage of the second boosted voltage generating circuit; and a difference between an output voltage of the second boosted voltage generating circuit and an output voltage of the first boosted voltage generating circuit. An output control circuit for limiting the output voltage to a predetermined level, and thereafter continuing to increase the output voltage of the first boosted voltage generation circuit in a state where the difference between the output voltages is not limited. Semiconductor storage device.