JP2000056993A - 外部記憶装置コントローラのキャッシュメモリ制御方法 - Google Patents

外部記憶装置コントローラのキャッシュメモリ制御方法

Info

Publication number
JP2000056993A
JP2000056993A JP10238027A JP23802798A JP2000056993A JP 2000056993 A JP2000056993 A JP 2000056993A JP 10238027 A JP10238027 A JP 10238027A JP 23802798 A JP23802798 A JP 23802798A JP 2000056993 A JP2000056993 A JP 2000056993A
Authority
JP
Japan
Prior art keywords
cache memory
segment
segments
external storage
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10238027A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000056993A5 (https=
Inventor
Takeshi Shikama
健 志鎌
Akira Kojima
昭 小島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10238027A priority Critical patent/JP2000056993A/ja
Publication of JP2000056993A publication Critical patent/JP2000056993A/ja
Publication of JP2000056993A5 publication Critical patent/JP2000056993A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP10238027A 1998-08-10 1998-08-10 外部記憶装置コントローラのキャッシュメモリ制御方法 Pending JP2000056993A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10238027A JP2000056993A (ja) 1998-08-10 1998-08-10 外部記憶装置コントローラのキャッシュメモリ制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10238027A JP2000056993A (ja) 1998-08-10 1998-08-10 外部記憶装置コントローラのキャッシュメモリ制御方法

Publications (2)

Publication Number Publication Date
JP2000056993A true JP2000056993A (ja) 2000-02-25
JP2000056993A5 JP2000056993A5 (https=) 2005-10-27

Family

ID=17024088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10238027A Pending JP2000056993A (ja) 1998-08-10 1998-08-10 外部記憶装置コントローラのキャッシュメモリ制御方法

Country Status (1)

Country Link
JP (1) JP2000056993A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004178571A (ja) * 2002-11-11 2004-06-24 Matsushita Electric Ind Co Ltd キャッシュ制御装置、キャッシュ制御方法、コンピュータシステム
US7539820B2 (en) 2004-04-20 2009-05-26 Hitachi Global Storage Technologies Netherlands B.V. Disk device and control method for cache

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004178571A (ja) * 2002-11-11 2004-06-24 Matsushita Electric Ind Co Ltd キャッシュ制御装置、キャッシュ制御方法、コンピュータシステム
US7539820B2 (en) 2004-04-20 2009-05-26 Hitachi Global Storage Technologies Netherlands B.V. Disk device and control method for cache

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