JP2000056972A - Vliw processor and its processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To dynamically change the number of instruction streams by a single processor. SOLUTION: Instruction pointers 120-123 which are installed in accordance with the respective instruction fields of 1VLIW and hold a memory address as a high-order bit and a field address in the memory address as a low-order bit, increment registers 180-183 which are installed for the pointers and add an increment value to the instruction pointers 120-123 whenever 1VLIW is held in instruction registers 140-143, a selection circuit 13 supplying the content of an instruction memory designated by the instruction pointers 120-123 to the instruction register corresponding to the content of the instruction pointer, a state update circuit 19 updating the content of the state register in response to a state shift instruction and an instruction stream termination instruction and a state/increment conversion circuit 21 converting the output of the state register 20 into the increment value and supplying it to the increment registers 180-183 are installed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VLIW processor which reads a very long instruction word (VLIW) comprising a plurality of instruction fields from an instruction memory and holds it in an instruction register, decodes the held very long instruction word, and executes the VLIW processor. Regarding the processing method.

[0002]

2. Description of the Related Art A VLIW processor is provided with a plurality of operation units and control units, and simultaneously executes a 64- to 512-bit VLIW composed of a plurality of instruction fields, thereby enabling high-speed processing. However, since the conventional VLIW processor has a single instruction stream, if resource control such as an input / output device is interrupted, necessary high-speed data processing must be temporarily interrupted.
Speeding up is hindered. Therefore, conventionally, such resource control has been performed using a plurality of separate controller processors.

[0003]

However, since it is necessary to construct a multiprocessor system having a plurality of microprocessors and communicate among the microprocessors, the cost increases and the control becomes complicated. Further, a resource control processor having an instruction set different from that of the VLIW processor cannot use the operating system for the VLIW processor, and therefore needs to have a plurality of OSs. In this case, for example, an O corresponding to a multimedia processor
There is no S, and the O
There is a problem that the affinity between S and the OS of the multimedia processor is poor, and a great deal of effort and time is required for adjusting the mutual operation.

An object of the present invention is to provide a VLIW processor capable of dynamically changing the number of instruction streams with a single processor and a processing method thereof in view of such a problem.

[0005]

According to the present invention, a very long instruction word consisting of n instruction fields is read from an instruction memory and held in an instruction register, and the held very long instruction word is decoded and executed. In a VLIW processor, an instruction pointer is provided for each of the n instruction fields, the instruction pointer holding memory address MA as an upper bit and field address FA in the memory address as a lower bit, and an instruction pointer for each of the instruction pointers. ,
i (1 ≦ i ≦ n) a value i is set for parallel processing of the instruction field, and an increment register for adding the value i to the instruction pointer each time the super instruction word is held in the instruction register; A selection circuit for supplying the contents of the instruction memory specified by the instruction pointer to the instruction register corresponding to the instruction pointer, and the number of the increment registers to which the value i is set is i.

According to the VLIW processor, the number of instruction streams can be dynamically changed in accordance with a set of contents of a plurality of increment registers, so that the following effects are obtained. (1) With a single processor, main processing can be performed at high speed, and resources such as input / output devices can be controlled. Therefore, there is no need to construct a multiprocessor system, and hardware and software configurations of the system are simplified. .

(2) Since the operating system for the VLIW processor can be used in resource control, the software configuration is simplified. (3) Since there is no need to adjust the mutual operation on the hardware, the design and development of the system are facilitated. (4) Conventionally, when interrupt processing was performed by a VLIW processor, the main processing had to be interrupted.
According to the IW processor, there is no need to interrupt the main processing, so that stable real-time processing can be performed.

(5) In a VLIW processor, a NOP instruction is added to an instruction group associated with processing data to
It is necessary to increase the number of W. In such a case, by performing other processing in parallel with the multi-instruction stream of the present invention, processing efficiency is improved. The present embodiment having the above effects greatly contributes to the cost reduction, size reduction, and short delivery time of the system.

In the VLIW processor according to the present invention, the VLIW processor may further include an increment update circuit for updating the contents of the increment register in response to the state transition instruction. According to the VLIW processor, a new instruction stream can be easily added during execution, similar to the conventional execution of a subroutine or activation of another processor.

According to a third aspect of the present invention, the VLIW processor according to the first aspect further includes an incremental update circuit for updating the contents of the increment register in response to an external instruction stream addition request. According to this VLIW processor, a new instruction stream can be easily added in hardware, similar to conventional interrupt processing or other processor activation.

According to a fourth aspect of the present invention, in the VLIW processor according to the second or third aspect, the increment updating circuit updates a status register updated in response to the content of the status transition instruction and an output of the status register to an increment value. And a state / increment conversion circuit for converting and supplying the result to the increment register.

According to the VLIW processor, the number of instruction streams can be easily changed by increasing or decreasing the output value of the status register. In the VLIW processor according to a fifth aspect, in the fourth aspect, the incremental update circuit is configured to, when the content of the status register is changed and a new instruction stream is added, terminate any one of the instruction streams. After detecting that the value of the instruction pointer has reached a predetermined value, the apparatus further includes a state update circuit that updates the contents of the state register to increase the width of one or more instruction streams.

According to the VLIW processor, the number of addresses to be specified for the instruction memory can be reduced to speed up the operation. In the VLIW processor according to a sixth aspect, in the fifth aspect, the state updating circuit updates the contents of the state register so that the width of the predetermined instruction stream increases.

According to the VLIW processor, the main stream can be processed at a higher speed by creating a program so that the predetermined instruction stream becomes the main stream. The VLIW of claim 7
In the processor, in claim 5, the state update circuit determines that the instruction stream has ended based on decoding of the instruction stream end instruction.

According to this VLIW processor, the process of increasing the instruction stream width is simplified. 9. The processing method of a VLIW processor according to claim 8, wherein a very long instruction word composed of n instruction fields is read from an instruction memory and held in an instruction register, and the held very long instruction word is decoded and executed.
An instruction pointer having for each of the n instruction fields, holding the memory address MA as the upper bits and holding the field address FA in the memory address as the lower bits, and for each of the instruction pointers, Each time a word is held in the instruction register, an increment register for adding a value i (1 ≦ i ≦ n) to the instruction pointer is stored in the V.
By providing the value i in the i number of increment registers and providing the contents of the instruction memory specified by the instruction pointer to the instruction register corresponding to the instruction pointer, n The following instruction streams are processed in parallel.

According to a ninth aspect of the present invention, the parallel number ratio of the instruction stream is changed by updating the contents of the increment register in response to the state transition instruction. According to a tenth aspect of the present invention, in the ninth aspect, when any of the instruction streams is terminated after a new instruction stream is added, the instruction pointer waits until the value of the instruction pointer becomes a predetermined value. Thus, by updating the contents of the increment register, the number of one parallel of the instruction stream is increased.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of the VLIW processor. An instruction memory 10 and a data memory 11 are provided for high-speed processing, and can be accessed by independent buses. Instruction memory 10 and data memory 1
1 is a cache memory, for example.

The instruction memory 10 includes an instruction pointer processing unit 12
And the contents of the instruction memory 10 are read out.
And the ready signal RDY supplied from the selection circuit 13 to the control circuit 15 is activated. The control circuit 15
In response to this, a pulse of the latch signal LCH is supplied to the instruction registers 140 to 143, and the instruction registers 140 to 143 are supplied.
3 holds VLIW. Instruction registers 140-14
3 are respectively decoded by the instruction decoders 160 to 163, and based on the results, the arithmetic circuits 170
To 173 are controlled, and the address information of the operands of the instruction registers 140 to 143 are stored in the instruction decoders 160 to 163.
Is supplied to the control circuit 15 via the The control circuit 15 includes a control unit corresponding to each of the arithmetic circuits 170 to 173. When the calculation of the real address of the operand is necessary, the control circuit 15 causes the arithmetic circuits 170 to 173 to perform the calculation, and stores the address in the data memory 11. To supply. Arithmetic circuit 170
173 are connected to the data memory 11 via a data bus, and exchange data with the data memory 11 on the operation target and the operation result.

Such processing is performed in a pipeline. The contents held in the instruction registers 140 to 143 are represented as # 0 to # 3, respectively. In the related art, since the stream is a 4-parallel single instruction stream, the data flow of # 0 to # 3 is limited to that shown in FIG. On the other hand, in the present embodiment, in addition to the 4-parallel single instruction stream, a 1: 3 multi-instruction stream as shown in FIG. 2B, a 2: 2 multi-instruction stream as shown in FIG. A 1: 1: 2 multi-instruction stream as shown in FIG. 2 (D) and a 1: 1: 2 as shown in FIG. 2 (E).
A 1: 1 multi-instruction stream can be executed, and the parallel state can be dynamically switched. FIG.
The parallel states of (A) to (E) are referred to as states 0 to 4, respectively.

FIG. 3 shows a multi-instruction stream in which such a state is dynamically switched. The flow of the process is in the direction of the arrow shown. FIG. 3 shows one main instruction stream and first to third sub-instruction streams. The line width indicates the number of parallel lines, and the wider the line width, the higher the speed of processing. The first to third sub-instruction streams are similar to the conventional branch processing such as interrupt processing and subroutines. However, instead of branching to interrupt processing with one instruction stream, a new instruction stream is added and execution is performed. The instruction stream in the middle can continue to be executed, so that there is no need to perform the save processing and the return processing performed in the interrupt processing.

Returning to FIG. 1, in order to make the number of instruction streams variable, the instruction pointer processing unit 12
The instruction pointers 120 to
123 is provided. As shown in FIG. 4A, the contents of the instruction pointers 120 to 123 each include an upper bit memory address MA and a lower bit field address FA. In the present embodiment, since 1 VLIW is a 4-instruction field, the field address FA is 2 bits.

The instruction memory 10 is specified by a memory address MA, and the data of each memory address MA is added to the data of FIG.
The field address FA is allocated, for example, every 32 bits as shown in FIG. A set of the memory address MA and the field address FA is represented by (MA, FA). For example, 1
If the VLWI is 128 bits and the instruction memory 10 has four 32-bit instruction memories, the field addresses correspond to the physical instruction memories, but such correspondence is not necessary.

In a normal stream without branches,
Every time one VLIW is held in the instruction registers 140 to 143, the output values of the increment registers 180 to 183 are added to the contents of the instruction pointers 120 to 123, respectively. In the case of a branch instruction, the branch destination address is supplied to the corresponding instruction pointer via the instruction decoder and control circuit 15 as in the conventional case, and the content of the instruction pointer is updated.

Similar to conventional subroutine execution or other processor invocation, the instruction set includes a state transition instruction to allow a new instruction stream to be added during execution. This state transition instruction includes a new instruction stream start address (MA, FA). When this instruction is decoded by the instruction decoder, on the one hand, the new instruction stream head address (MA, FA) is supplied to the instruction pointer processing unit 12 via the control circuit 15, and on the other hand, the control circuit 15 and the state update circuit 19 Is added to the content S of the status register 20 if S = 1, and 1 if S ≠ 1. In this case, the state update circuit 19 may be a simple signal passage path.

For the sake of simplicity, the instruction pointer processing unit 12 reduces, for example, the width of the instruction stream having a width (number of parallels) of 2 or more before the state transition and the width of the leftmost instruction stream in FIG. Allocate a new instruction stream.
More specifically, if the state S before the state transition is S = 0, 1, 2, or 3, the instruction pointer processing unit 12 assigns a new instruction pointer 123, 122, 123, or 121 from the control circuit 15 to the instruction pointer 123, 122, 123, or 121, respectively. Instruction stream start address (MA,
FA).

In this way, the state transition processing is simplified. As an exception, a state transition instruction is defined so that transition from state 0 to state 2 is possible. In this case, for example, the new instruction stream start address is set in the instruction pointers 122 and 123. The reason that the state is not designated by the state transition instruction is that a hardware instruction stream addition request ISRQ described later is used.
This makes it impossible to know the state of the instruction stream currently being executed at the program creation stage, and to simplify the configuration. It should be noted that the instruction stream addition request ISRQ like hardware such as an interrupt mask is prohibited or the content S of the status register 20 is read by a program to check the instruction stream state, and the state S is designated by the state transition instruction. You may.

The status / increment conversion circuit 21 converts the output S of the status register 20 into the following increment values ΔPC0 to ΔPC3 for the increment registers 180 to 183. S = 0: ΔPC3 = 4, ΔPC2 = 4, ΔPC1 =
4, ΔPC0 = 4 S = 1: ΔPC3 = 1, ΔPC2 = 3, ΔPC1 =
3, ΔPC0 = 3 S = 2: ΔPC3 = 2, ΔPC2 = 2, ΔPC1 =
2, ΔPC0 = 2 S = 3: ΔPC3 = 1, ΔPC2 = 1, ΔPC1 =
2, ΔPC0 = 2 S = 4: ΔPC3 = 1, ΔPC2 = 1, ΔPC1 =
1, ΔPC0 = 1 The above-mentioned state update circuit 19, state register 20, and state / increment conversion circuit 21 constitute an incremental update circuit 22.

The control circuit 15 responds to an external instruction stream addition request ISRQ so that a new instruction stream can be added in hardware, similar to the conventional interrupt processing or other processor activation. On the other hand, if S <4, in response to the request, a predetermined address (M
A, FA) is supplied to the instruction pointer processing unit 12, and 2 is added to the content of the status register 20 via the status update circuit 19 if S = 1, and 1 if S ≠ 1. The instruction pointer processing unit 12 assigns the address (MA, F) to the selected instruction pointer in the same manner as in the case of the state transition instruction.
A) is held.

The instruction stream addition request ISRQ is similar to the conventional interrupt request, except that the number of instruction streams is increased by one so that the instruction stream being executed can continue execution.
Therefore, it is not necessary to perform the saving process and the returning process performed in the interrupt process, and this is also advantageous. FIG. 5 shows the state 0
From the 4-parallel single instruction stream described above to the state 2 instruction stream or the instruction stream addition request ISRQ. In FIG. 5, the flow of the values # 3 to # 0 of the instruction registers 143 to 140 is shown by the flow of the corresponding addresses (MA, FA) in the instruction memory 10 where the values are stored.

First, the content of the status register 20 is 0, and the increments ΔPC3 to ΔPC0 are all 4. The instruction is read from the address 0 of the instruction memory 10 and the contents of the addresses (0, 3) to (0, 0) are held by the selection circuit 13 in the instruction registers 143 to 140, respectively. In this case, since there is one address, the selection circuit 13 functions simply as a wiring.

Next, the instruction is read from the address 1 of the instruction memory 10, and the address (1,
3) to (1, 0) are stored in the instruction register 143, respectively.
~ 140. PC3 = (100,0) in response to a state transition instruction or instruction stream addition request ISRQ
In parallel with this, the instruction pointer values PC2 to PC0
Are (2, 2) to (2, 0), respectively. The content of the status register 20 changes to 2, which causes the increment ΔPC3 ~
PC0 changes to 1, 3, 3 and 3, respectively. Instructions are read from the addresses 100 and 2 of the instruction memory 10, and the contents of the addresses (100, 0) and (2, 2) to (2, 0) are held by the selection circuit 13 in the instruction registers 143 to 140, respectively. .

Here, when the instruction memory 10 is a cache memory, since the storage capacity is relatively small and the degree of integration of the processor is further improved, a plurality of instruction memories having the same contents and independent buses are provided. By specifying a plurality of addresses, the time required to read 1 VLIW from the instruction memory may be reduced. Further, the selection circuit 13 may be provided with a buffer register and a shift register capable of shifting in instruction field units, so that the contents already read from the instruction memory 10 and held in the buffer register are taken out from the buffer register. Good.

The values of the increments ΔPC3 to PC0 are added to the instruction pointer values PC3 to PC0, respectively.
0 changes as follows. PC3: (100, 1) ← (100, 0) +1 PC2: (3, 1) ← (2, 2) +3 PC1: (3, 0) ← (2, 1) +3 PC0: (2, 3) ← (2, 0) +3 The instruction is read from addresses 100, 3 and 2 of the instruction memory 10, and the address (100,
The contents of 1), (3,1), (3,0) and (2,3) are held in the instruction registers 143 to 140, respectively.

In the case of the instruction stream addition request ISRQ,
In the program executed in response to this request, the status flag indicating the cause of the instruction stream addition request similar to the interrupt cause flag is checked, and the cause of the request, for example, the type of the input / output device of the request source is checked. Jump to the service routine accordingly. During this process, the contents of the status register 20 may be checked, and if S = 1, for example, the status may be shifted to the status 2 by a status shift command.

FIG. 6 illustrates the transition from a four parallel single instruction stream in state 0 to a 1: 3 multi-instruction stream in state two. FIG. 7 illustrates the transition from a 1: 3 multi-instruction stream in state 1 to a 1: 1: 2 multi-instruction stream in state 3. FIG. 8 shows the transition from the state 3: 1: 1: 2 multi-instruction stream to the state 4 1: 1: 1: 1 multi-instruction stream.

7 and 8, as described above,
An instruction stream having a width of 2 or more before the state transition and the width of the leftmost instruction stream in the drawing is reduced by one, and a new instruction stream is allocated to this. After the new instruction stream is added as described above, if any of the instruction streams ends, the parallel number becomes smaller than four. Therefore, by increasing the instruction stream width and making the parallel number four, It is preferable to increase the processing speed.

Therefore, an instruction stream end instruction is included in the instruction set so that the instruction stream width can be increased without changing the number of instruction streams. When this instruction is decoded by the instruction decoder, on the one hand, the identification code of the decoded instruction decoder is supplied to the instruction pointer processing unit 12 via the control circuit 15, and on the other hand, in response to the signal from the control circuit 15, The state updating circuit 19 subtracts 2 from the contents of the state register 20 if S = 2, and subtracts 1 if S ≠ 2.

There is an option as to which instruction stream is widened. In designing a VLIW processor, for example, one of the following rules is selected. (1) To increase the width of the main instruction stream, for example, FIG.
Widen the rightmost instruction stream of (2) In order to simplify the rule, the width of the instruction stream adjacent to the completed instruction stream, for example, the instruction stream on the right side of FIG.

(3) The instruction stream end instruction includes information on which instruction stream is to be widened, and the instruction stream is determined based on the information. (4) having a register indicating the main instruction stream,
Set the contents of this register in advance in the program,
Look at its contents to identify the main instruction stream and expand its width.

The instruction pointer processing unit 12 includes a control circuit 15
The contents of the instruction pointers 120 to 123 are changed so that the width of the predetermined instruction stream is widened based on the identification code and the selected rule. This change includes:
It may involve moving the instruction stream as described below. The timing of stream width expansion is determined by the state update circuit 19 as follows in order to minimize the number of instruction memory designated addresses corresponding to 1 VLIW after expansion.

FIGS. 9 and 10 show the case of rule (1) or (2), FIG. 11 shows the case of rule (2), and FIG. 12 shows the case of rule (1). 9 to 12 can be said to show an example of the rule (3) or (4). FIG. 9 illustrates the transition from a 1: 3 multi-instruction stream in state 1 to a 4-parallel single instruction stream in state 0.

(160, 1) in the column of # 3 in FIG. 9 is the address of the instruction stream end instruction. When this instruction is decoded by the instruction decoder 163, the control circuit 15
On the other hand, the instruction decoder 1
63, while the state update circuit 1
9 is supplied with a stream width expansion command. When the state S is changed in the next 1VWL, the number of addresses to be specified for the instruction memory 10 becomes two.
The state update circuit 19, on the other hand,
Until the field address FA of the instruction pointer 120 becomes 0, the content of the instruction register 143 is changed to a NOP instruction (no operation instruction) or the instruction decoder 163 and the arithmetic circuit 173 are stopped, while updating of the status register 20 is prohibited. And the instruction pointer processing unit 12 is prohibited from updating the instruction pointer 123.

When the field address FA of the instruction pointer 120 becomes 0, the prohibition is released, and the instruction pointer processing section 12 copies the contents of the instruction pointer 122 to the instruction pointer 123, and the content of the instruction pointer 123 becomes 1
Is added, and PC3 = (23, 3). In parallel with this, the instruction pointer values PC2 to PC0 are respectively (2, 3).
3,2) to (23,0). The content S of the status register 20 is updated from 1 to 0, whereby the increment ΔPC3 to
PC0 changes to 4 in each case. The instruction is read from the address 23 of the instruction memory 10 and held in the instruction registers 143 to 140 via the selection circuit 13. Increment ΔPC3
To PC0 are instruction pointer values PC3 to PC0, respectively.
And PC3 to PC0 become (24,3) to (24,
0).

FIG. 10 shows the transition from the 2: 2 multi-instruction stream in state 2 to the 4-parallel single instruction stream in state 0. (160, 1) in the column of # 3 is the address of the instruction stream end instruction. Note that (160, 0)
Is the address of the instruction stream end instruction (160, 1)
May be the address of a meaningless instruction. FIG.
It shows the transition from the 1: 3 multi-instruction stream of state 3 to the 2: 2 multi-instruction stream of state 2.

(260, 3) in the column of # 3 is the address of the instruction stream end instruction. Next, when the instruction stream width of # 2 expands, (161, 0)
The memory address to be designated as (160, 3) is 2
One. Therefore, until the field address FA of the instruction pointer 122 corresponding to the rightmost side of the instruction stream whose width is to be expanded becomes 0, that is, until the field address FA becomes 2 or 0, the status registers 20 and Update of the instruction pointer 122 is prohibited. In order to simplify the configuration, “2 or 0” is replaced with “0”.
There is no big difference.

FIG. 12 shows the transition from the state 4 1: 1: 1: 1 multi-instruction stream to the state 3 1: 1: 2 multi-instruction stream. (350, 3) in the column of # 3 is
Instruction stream end instruction address. Similarly to the above, updating of the status register 20 and the instruction pointer 121 is prohibited until the field address FA of the instruction pointer 120 corresponding to the rightmost side of the instruction stream whose width is to be enlarged becomes 0. When the instruction pointer 121 is updated to increase the instruction stream width of # 0, that is, when the contents of the instruction pointer 120 are copied to the instruction pointer 121 and added to the contents of the instruction pointer 121, the original #
1 is lost, the instruction pointer 12
This change is made after the content of 1 is transferred to the instruction pointer 123 corresponding to the end instruction stream. The contents of the instruction pointers 121 and 122 are stored in the instruction pointer 1 respectively.
This update may be performed after shifting to 22 and 123.

According to the present embodiment, the number of instruction streams can be dynamically changed, so that the following effects can be obtained. (1) With a single processor, main processing can be performed at high speed, and resources such as input / output devices can be controlled. Therefore, there is no need to construct a multiprocessor system, and hardware and software configurations of the system are simplified. .

(2) Since the operating system for the VLIW processor can be used in resource control, the software configuration is simplified. (3) Since there is no need to adjust the mutual operation on the hardware, the design and development of the system are facilitated. (4) Conventionally, when interrupt processing was performed by the VLIW processor, the main processing had to be interrupted. However, according to the VLIW processor of the present embodiment, there is no need to interrupt the main processing. It can be carried out.

(5) In the VLIW processor, for example, ADD A, B SUB A, C MULT A,
When the processing result is used in the next step as in DINCA, 1
The processing cannot be performed by VLIW. In this case, it is necessary to add a NOP instruction by a programmer or a compiler to make the following 4 VLIW.

ADD A, B NOP NOP NOP SUB A, C NOP NOP NOP MULT A, D NOP NOP NOP INC A NOP NOP NOP In such a program with a relatively large amount of waste, a multi-instruction stream is used as in this embodiment. By performing other processing in parallel, the processing efficiency is improved.

The present embodiment having the above effects is
It greatly contributes to the cost reduction, miniaturization and short delivery time of the system.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a VLIW processor according to an embodiment of the present invention.

FIGS. 2A to 2D are explanatory diagrams showing instruction streams in states 0 to 4, respectively.

FIG. 3 is a diagram showing a change in the number of multi-instruction streams.

FIG. 4A is a diagram showing a format of an instruction pointer, and FIG. 4B is a diagram showing a relationship between a memory address and a field address in an instruction memory.

FIG. 5 is an explanatory diagram showing a transition from a 4-parallel single instruction stream in state 0 to a 1: 3 multi-instruction stream in state 1;

FIG. 6 is an explanatory diagram showing a transition from a 4-parallel single instruction stream in state 0 to a 2: 2 multi-instruction stream in state 2;

FIG. 7 is an explanatory diagram showing a transition from a 1: 3 instruction stream in state 1 to a 1: 1: 2 multi-instruction stream in state 3;

FIG. 8 is an explanatory diagram showing a transition from a 1: 1: 2 multi-instruction stream in state 3 to a 1: 1: 1: 1 multi-instruction stream in state 4;

FIG. 9 is an explanatory diagram showing a transition from a 1: 3 multi-instruction stream in state 1 to a 4-parallel single instruction stream in state 0;

FIG. 10 is an explanatory diagram showing a transition from a 2: 2 multi-instruction stream in state 2 to a 4-parallel single instruction stream in state 0;

FIG. 11 is an explanatory diagram showing transition from a 1: 3 multi instruction stream in state 3 to a 2: 2 multi instruction stream in state 2;

FIG. 12 is an explanatory diagram showing a transition from a 1: 1: 1: 1 multi-instruction stream in state 4 to a 1: 1: 2 multi-instruction stream in state 3;

[Explanation of symbols]

 Reference Signs List 10 instruction memory 11 data memory 12 instruction pointer processing unit 120 to 123 instruction pointer 13 selection circuit 140 to 143 instruction register 15 control circuit 160 to 163 instruction decoder 170 to 173 arithmetic circuit 180 to 183 increment register 19 state update circuit 20 state register 21 State / Increment conversion circuit 22 Increment update circuit ISRQ Instruction stream addition request RDY Ready signal LCH Latch signal ΔPC0 to ΔPC3 Increment PC0 to PC3 Instruction pointer value S state

Claims (10)

[Claims] 1. A VLIW processor for reading an ultra-long instruction word consisting of n instruction fields from an instruction memory, holding the instruction in an instruction register, and decoding and executing the held ultra-long instruction word. An instruction pointer for holding the memory address MA as the upper bit and the field address FA in the memory address as the lower bit; and an instruction pointer provided for each of the instruction pointers. An increment register for setting and adding the value i to the instruction pointer each time the super instruction word is held in the instruction register, and a content of the instruction memory designated by the instruction pointer corresponding to the instruction pointer. A selection circuit for supplying the instruction register; and i being a number of the increment registers in which the value i is set. VLIW processor according to claim. 2. The VLIW processor according to claim 1, further comprising an increment update circuit for updating the contents of said increment register in response to a state transition instruction. 3. The VLI according to claim 1, further comprising an increment update circuit for updating the contents of said increment register in response to an external instruction stream addition request.
W processor. 4. The status update circuit according to claim 1, wherein said status update command is a status register which is updated in response to the content of said status transition instruction. A VLI according to claim 2 or 3, comprising:
W processor. 5. The method according to claim 1, wherein when the content of the status register is changed and a new instruction stream is added, when one of the instruction streams ends, the value of the instruction pointer becomes a predetermined value. 5. The VLIW processor according to claim 4, further comprising a status update circuit for updating the content of said status register in order to increase the width of one or more instruction streams after detecting the fact. 6. The VLI according to claim 5, wherein said status update circuit updates the contents of said status register so that the width of the predetermined instruction stream increases.
W processor. 7. The VLIW processor according to claim 5, wherein said state update circuit determines that said instruction stream has ended based on decoding of an instruction stream end instruction. 8. A processing method of a VLIW processor for reading an ultra-long instruction word consisting of n instruction fields from an instruction memory, storing the instruction in an instruction register, and decoding and executing the stored ultra-long instruction word, wherein each of the n instruction fields And an instruction pointer holding the memory address MA as the upper bit and the field address FA in the memory address as the lower bit, and holding each of the instruction pointers and holding the super instruction word in the instruction register The VLIW processor is provided with an increment register for adding a value i to the instruction pointer each time the instruction memory is operated, the value i is set in the i number of the increment registers, and the instruction memory specified by the instruction pointer is set. Is supplied to the instruction register corresponding to the instruction pointer, thereby processing n or less instruction streams in parallel. Method of processing VLIW processor, wherein and. 9. The VLI according to claim 8, wherein the parallel number ratio of the instruction stream is changed by updating the contents of the increment register in response to a state transition instruction.
Processing method of W processor. 10. When one of the instruction streams is terminated after a new instruction stream is added, the content of the increment register is updated after the value of the instruction pointer reaches a predetermined value. Increasing the parallel number of one of said instruction streams by:
A processing method of the VLIW processor described in the above.