JP2000050100A - Vertical deflection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a vertical deflection circuit for reducing the power consumption. SOLUTION: This vertical deflection circuit prepares the vertical sawtooth wave signals of a prescribed amplitude synchronized with synchronizing signals by a vertical sawtooth wave generation circuit 5 and varies the inclination of the scanning period and the fly-back period of the vertical sawtooth wave signals outputted from the vertical sawtooth wave generation circuit 5. Also, the amplitude of the vertical sawtooth wave signals outputted from the vertical sawtooth wave generation circuit 5 is controlled, the phase amount of the vertical sawtooth wave signals outputted from the vertical sawtooth wave generation circuit 5 is varied, the vertical sawtooth wave signals outputted from a phase control circuit 6 are amplified by an output circuit 2 and a deflection current is made to flow to a deflection yoke 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a vertical deflection circuit, and more particularly, to a vertical deflection circuit of a CRT display.

[0002]

2. Description of the Related Art As shown in FIG. 6, a conventional vertical deflection circuit generates a vertical sawtooth signal having an amplitude that varies with a DC voltage controlled by screen amplitude information by using a vertical synchronizing signal as a trigger. And a DC shift circuit 104 that varies a vertical sawtooth signal output from the vertical sawtooth generation circuit 105 with a DC voltage controlled by screen position information.
And an output circuit 1 that amplifies the vertical sawtooth signal output from the DC shift circuit 104 and outputs the amplified signal to the deflection yoke 101.
02, and a pump-up circuit 103 for increasing the power supply voltage of the output circuit 102 to shorten the retrace period.

[0003] The relationship between the screen amplitude and screen position of this conventional vertical deflection circuit and the vertical deflection current is as shown in FIG. In the area, power is wasted, and as shown in FIG. 7B, a larger deflection current flows to expand the screen. As shown in FIG. 7D, in order to move the screen, it is necessary to increase the dynamic range of the power supply voltage. Therefore, increasing the power supply voltage increases power consumption.

[0004]

In this conventional vertical deflection circuit, the deflection current in the non-display area is large, so that power must be wasted and the blanking period must be shortened. In addition, there was a problem that the power supply voltage had to be increased.

[0005]

In order to solve the above-mentioned problems, a vertical deflection circuit according to the present invention comprises an amplitude suppressed by a predetermined amplitude suppression voltage, and a display period and a blanking period of an input video signal. And a vertical sawtooth wave generating circuit for generating a vertical sawtooth signal synchronized with a vertical synchronizing signal of the input video signal, and a display period and a scanning period of the input video signal coincide with each other. A phase control circuit for controlling the phase of the vertical sawtooth signal with a phase control voltage, and an output circuit for amplifying the vertical sawtooth signal whose phase has been controlled by the phase control circuit and outputting the amplified signal to a deflection yoke. Features.

[0006]

Next, a vertical deflection circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a vertical deflection circuit according to an embodiment of the present invention.

FIG. 2 shows a vertical deflection current waveform diagram and a screen diagram of the vertical deflection circuit according to one embodiment of the present invention.

FIG. 3 is a vertical deflection current waveform diagram of the vertical deflection circuit according to one embodiment of the present invention.

FIG. 4 is a block diagram of the vertical deflection circuit according to one embodiment of the present invention, from which the amplitude control voltage has been removed.

FIG. 5 is a block diagram of the vertical deflection circuit according to one embodiment of the present invention, from which the pump-up circuit is omitted.

As shown in FIG. 1, a vertical deflection circuit according to an embodiment of the present invention includes an amplitude suppressed by a preset amplitude suppression voltage and a duty cycle between a display period and a blanking period of an input video signal. A vertical sawtooth wave generating circuit 5 for generating a vertical sawtooth signal synchronized with a vertical synchronizing signal of the input video signal, and a vertical sawtooth signal for adjusting the display period and the scanning period of the input video signal to coincide with each other. A phase control circuit 6 for controlling the phase with a phase control voltage; an output circuit 2 for amplifying the vertical sawtooth signal phase-controlled by the phase control circuit 6 and outputting the amplified signal to the deflection yoke 1; And a pump-up circuit 3 for increasing the pressure.

Next, the operation of the vertical deflection circuit according to one embodiment of the present invention will be described with reference to the drawings.

The operation of the vertical deflection circuit according to one embodiment of the present invention is as follows. When an image is displayed in a full display area as shown in FIGS. As described above, since only the deflection current flows to deflect the display area, power consumption is reduced in the non-display area without wasting power, and when the screen is widened, as shown in FIG. Since only the deflection current for deflecting the display area is changed by changing only the inclination of the deflection current, the power consumption is reduced in the non-display area without wasting power.

When the screen position is moved downward, FIG.
As shown in D, since only the deflection current flows to change the phase of the deflection current and deflect the display area, the power consumption is reduced without wasting power in the non-display area, and the flyback period is reduced. By reducing the vertical sawtooth signal to zero, the power consumption is further reduced as shown in FIG.

Further, by calculating the DC voltage of the display area information from the sensitivity of the deflection yoke 1, as shown in FIG. 4, the amplitude control voltage can be eliminated, and by extending the retrace period, as shown in FIG. As shown, the pump-up circuit can be eliminated.

[0017]

As described above, according to the vertical deflection circuit of the present invention, the deflection current in the non-display area is reduced and the deflection current is fed back using the period of the non-display area. Has the effect of reducing the power consumption by flowing only the deflection current necessary for the power supply.

[Brief description of the drawings]

FIG. 1 is a block diagram of a vertical deflection circuit according to an embodiment of the present invention.

FIG. 2 is a vertical deflection current waveform diagram and a screen diagram of a vertical deflection circuit according to an embodiment of the present invention.

FIG. 3 is a vertical deflection current waveform diagram of the vertical deflection circuit according to one embodiment of the present invention.

FIG. 4 is a block diagram of the vertical deflection circuit according to one embodiment of the present invention, from which an amplitude control voltage is deleted.

FIG. 5 is a block diagram of the vertical deflection circuit according to the embodiment of the present invention, from which a pump-up circuit is omitted.

FIG. 6 is a block diagram of a conventional vertical deflection circuit.

FIG. 7 is a vertical deflection current waveform diagram and a screen diagram of a conventional vertical deflection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Deflection yoke 2 Output circuit 3 Output circuit (pump-up circuit) 5 Vertical sawtooth wave generation circuit 6 Phase control circuit

Claims (1)

[Claims] 1. A vertical synchronizing signal which is formed by an amplitude suppressed by a preset amplitude suppression voltage and a duty ratio between a display period and a blanking period of an input video signal and synchronized with a vertical synchronizing signal of the input video signal. A vertical sawtooth wave generating circuit for generating a sawtooth signal; a phase control circuit for controlling the phase of the vertical sawtooth signal with a phase control voltage so that the display period and the scanning period of the input video signal coincide; And an output circuit for amplifying the vertical sawtooth signal phase-controlled by the circuit and outputting the amplified signal to a deflection yoke.