JP2000049612A - D/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evade nonlinearity by the capacity difference of both capacity elements, to secure the monotony of conversion characteristics and to reduce differentiation errors at the center of a conversion range by switching and altering the two capacity elements for redistribution corresponding to an input signal value. SOLUTION: A first capacity element C1 is charged in the case that the most significant bit of digital input signals Din is 0, a second capacity element C2 is charged successively corresponding to a bit value from a least significant bit through S1 in the case that it is 1, they are redistributed respectively to the C2 and C1 and a voltage corresponding to the total sum of 1/2 power series is charged. As for the binary signals of the most significant bit, they are extracted by a changeover control circuit 3, switch circuits S3 and S4 are controlled in response to the signals and the C1 and the C2 are switched and altered. In such a manner, by altering them at a simultaneous carry or borrow point where the most significant bit is inverted, the end point and origin point of a characteristic curve part are made continuous, nonlinear characteristics by the capacity difference of the C1 and the C2 are improved and the characteristic curve monotonous as the whole is synthesized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effective when applied to a D / A converter and further to a charge redistribution type D / A converter, and is used, for example, in a digital servo system. It is about effective technology.

[0002]

2. Description of the Related Art As a D / A converter, a segment type as described in, for example, US Pat. No. 4,176,344 is well known. Since a high-precision constant current source weighted to correspond to each bit position of a bit digital input signal is required for the number of bits of the digital input signal, there is a problem that the circuit becomes complicated and large-scale. Therefore, when an attempt is made to construct a digital servo system using this type of D / A converter, for example, there arises a problem that the D / A converter increases the cost and power consumption of the system.

Accordingly, the present inventor has proposed a charge redistribution type D / A converter which can be constituted by a relatively simple and small-scale circuit as a D / A converter which can be easily used for the above-mentioned applications. Vessel was examined.

FIG. 10 shows a schematic configuration of a charge redistribution D / A converter studied by the present inventors.

The D / A converter shown in FIG. 1 includes a first capacitance element C1, a second capacitance element C2, and a first switch circuit S.
1, the second switch circuit S2, the sequence control circuit 1,
It is configured by the voltage sampling circuit 2 and converts a digital input signal Din composed of a binary code string of a plurality of bits into an analog output voltage VA and outputs it.

In FIG. 1, first and second capacitance elements C1 and C2 are formed to have the same capacitance (C1 = C2).

The first switch circuit S1 charges the first capacitive element C1 to a high reference potential (Vcc) or a low reference potential (0V) according to the bit value of the digital input signal Din. That is, when the bit value is “1”, C1 is set to Vc
Charge to c, and if "0", charge (discharge) C1 to 0V
I do.

The second switch circuit S2 is configured by connecting the first capacitive element C1 charged to Vcc or 0V by the first switch circuit S1 to the second capacitive element in parallel, so that both capacitive elements C1 and C2 are connected. Are redistributed at the same potential. At this time, if C1 = C2, the charges redistributed to C1 and C2 are equal to each other. That is, C1, C
The total charge of 2 is equally divided into C1 and C2 by 1/2.

[0009] The sequence control circuit 1 determines whether C1
And a redistribution of the total charge by S2 is sequentially performed one bit at a time in order from the lower bit to the upper bit of the digital input signal Din.

Thus, the values of the digital input signal Din (from 0 to 25 in decimal in the case of 8 bits) are stored in C1 and C2 at the stage when the above-mentioned sequence is completed.
The voltage VA corresponding to 5) is charged.

That is, if C1 = C2, each bit value (b0, b1, b1) of the n-bit digital input signal Din
b2,..., b (n-1)), VA = Vcc ×
(B0 × 2 ⁻¹ + b1 × 2 ⁻² + b2 × 2 ⁻³ +... + B (n
-1) × 2 ^-n ) are voltages VA and C2
Will be charged.

FIG. 11 is a circuit diagram for each state showing an operation example of the above-mentioned D / A converter.

FIG. 1A shows an initialization operation performed every time the digital input signal Din is updated. In this initialization operation, C1 and C2 are both set to the row reference potential (0 V).
To make each charge zero once.

FIG. 1B shows the operation when the j-th bit value bj of the digital input signal Din is "1" (b).
j = “1”). In this case, S1 charges C1 to Vcc. Thereafter, S1 is at an intermediate off position that disconnects C1 from both Vcc and 0V. When S1 reaches the middle off position, S2 connects between C1 and C2. This allows
If C1 = C2, the total charge of C1 and C2 (q1 + q
2) is redistributed to C1 and C2 in equal amounts of 1/2.

FIG. 1C shows the operation when the j-th bit value bj of the digital input signal Din is "0" (b).
j = “0”). In this case, S1 charges (discharges) C1 to 0V. Thereafter, S1 is at an intermediate off position that disconnects C1 from both Vcc and 0V. When S1 reaches the middle off position, S2 connects between C1 and C2. Thus, if C1 = C2, C1 and C2 are obtained in the same manner as in the above case.
The two total charges (q1 + q2) are redistributed into C1 and C2 in equal amounts of １ ／.

The above operation is performed by the digital input signal Di.
By repeating one bit at a time in order from the lower bit to the upper bit of n, the charging voltage (V) corresponding to the digital value of the digital input signal Din is applied to C1 and C2.
A) is formed.

For example, if the digital input signal Din is an 8-bit binary code string, "00000000"
From "11111111" (from 0 to 255 in decimal) is from 0V to 255 × Vcc / 2
It is converted in linear correspondence to up to 56 voltages.

[0018]

However, it has been clarified by the present inventors that the above-described technology has the following problems.

That is, the above-described charge redistribution type D / A
In order for the conversion operation of the converter to be performed ideally, the capacitance values of the first capacitance element C1 and the second capacitance element C2 must be completely the same (C1 = C2). However, in reality, it is impossible to form C1 and C2 completely identically, and usually some error is interposed.

If this error exists, the analog output voltage VA cannot linearly increase with respect to the digital input signal Din, as shown in FIG. The signal Din (“00
000000 ”to“ 11111111 ”(“ 01111111 ”,“ 100000 ”)
It has been clarified by the present inventors that a problem arises in that the monotonicity of the analog output voltage VA is greatly disturbed at 0 ″).

This monotonic disorder is generated as follows.

That is, the two capacitive elements C1,
If C2 is not completely the same capacitance, the two capacitive elements C2
The redistribution of charge to C1 and C2 cannot be accurately performed in equal amounts of 1/2. Errors due to this uneven charge redistribution are accumulated each time the charge is redistributed. At this time, the redistribution of the charge is sequentially repeated one bit at a time in the order from the lower bit to the upper bit of the digital input signal Din. A cumulative error occurs.

Therefore, where the digital input signal Din changes from "01111111" to "10000000", the change in the digital value is 00000001 (2
Base) = 1 (decimal), and the corresponding change in the analog output voltage VA is ideally 128 × Vcc / 2.
56-127 × Vcc / 256 = Vcc / 256, but “01111111” and “100000
In the case of "00", the accumulation of errors due to the redistribution of electric charges is maximized, so that a large differential error occurs as shown in FIG. 12 (A) or (B).

In FIG. 12, (A) shows the conversion characteristics when C2> C1, and (B) shows the conversion characteristics when C2 <C1.

As shown in the figure, in any case, if there is a difference between the two capacitance elements C1 and C2, a large differential error occurs at the center of the D / A conversion range. The center of this conversion range is the most frequently used area. For example, in the case of a digital servo system, feedback control is performed to stabilize the system in the center of the conversion range, thereby compensating for fluctuations in the system. The maximum possible range can be brought. However, if there is a large differential error in the center of the conversion range in which the maximum compensable range can be obtained, there arises a problem that the feedback operation for performing the compensation becomes unstable.

As described above, in the D / A converter, it is very important to ensure the monotonicity of the conversion characteristic, and particularly to reduce the differential error at the center of the conversion range.

An object of the present invention is to provide a technique for ensuring monotonicity of conversion characteristics of a charge redistribution type D / A converter, and particularly for reducing a differential error at the center of a conversion range.

The above and other objects and features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0029]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the first means is provided in accordance with the first and second capacitance elements formed to have the same capacitance value with each other and the bit value of a digital input signal composed of a binary code string of a plurality of bits. A first switch for charging the first capacitor to a high reference potential or a low reference potential; and connecting the first capacitor charged by the first switch to the second capacitor in parallel. Second switch means for redistributing the total electric charge of both capacitance elements at the same potential; charging the first capacitance element by the first switch means and redistributing the total electric charge by the second switch means Is sequentially repeated one bit at a time in the order from the lower bit to the upper bit of the digital input signal to generate a charging voltage corresponding to the digital input signal value. To the D / A is taken out as a
The converter includes circuit switching means for switching between the first capacitive element and the second capacitive element according to the digital input signal value (first invention).

[0031] The second means is the first means,
Circuit switching means for switching between the first capacitive element and the second capacitive element according to the most significant bit value of the digital input signal is provided (second invention).

The third means comprises a first and a second capacitance element formed to have the same capacitance value with each other, and a first capacitance element according to a bit value of a digital input signal comprising a binary code string of a plurality of bits. A first switch means for charging the first capacitance element to the high reference potential or the low reference potential, and the first capacitance element charged by the first switch means is connected in parallel to the second capacitance element to thereby provide both capacitances. A second switch means for redistributing the total electric charge of the element at an equal potential;
The charging of the first capacitive element by the switching means and the redistribution of the total charge by the second switching means are sequentially repeated one bit at a time in order from the lower bit to the upper bit of the digital input signal. A D / A converter configured to generate a charging voltage corresponding to the value and extract the charging voltage as an analog output signal, wherein the first capacitor and the second capacitor are connected to a bit of the digital input signal. Circuit switching means for switching and switching according to the position is provided (third invention).

A fourth means is the third means,
Circuit switching means for switching between the first capacitive element and the second capacitive element for each bit of the digital input signal is provided (fourth invention).

According to the above-described means, the non-linear error caused by the capacitance difference between the first capacitance element and the second capacitance element is equal to D
It is possible to avoid large appearance in the middle of the / A conversion range, especially at the center of the range.

This achieves the object of ensuring the monotonicity of the conversion characteristics of the charge redistribution D / A converter and reducing the differential error at the center of the conversion range, in particular.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

In the figures, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a charge redistribution D / A converter to which the technique of the present invention is applied.

The D / A converter shown in FIG. 1 includes a first capacitive element C1, a second capacitive element C2, and a first switch circuit S.
1, second switch circuit S2, third switch circuit S
3, the fourth switch circuit S4, the sequence control circuit 1,
It comprises a voltage sampling circuit 2, a switching control circuit 3, and the like, and converts a digital input signal Din composed of a binary code string of a plurality of bits into an analog output voltage VA and outputs it.

In the figure, the first and second capacitance elements C1 and C2 are formed to have the same capacitance (C1 = C2), but they are not completely the same, and a slight error .DELTA. are doing.

The first switch circuit S1 charges the first capacitive element C1 to a high reference potential (Vcc) or a low reference potential (0V) according to the bit value of the digital input signal Din. That is, when the bit value is “1”, C1 is set to Vc
Charge to c, and if "0", charge (discharge) C1 to 0V
I do.

The second switch circuit S2 is constructed by connecting the first capacitive element C1 charged to Vcc or 0V by the first switch circuit S1 to the second capacitive element in parallel to form both capacitive elements C1 and C2. Are redistributed at the same potential.

At this time, it is ideal that the electric charges redistributed to C1 and C2 are equal to each other by half. However, due to the above-mentioned error Δ, the electric charges are biased by the error Δ. Is done.

The sequence control circuit 1 determines that C1
And a redistribution of the total charge by S2 is sequentially performed one bit at a time in order from the lower bit to the upper bit of the digital input signal Din.

The voltage sampling circuit 2 analog-samples and holds the charging voltages of C1 and C2, and outputs this as an analog output voltage VA. Cp is a capacitance element for holding a voltage.

Third and fourth switch circuits S3, S4
Performs circuit switching to alternate between the first capacitive element C1 and the second capacitive element C2. The switching control circuit 3 controls the switching position of the switch circuits S3 and S4 according to the value of the digital input signal Din. That is, the switch circuit S
3, S4 and the switching control circuit 3 form circuit switching means for switching between the first capacitive element C1 and the second capacitive element C2 in accordance with the digital input signal Din value.

FIG. 2 shows the charge redistribution type D / A shown in FIG.
4 shows an operation timing chart of the converter.

In the example shown in FIG.
The operation of the switch circuits S1 and S2 when the 8-bit binary code string “01001101” is input as n is shown.

In this case, the switch circuits S3 and S4 charge the first capacitor C1 to Vcc or 0 in accordance with the bit value of the digital input signal Din, and charge the second capacitor C2 to the redistributed charge. In the switching position to carry over.

The charge of C1 by the switch circuit S1 and the redistribution of the total charge by the switch circuit S2 are performed by switching one bit from the lower bit to the upper bit of the digital input signal Din (b0, b1, b2,..., B7). Are sequentially repeated.

That is, Din is “01001101”
In the case of, first, the least significant bit value b0 = "1"
1 is turned on, C1 becomes Vcc
(High-side reference potential). After this charge, S2
Is turned on, and C1 and C2 are commonly connected in parallel, whereby the total charge of C1 and C2 is redistributed to C1 and C2 in substantially equal amounts.

Next, the lower second bit value b1 = "0"
In response, S1 is turned on between bc and C1.
Is charged (discharged) to 0V. Thereafter, as in the case described above, the charge is redistributed by turning on S2.

When the lower third bit value b2 = "1", C
1 is charged to Vcc, and the charge charged to C1 and C1
2 is redistributed to C1 and C2.

By repeating the above-described charge and redistribution operations, the most significant bit value b7 = "0".
At the time when charging and redistribution are completed, C1 and C2 contain:
Each bit value (b0 = “1”, b1 = “0”, b2 =
“1”, b3 = “1”, b4 = “0”, b5 = “0”,
b6 = "1", b7 = "0") the power series sum to a constant ^{(b0 · 2 0 + b1 ·} 2 1 + b2 · 2 2 + b3 · 2 3 + b4
・ 2 ⁴ + b5 2 ⁵ + b6 2 ⁶ + b7 2 ⁷ = 2 ⁰ +0+
Voltage (77 ×) corresponding to 2 ² +2 ³ + 0 + 0 + 2 ⁶ +0)
Vcc / 256) is charged. Then, this charging voltage is sampled and held by the sampling circuit 2 and output as an analog output voltage VA. This analog output voltage VA is equal to the digital input signal Din =
This corresponds to the value “001001101”.

FIG. 3 shows the charge redistribution D / A shown in FIG.
3 shows a more specific embodiment of the converter.

In the figure, the sequence control circuit 1
Digital input signal Din (b0 to b0) in the parallel data format
b (n-1) or b7) in serial data format (bj)
And a serial output (bj) of the parallel / serial conversion circuit 11
And a timing control circuit 12 for controlling the switch circuits S1 and S2 based on the synchronous clock signals φ1 and φ2.

In the embodiment shown in the figure, the switching control circuit 3 is constituted by a circuit which only extracts the binary signal of the most significant bit b7 of the digital input signal Din. By the switching control circuit 3, the switching circuits S3 and S4 are binary-controlled by the signal value of the most significant bit b7 of the digital input signal Din. Thus, the first capacitive element C1 and the second capacitive element C2 are switched and changed according to the value of the most significant bit b7 of the digital input signal Din. That is, the capacitance elements C1 and C2 change the digital input signal Din from “00000000” to “01111111”.
1 ”and between“ 10000000 ”and“ 1 ”.
The position on the circuit can be switched between when it is between 1111111 "and the other.

FIG. 4 shows that the digital input signal Din is "01".
The operation in the case of 111111 ″ or less will be described.

In this case, charging based on the bit value of the digital input signal Din is performed on the first capacitive element C1, and the charge charged on the first capacitive element C1 is transferred to the second capacitive element C2. Redistributed between

FIG. 7A shows an initialization operation performed every time the digital input signal Din is updated. In this initialization operation, both C1 and C2 are connected to a low reference potential (0 V) to temporarily set each charge to zero.

FIG. 11B shows the bit value of “1” (bj =
"1") indicates a state in which C1 is charged to Vcc. FIG. 9C shows a bit value of “0” (bj = “0”).
Shows a state in which C1 is charged to 0 V based on. (D)
Shows a state in which C1 charged to Vcc or 0V in (B) or (C) is commonly connected to C2, and charge redistribution by equipotential is performed.

FIG. 5 shows that the digital input signal Din is "10
The operation in the case of 000000 "or more is shown.

In this case, the charging based on the bit value of the digital input signal Din is performed on the second capacitive element C2, and the electric charge charged in the second capacitive element C2 is transferred to the first capacitive element C1. Redistributed between

FIG. 9A shows an initialization operation performed every time the digital input signal Din is updated. In this initialization operation, both C1 and C2 are connected to a low reference potential (0 V) to temporarily set each charge to zero.

FIG. 9B shows a bit value (bj = 1) of “1”.
"1") indicates a state in which C2 is charged to Vcc. FIG. 9C shows a bit value of “0” (bj = “0”).
Shows a state in which C2 is charged to 0 V based on. (D)
Shows a state in which C2 charged to Vcc or 0V in (B) or (C) is commonly connected to C1 at an equal potential, and charge redistribution is performed.

Equations (1) to (3) represent the charge redistribution type D /
The operation of the A converter is shown by a mathematical model.

[0067]

(Equation 1)

[0068]

(Equation 2) First, Equations 1 and 2 will be described for each stage from n = 0 to n = k.

N = 0: Initialization As shown in the equation (1), the charges q1 and q2 of C1 and C2 are both set to 0.

N = 1: Charging and Redistribution of Electric Charge with Least Significant Bit Value b0 The capacitive element C1 is charged to a voltage corresponding to the product of the least significant bit value b0 and the high-side reference potential Vcc. That is, b
If 0 = "1", it is charged to Vcc, and if b0 = "0", it is charged to 0V. That is, C1 is charged with the electric charge q1 given by Expression (2).

After the charging, when the capacitance elements C1 and C2 are commonly connected so as to have the same potential, the sum (q1 + q2) of the charge q1 of C1 and the charge q2 of C2 becomes C1.
1 and C2. In this case, since the charge q2 of C2 has been initialized to 0 in advance, the charge voltage V1 of C1 and C2 after the charge redistribution is represented by Expression (3).

The capacity ratio r1 of C1 to C2 is expressed by the following equation (4).
By defining as follows, V1 is as shown in equation (5). C
2, the charge q2 given by the equation (5) is distributed.
This distributed charge q2 of C2 is carried over to the next stage (n = 2).

N = 2: Charge and redistribution of charge using lower-order second bit value b1 Similarly to the above case, as shown in equation (7), lower-order second bit b1 value (“1” or “0”) C) is charged by the product of ") and Vcc.

After this charging, as in the previous case,
The total charge (q1 + q2) of 1 and C2 is redistributed to C1 and C2. At this time, the charge q2 distributed last time (n = 1) is carried over to C2. Therefore, the charge voltage V2 of C1 and C2 after the current charge redistribution is as shown in Expression (8).

The capacitance ratio r2 of C2 to C1 is expressed by the following equation (9).
If V2 is defined as follows, V2 is as shown in Expression (10).
The charge q2 given by the equation (11) is distributed to C2 and carried over to the next stage (n = 3).

N = 3: Charge and redistribution of electric charge by the lower third bit value b2 As shown by the equation (12), the product of the lower third bit b2 value ("1" or "0") and Vcc Charging of C1 is performed.

After this charge, due to the charge redistribution between C1 and C2, the charge voltage V3 of C1 and C2 becomes as shown in equation (13), and the charge q2 given by equation (14) is applied to C2.
Is distributed. Then, the charge q2 distributed to C2 is carried over to the next stage (n = 4).

N = 4: Charge and redistribution of electric charge by lower 4th bit value b3 Charge of C1 according to equation (15) is performed as in the previous case. The charge redistribution performed after this charge allows C
The charge voltage V4 of C1 and C2 is as shown in Expression (16). C
2, the charge q2 given by equation (17) is distributed and carried over to the next stage (n = 5).

N = k: Charging and redistribution of electric charges by the lower k-th bit value b (k-1) As described above, electric charges are charged to C1 by the equation (18). By the charge redistribution performed after the charging, the charging voltage Vk of C1 and C2 becomes as shown in Expression (19).

As described above, at the stage where charging and redistribution by the voltage (Vcc or 0 V) corresponding to the k-th bit value b (k-1) from the least significant are performed, the digital input signal Din Each bit value (b0, b1, b2, b
3,..., B (k-1)) are charged to C1 and C2 with a voltage Vk corresponding to the sum of 1/2 power series. Thus, a digital input signal Din (b0, b1, b2, b3,..., B (k−
1)) is converted into an analog voltage Vk given by equation (19) and output.

Equation 3 is obtained by converting the above equation (19) into C1 = C2,
C2> C1 and C2 <C1.

[0082]

(Equation 3) In Equation 3, if C1 and C2 are equal in capacity (C1 = C2), the voltage Vk after k times of charging and charge redistribution is given by the following equation (2).
0), the sum of 1/2 power series with each bit value (b0, b1, b2, b3,..., B (k-1)) of the digital input signal Din as a constant, which is k Digital input signal Din (b0, b) consisting of a binary code sequence of bits
1, b2, b3,..., B (k-1)).

On the other hand, if there is a capacitance error Δ between C 1 and C 2, the voltage Vk does not become the sum of ベ power series as in equation (21) or (22). The voltage Vk no longer accurately corresponds to the value of the digital input signal Din.

As described above, if there is a capacitance error Δ between C1 and C2, the analog output voltage Vk changes to the digital input signal Di.
An error occurs that the value does not linearly correspond to the n value. This error is a non-linear error that changes according to the bit pattern of the digital input signal Din, and appears as follows.

That is, the non-linear error due to the capacitance error Δ between C1 and C2 appears where a carry (or a borrow) occurs in the bit sequence of the digital input signal Din composed of a binary code sequence. Further, the error due to the carry becomes more remarkable as the number of bits that are simultaneously inverted from “1” to “0” due to the carry increases.
It appears most prominently when the most significant bit value of the digital input signal Din is inverted from “0” to “1”. This is because in the carry in which the most significant bit is inverted, the bit values of the second and upper most significant bits are simultaneously inverted from “1” to “0”. Therefore, for example, in the case of an 8-bit D / A converter, as shown in FIGS.
The center of the A conversion range (“01111111” and “100
00000 "), a differential error occurs in which the analog output voltage sharply rises or falls.

Although the above-mentioned non-linear error appears in both cases of C2> C1 and C2 <C1, C2, C1
If the capacitance errors Δ between the two are the same, they appear symmetrically.
For example, when C2> C1, it appears as shown in FIG. 12A, but when C2 <C1, it appears as shown in FIG. 12B. This symmetry also appears in the expressions (21) and (22).

Here, assuming that the capacitance error Δ between C2 and C1 is the same, the D / A conversion characteristic curve when C2> C1 and the D / A conversion characteristic curve when C2 <C1 are digitally calculated. The most significant bit of the input signal Din changes from “0” to “1”
6A or 6B, Din becomes "0111" as shown in FIG.
The end point of the characteristic curve portion at 1111 "or less can be made continuous with the starting point of the characteristic curve portion at Din of" 10000000 "or more, whereby a monotonous characteristic curve can be synthesized as a whole.

That is, as shown in FIGS. 4 and 5,
According to the most significant bit value of the digital input signal Din, C1
And C2, the center of the D / A conversion range (“01” as shown in FIG. 6A or 6B).
A differential error in which the analog output voltage sharply increases or decreases between “111111” and “10000000”) can be canceled.

FIG. 6 shows the conversion characteristics of the D / A converter shown in FIG.

In the figure, (A) shows the characteristics when there is a capacitance error of C2> C1, and (B) shows the characteristics when there is a capacitance error of C2 <C1.

As described above, the non-linear error caused by the capacitance difference between the first capacitance element C1 and the second capacitance element C2 greatly appears in the middle of the D / A conversion range, especially at the center of the range. Can be avoided. This achieves the object of ensuring the monotonicity of the conversion characteristics of the charge redistribution D / A converter and reducing the differential error, especially at the center of the conversion range.

FIG. 7 shows a configuration example of a charge redistribution D / A converter according to another embodiment of the present invention.

The following description focuses on the difference from the above-described embodiment. In the D / A converter shown in FIG.
Switching between 1 and C2 is performed not according to the digital input signal Din value, but according to the bit position in the digital input signal.

As a means for realizing the switching, in the embodiment shown in FIG.
(Divide-by-2 flip-flop) 31 is used. This counter 31 outputs a digital input signal D
The output switches from "1" to "0" or from "0" to "1" for each bit (bj) of in. By performing binary control of the switch circuits S3 and S4 with the output of the counter 31, C1 and C2 are switched and switched every bit of the digital input signal Din.

FIG. 8 shows the operation of the D / A converter shown in FIG.

In FIG. 9A, the first capacitive element C1 is charged to Vcc by the switch circuit S1 because the j-th bit value bj of the serially converted digital input signal Din is "1". Indicates the state that is performed.

(B) shows that C1 and C2 are switched circuits S2
2 shows that the common charge (q1 + q2) of C1 and C2 is redistributed to C1 and C2.

After the states of (A) and (B), as shown in (C), the positions of the switch circuits S3 and S4 are switched, and the circuit positions of C1 and C2 alternate.

Thereafter, as shown in (D) and (E),
The charge and the redistribution based on the next bit value b (j + 1) of the digital input signal Din are performed. At this time, the charge is performed on C2, and the charge q charged on C2 is performed.
The sum (q1 + q2) of 2 (= b (j + 1) × C2 × Vcc) and the charge q1 (= Vj × C1) distributed to C1 is redistributed to C2 and C1.

Thereafter, the positions of the switch circuits S3 and S4 are switched again, and the circuit positions of C1 and C2 alternate again.

As described above, by changing the circuit positions of C1 and C2 for each bit position of the digital input signal Din, the conversion error caused by the large amount of charge distribution to either C2 or C1 can be reduced. As a result, the non-linear errors due to the capacitance error between C1 and C2 can be significantly improved as shown in FIG.

FIG. 9 shows the conversion characteristics of the D / A converter shown in FIG.

As shown in the figure, the analog output voltage VA
Exhibits substantially good monotonicity over the entire conversion range without being significantly affected by "1" / "0" inversion due to a carry in the bit string of the digital input signal Din.

As described above, the first invention of the present invention is characterized in that the first and second capacitance elements (C1 and C2) formed to have the same capacitance value,
The first capacitive element (C1) is set to the high reference potential (V) in accordance with the bit value of the digital input signal (Din) composed of a binary code string.
cc) or a row reference potential (0 V), a first switch means (S1), and the first switch means (S1).
By connecting the first capacitive element (C1) charged in 1) to the second capacitive element (C2) in parallel, the total charge (q1 + q2) of both capacitive elements (C1, C2) is redistributed at the same potential. A second switch means (S2);
The first capacitive element (C1) by the switch means (S1)
Charging and redistribution of the total charge (q1 + q2) by the second switch means (S2) are performed by the digital input signal (D
in), the digital input signal (D
in), a charging voltage corresponding to the value is generated, and this charging voltage is taken out as an analog output signal (VA).
/ A converter, the first capacitance element (C1) and the second capacitance element (C2) are connected to the digital input signal (Di).
n) circuit switching means (S
3, S4, 3).
Thereby, the nonlinearity of the analog output with respect to the digital input can be improved.

[0105] The second invention is the first invention according to the first invention.
Circuit switching means (S3, S4, 3) for switching between the capacitive element (C1) and the second capacitive element (C2) according to the most significant bit value of the digital input signal (Din). Thus, the differential error at the center of the D / A conversion range can be effectively improved.

According to the third aspect of the present invention, the first and second capacitive elements (C1, C2) formed to have the same capacitance value as each other.
2) and a first capacitive element (C) according to the bit value of a digital input signal (Din) composed of a binary code string of a plurality of bits.
1) is changed to the high reference potential (Vcc) or the low reference potential (0
V) A first switch means (S1) for charging the first capacitor means (C1) and a first capacitor element (C1) charged by the first switch means (S1) are connected in parallel to a second capacitor element (C2). As a result, the total charge (q1) of the two capacitive elements (C1, C2)
+ Q2) at the same potential, and a second switch means (S2) for charging the first capacitive element (C1) by the first switch means (S1) and a second switch means (S2). ), The charge voltage corresponding to the value of the digital input signal (Din) is generated by sequentially repeating the redistribution of the total charge (q1 + q2) by 1 bit from the lower bit to the upper bit of the digital input signal (Din). The D / A converter is configured to take out the charging voltage as an analog output signal (VA).
Circuit switching means (S3, S4, 3) for switching between the capacitive element (C1) and the second capacitive element (C2) according to the bit position of the digital input signal (Din). Therefore, the nonlinearity of the analog output with respect to the digital input can be improved.

The fourth invention is the third invention, wherein the first
Circuit switching means (S3, S4, 3) for switching between the capacitive element (C1) and the second capacitive element (C2) for each bit of the digital input signal (Din). Thus, “1” / caused by a carry in the bit string of the digital input signal (Din).
Almost good monotonicity can be obtained over the entire conversion range without being significantly affected by "0" inversion.

The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

For example, capacitance elements C1 and C2 shown in FIG.
The same effect can be obtained even if the switching replacement is performed every two bits or according to another rule.

In the above description, mainly the case where the invention made by the present inventor is applied to a digital servo D / A converter, which is the field of application as the background, is not limited thereto. For example, it can be applied to digital audio or digital video.

[0111]

The effects of typical inventions disclosed in the present application will be briefly described as follows.

That is, the effect is obtained that the monotonicity of the conversion characteristics of the charge redistribution D / A converter can be ensured, and the differential error at the center of the conversion range can be reduced.

[Brief description of the drawings]

FIG. 1 is a charge redistribution D / A to which the technology of the present invention is applied.
Circuit diagram showing one embodiment of the converter

FIG. 2 is a timing chart showing an operation example of the charge redistribution D / A converter shown in FIG.

FIG. 3 is a circuit diagram showing a more specific embodiment of the charge redistribution D / A converter shown in FIG. 1;

FIG. 4 is a state-by-state circuit diagram showing an operation when a digital input signal is “01111111” or less.

FIG. 5 is a state-specific circuit diagram showing an operation when a digital input signal is “10000000” or more.

FIG. 6 is a diagram showing conversion characteristics of the D / A converter shown in FIG.

FIG. 7 shows a charge redistribution D / according to another embodiment of the present invention.
Circuit diagram showing a configuration example of an A converter

FIG. 8 is a circuit diagram for each state showing the operation of the D / A converter shown in FIG. 7;

FIG. 9 is a diagram showing conversion characteristics of the D / A converter shown in FIG. 7;

FIG. 10 shows a charge redistribution type D /
Circuit diagram showing a schematic configuration of the A converter

11 is a circuit diagram for each state showing an operation example of the D / A converter shown in FIG.

FIG. 12 is a diagram showing conversion characteristics of the D / A converter shown in FIG.

[Explanation of symbols]

 C1 first capacitance element C2 second capacitance element S1 first switch circuit S2 second switch circuit S3 third switch circuit S4 fourth switch circuit 1 sequence control circuit 2 voltage sampling circuit 3 switching control circuit Din digital Input signal VA Analog output voltage

Claims (4)

[Claims] A first capacitor and a second capacitor formed to have the same capacitance value with each other, and a first capacitance element according to a bit value of a digital input signal composed of a binary code string of a plurality of bits. A first switch for charging to a high reference potential or a low reference potential, and a first capacitor charged by the first switch is connected in parallel to a second capacitor, so that the total charge of both capacitors is obtained. And a second switch means for redistributing the digital input signal at the same potential. The charging of the first capacitive element by the first switch means and the redistribution of the total charge by the second switch means are performed by the digital input signal. A charge voltage corresponding to the digital input signal value is generated by sequentially repeating one bit at a time in the order from the lower bit to the upper bit, and the charge voltage is extracted as an analog output signal. D / A converter, the first
A D / A converter characterized by comprising circuit switching means for switching between the capacitive element and the second capacitive element in accordance with the digital input signal value. 2. The D / D converter according to claim 1, further comprising circuit switching means for switching between the first capacitance element and the second capacitance element in accordance with the most significant bit value of the digital input signal. A converter. 3. The first and second capacitance elements formed to have the same capacitance value with each other, and the first capacitance element according to a bit value of a digital input signal composed of a binary code string of a plurality of bits. A first switch for charging to a high reference potential or a low reference potential, and a first capacitor charged by the first switch is connected in parallel to a second capacitor, so that the total charge of both capacitors is obtained. And a second switch means for redistributing the digital input signal at the same potential. The charging of the first capacitive element by the first switch means and the redistribution of the total charge by the second switch means are performed by the digital input signal. A charge voltage corresponding to the digital input signal value is generated by sequentially repeating one bit at a time in the order from the lower bit to the upper bit, and the charge voltage is extracted as an analog output signal. D / A converter, the first
A D / A converter characterized by comprising circuit switching means for switching between the capacitive element and the second capacitive element according to the bit position of the digital input signal. 4. The D / A converter according to claim 3, further comprising circuit switching means for switching between the first capacitive element and the second capacitive element for each bit of the digital input signal. vessel.