JP2000049605A - A/d conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D conversion circuit where power consumption is less and the influence of noise appearing in converted digital output is comparatively small. SOLUTION: A sample-and-hold circuit having capacity for holding an input analog signal for prescribed time, an A/D converter 1 which A/D-converts the signal held in the sample-and-hold circuit and a digital multiplier 2 multiplying the output of the A/D converter 1 by a gain signal are provided for an A/D conversion circuit 10. A plurality of capacities different in capacity values and a capacitor switching pulse block 4 selecting the capacity of the large capacity value when the gain signal is large and the capacity of the small capacity value when the gain signal is small from a plurality of capacities are installed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D conversion circuit, and more particularly to an A / D conversion circuit which suppresses power consumption and reduces the influence of noise.

[0002]

2. Description of the Related Art In an A / D conversion circuit, accurate conversion cannot be performed unless the analog input is kept constant for a predetermined time required for the A / D conversion. In order to maintain the analog input, a sample and hold circuit (sample and hold) for holding the input analog signal for a certain time is provided before the A / D converter.
hold circuit). Usually, this sample-and-hold circuit is often constituted by a combination of an analog switch and a capacitor.

The capacitor for sampling and holding the input analog signal generates noise called KT / C noise, which is inversely proportional to the square root of the capacitance C of the capacitor.
This is the dominant noise of the D conversion circuit. Furthermore,
If a digital gain is applied to the output of the A / D conversion circuit, the KT / C noise becomes prominent.

If it is assumed that a capacitor having a large capacitance C is used as a sample and hold capacitor in order to suppress the KT / C noise, it is necessary to sufficiently set and set the sample and hold. However, there arises a problem that the current consumption increases and the time constant becomes large, and the conversion speed decreases.

[0005]

As described above, the sample-and-hold capacitor generates noise that is inversely proportional to the square root of its capacitance, which is the dominant noise of the A / D conversion circuit. To reduce this noise,
Assuming that the capacity of the hold capacitor is large,
There is a problem that power consumption required for settling increases and conversion speed decreases.

An object of the present invention is to solve this problem by a relatively simple method and to realize an A / D conversion circuit which consumes less power and has a relatively small influence of noise appearing in a converted digital output. .

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a sampling and holding means having capacity means for holding an input analog signal for a predetermined time, and an input analog signal held by the sampling and holding means. A
In an A / D conversion circuit including A / D conversion means for performing A / D conversion and digital multiplication means for multiplying an output of the A / D conversion means by a gain constant, the capacitance means includes a plurality of capacitance elements having different capacitance values. And a capacitance selecting means for selecting a capacitance element having a large capacitance value when the gain constant is large and a capacitance element having a small capacitance value when the gain constant is small among the plurality of capacitance elements. Features.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an A / D conversion circuit according to the present invention will be described in detail with reference to the accompanying drawings. FIG.
1 is a block diagram illustrating a configuration of an embodiment of an A / D conversion circuit according to the present invention. In FIG. 1, reference numeral 10 denotes an A / D conversion circuit, 1 denotes an A / D converter, 2 denotes a multiplier, 3 denotes a microcomputer, and 4 denotes a capacitor of a sample and hold circuit in the A / D converter 1. This is a capacitor switching pulse block that generates a pulse.

The analog input signal to be converted is A /
The signal is input to the D converter 1 and converted into a digital signal.
The converted digital signal is multiplied by the gain signal sent from the microcomputer 3 by the multiplier 2 to output an amplified digital output signal. Here, a digital AGC (automatic gain control) circuit can be configured by outputting a signal inversely proportional to the time integral of the output of the A / D conversion circuit 10 from the microcomputer 3 as the gain signal.

A gain signal sent from the microcomputer 3 is sent to the capacitor switching pulse block 4 at the same timing, and the capacitor switching pulse block 4 is used for a capacitor used in the sample and hold circuit of the A / D converter 1. Is generated based on this gain signal.

FIG. 2 is a circuit diagram showing an example of a sample and hold circuit in the A / D converter 1 used in the A / D conversion circuit of the present invention. In FIG. 2, reference numerals 11 and 12 denote first stage capacitors, which are input capacitors constituting the input impedance of the amplifier 15. Reference numerals 13 and 14 denote capacitors at the subsequent stage, which are feedback capacitors constituting the feedback impedance of the amplifier 15.
It is assumed that each of the capacitors 11, 12, 13, and 14 is provided with switch means for selecting the capacitor. Further, the capacitance C11 of the capacitor 11 and the capacitor 11
And the capacitance C13 of the capacitor 13 and the capacitance C14 of the capacitor 14 have a relation of C14> C13. Fifteen
Is an amplifier.

The sample and hold circuit comprises input capacitors 11 and 12, feedback capacitors 13 and 14, and an amplifier 15 for supplying a current to each capacitor. In the case of a pipeline type A / D converter, such a sample-and-hold circuit has a configuration in which a plurality of stages are connected in series.

The capacitors 11, 12, 13, and 14 used in the sample and hold circuit generate noise (KT / C noise) inversely proportional to the square root of the capacitance, and this noise is controlled by the A / D converter 1. Noise. Therefore, in FIG. 1, when the multiplication gain of the multiplier 2 is large, the capacitor switching pulse block 4 selects the capacitors 12 and 14 having the larger capacitance in order to lower the noise level of the amplified digital signal. . However, in this case, there is a problem that the time constant increases, and when a large analog input enters, the current flowing through the amplifier 15 increases, thereby increasing power consumption.

On the other hand, when the multiplication gain is small, the capacitor switching pulse block 4 selects the capacitors 11 and 13 having the smaller capacitance. Thereby, the amplifier 15
Even if the current flowing through the analog input signal is small, a large analog input signal can be set and power consumption can be reduced.

In the above, a description has been given of a case in which the capacitors are composed of a large-capacity capacitor and a small-capacity capacitor, and one of them is selected according to the magnitude of the multiplication gain. Four or more different capacitors having different capacities, the one having the largest capacitance when the multiplication gain is the largest, the one having the smallest capacitance when the multiplication gain is the smallest, and the middle gain At times, try to choose a medium capacity,
It is, of course, possible to respond finely according to the multiplication gain, and it is possible to respond more finely to noise and power consumption.

In integrating the A / D conversion circuit 10 of the present embodiment shown in FIG. 1, the multiplier 2 is not housed in the same chip as the A / D converter 1, and the A / D conversion circuit 10
DSP (Digital Signal Processing Circuit: Digital Sign)
al Processor) side can be stored together with the microcomputer 3 and the like.

[0017]

As described above, according to the first aspect of the present invention, there is provided a sampling and holding means having a capacitance means for holding an input analog signal for a predetermined time, and an input analog signal held by the sampling and holding means. A / D conversion means for A / D conversion of the A / D conversion means, and digital multiplication means for multiplying the output of the A / D conversion means by a gain constant.
In the D conversion circuit, the capacitance means includes a plurality of capacitance elements having different capacitance values, and a capacitance selection means for selecting any one of the plurality of capacitance elements according to a gain constant. . This allows for a relatively simple
A capacitor for sample and hold can be selected according to the situation.

According to a second aspect of the present invention, the capacitance selecting means includes a capacitance element having a large capacitance value when the gain constant is large.
When the gain constant is small, a capacitance element having a small capacitance value is selected. Thus, an A / D conversion circuit with low power consumption and relatively little influence of noise appearing on the output can be realized by a relatively simple method.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an A / D conversion circuit of the present invention.

FIG. 2 is a circuit diagram of a sample and hold circuit in the A / D converter according to the embodiment of FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... A / D converter, 2 ... Multiplier, 3 ... Microcomputer, 4 ... Capacitor switching pulse block, 10 ...
A / D conversion circuit, 11, 12 ... first stage capacitor, 13,
14: Post-stage capacitor, 15: Amplifier.

Claims (2)

[Claims] 1. A sample-and-hold means having a capacitor means for holding an input analog signal for a predetermined time, and an input analog signal held by the sample-and-hold means is stored in an A
An A / D conversion circuit comprising: A / D conversion means for performing A / D conversion; and digital multiplication means for multiplying an output of the A / D conversion means by a gain constant, wherein the capacitance means includes a plurality of capacitance elements having different capacitance values. An A / D conversion circuit, comprising: a capacitance selection unit that selects any one of the plurality of capacitance elements according to the gain constant. 2. The capacitance selection means selects a capacitance element having a large capacitance value when the gain constant is large, and selects a capacitance element having a small capacitance value when the gain constant is small. 3. The A / D conversion circuit according to claim 1.