JP2000049533A - Voltage controlled oscillator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage controlled oscillator which controls modulation sensitivity and stabilizes the input level of a buffer to be connected to the subsequent stage. SOLUTION: This voltage controlled oscillator is constructed by connecting buffer circuits in two-stage. In this buffer circuit, a signal is inputted from a positive-phase input terminal 1 and a negative-phase input terminal 2, passes through a differential amplifying part BUF and is outputted from output terminals 3 and 4 through an emitter follower EF. Differential amplifying parts PBUF and NBUF are provided between the output end of the follower EF and the output end of the part BUF. The parts PBUF and NBUF operate as positive and negative feedback amplifiers respectively. A feedback quantity control buffer CBUF controls feedback quantity that is feedbacked to the output of the part BUF by controlling current flowing into the parts PBUF and NBUF.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage controlled oscillator suitable for application to a receiver of an optical transmission system.

[0002]

2. Description of the Related Art Currently, a transmission speed of 2.5 G has been practically used.
In backbone optical transmission systems such as 10 bit / s and 10 Gbit / s, an integrated circuit (I
C) It is necessary to reduce the number of chips and to reduce the cost of the entire optical transmission system. I constituting the receiver
Among the three ICs, a full-wave rectifier, a surface acoustic wave filter (or a dielectric filter), and a limit amplifier, which constitute a timing extraction system for extracting a clock signal from a data signal, are connected to a phase-locked loop (PLL: Phase Lock Loop).
ed Loop), and further integrating it with the IC of the discriminator, it is possible to replace a total of four ICs with one PLL integrated circuit (PLL-IC).
When a receiver is configured by a PLL, a new voltage controlled oscillator (VCO) is required instead of using four ICs as one.

[0003] VCOs can be classified into a multivibrator type and a ring oscillator type. In order to use a frequency comparator for expanding the capture range of the PLL, it is essential to mount a ring oscillator type VCO that can directly output two signals having a phase difference of 90 degrees. As an example of this ring oscillator type VCO, ISSCC94 (19
94 IEEE International Sol
id-State Circuits Conference
nce) pp. 116-117 "An 8GHz
Silicon Bipolar Clock-Rec
overy and Data-Regenerato
r IC ". This circuit is composed of a two-stage buffer, and the phase difference between the first-stage output and the second-stage output clock signal is 90 degrees. In this circuit, one stage is provided. The buffers forming the first and second stages are buffers based on a first transistor pair having a common emitter, and a second transistor pair and a third transistor pair fed back from a load resistor via an emitter follower. The buffer composed of the second transistor pair is applied for the purpose of applying positive feedback, and the buffer composed of the third transistor pair is applied for the purpose of applying negative feedback, and the respective buffers are set to be lower or higher than the reference frequency. The frequency fluctuation range can be determined by the current flowing through the second pair of positive feedback transistors and the third pair of negative feedback transistors.

[0004]

In the prior art, VC
The output clock frequency of O is controlled by the currents of the first to third transistor pairs and the emitter follower constituting the VCO. This current is controlled by the same voltage. Since this control voltage is applied to the base terminal of the current source, the control voltage range is as narrow as 0.6 V as shown in the prior art. Therefore, when the variable range extends to GHz, the modulation sensitivity of the VCO becomes very high. For this reason, the loop band of the PLL is set to 4 MHz or more in accordance with ITU-T.
It is difficult to set to 8 MHz. Further, in the conventional technique, since the currents of the transistor pair and the emitter follower are directly varied, there is also a problem that the fluctuation of the DC bias level of the output clock becomes large.

Accordingly, it is an object of the present invention to provide a voltage controlled oscillator capable of controlling modulation sensitivity. Another object of the present invention is to provide a voltage controlled oscillator that can stabilize the input level of a buffer connected to the next stage.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to have first and second buffer circuits configured to control a feedback amount of a feedback path, and to connect an opposite-phase output terminal of the first buffer circuit to a second buffer circuit.
Connected to the positive-phase input terminal of the first buffer circuit, connected to the negative-phase input terminal of the second buffer circuit, and connected to the negative-phase output terminal of the second buffer circuit. This is achieved by a voltage-controlled oscillator connected to the negative-phase input terminal of one buffer circuit and the positive-phase output terminal of the second buffer circuit connected to the positive-phase input terminal of the first buffer circuit.

Here, the feedback path comprises a positive feedback path and a negative feedback path, and is configured to control the feedback amount of the positive feedback and the negative feedback. This feedback amount is a current amount. Further, a third buffer circuit is connected to at least one output side of the first and second buffer circuits in order to increase the amplitude of the clock oscillation output of the voltage controlled oscillator. The third buffer circuit has one or more stages.

A phase locked loop integrated circuit can be constructed using such a voltage controlled oscillator. A phase-locked loop integrated circuit according to the present invention includes a voltage-controlled oscillator configured to control the modulation sensitivity and outputting first and second clock signals having different phases, and a second circuit configured to input a data signal and a first clock signal. A first phase comparator, a second phase comparator for inputting a data signal and a second clock signal, and a first phase comparator.
A frequency comparator that operates based on an output signal of the second phase comparator, a selector that switches an output signal of the first phase comparator and the output signal of the frequency comparator, and outputs the output signal to the voltage-controlled oscillator, And a phase shifter that receives the second clock signal and adjusts the locked clock phase with respect to the data phase.

Further, a phase locked loop integrated circuit according to the present invention is configured such that a data input terminal for inputting a data signal, a data output terminal for outputting a data signal, and a band of the phase locked loop can be set within a predetermined range. A threshold adjustment terminal for adjusting a threshold value for switching the input signal of the voltage controlled oscillator, a phase shift amount adjustment terminal for adjusting a phase shift amount of a phase shifter for inputting an output clock of the voltage controlled oscillator, A clock output terminal to which the output of the phase shifter is transmitted. Here, the voltage controlled oscillator has a feedback amount control terminal.

Further, the buffer circuit according to the present invention includes a first differential amplifier connected to an input terminal, an emitter follower receiving an output of the first differential amplifier as an input, and an output terminal of the emitter follower. Second and third differential amplifiers provided between the output terminals of the first differential amplifier, and fourth differential amplifier for controlling current flowing through the second and third differential amplifiers Unit.

The fourth differential amplifier has first and second transistors, each base of the first and second transistors as an input terminal, each collector as an output terminal, and both emitters. And a current source is connected to the commonly connected emitter. The fourth differential amplifying section has first and second transistors, and the first and second
The transistors may be configured such that each base is an input terminal, each collector is an output terminal, both emitters are connected via resistors, and a current source is connected between the two resistors.

With this configuration, it is possible to obtain a voltage controlled oscillator capable of controlling the modulation sensitivity. Further, the input level of the buffer connected to the next stage can be stabilized.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a voltage controlled oscillator (VCO) according to the present invention and a phase locked loop integrated circuit (PLL-IC) using the same will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a buffer circuit RBUF constituting a VCO according to the present invention. The signal is input from the positive-phase input terminal 1 and the negative-phase input terminal 2, passes through the differential amplifier BUF, and passes through the emitter follower E.
The signal is output from output terminals 3 and 4 via F. The differential amplifiers PBUF and NBUF connected to the output of the emitter follower EF and connected to the output terminals O1 and O2 of the differential amplifier BUF operate as positive / negative feedback amplifiers, respectively. The differential amplifier PBUF operates as positive feedback to lower the oscillation frequency, and the differential amplifier NBUF operates as negative feedback to increase the oscillation frequency. Therefore, the positive-phase output terminal of the differential amplifier PBUF is
1, while the negative-phase output terminal is connected to O2, the positive-phase output terminal of the differential amplifier NBUF is connected to O2, and the negative-phase output terminal is connected to O1.

The feedback amount control buffer CBUF is provided for controlling the current flowing through the differential amplifiers PBUF and NBUF on the feedback path. By controlling this current, the amount of feedback that is fed back to the output of the differential amplifier BUF can be controlled. Here, when the current flowing through the differential amplifier PBUF is larger than that of the differential amplifier NBUF, positive feedback is applied, and when it is smaller, negative feedback is applied. The feedback amount control buffer CBUF has a feedback amount control terminal 5
And 6 to input a voltage and output a control current.

FIG. 2 shows the buffer circuit RBUF shown in FIG.
FIG. 3 is a block diagram showing one embodiment of a ring oscillator type VCO in which are connected in two stages. In order to operate as an oscillator, the following connections are required. That is, the negative phase output terminal 3 of the buffer circuit RBUF1 is connected to the buffer circuit RBUF.
2, the positive-phase output terminal 4 of the buffer circuit RBUF1 is connected to the negative-phase input terminal of the buffer circuit RBUF2, and the negative-phase output terminal 2 of the buffer circuit RBUF2 is connected to the negative-phase output terminal 2 of the buffer circuit RBUF1. The input terminal is connected to the in-phase output terminal 1 of the buffer circuit RBUF2, and the in-phase output terminal 1 of the buffer circuit RBUF1 is connected to the in-phase input terminal of the buffer circuit RBUF1. In this configuration, the phase difference between the clock signals extracted from the terminals 1 and 2 and the terminals 3 and 4 is 90 degrees, which is useful in a PLL using a frequency comparator. By controlling the feedback amount of the feedback control system of each buffer circuit, the control voltage range can be widened to, for example, 1.0 V to 2.0 V.

FIG. 3 is a block diagram when the amplitude of the clock oscillation output of the VCO shown in FIG. 2 is increased. An output buffer OBUF is connected to the output terminals 1 and 2 of the voltage controlled oscillator VCO including the buffer circuits RBUF1 and RBUF2, and the amplified clock is output to the output terminal RO.
2 and RO1. Also, a voltage controlled oscillator VC
O output terminals 3 and 4 have another output buffer OBUF
, And a clock is similarly extracted from the output terminals RO3 and RO4. FIG. 3 shows an output terminal RO1 /
The phase difference between RO2 and RO3 / RO4 is 90 degrees.

FIG. 4 shows the buffer circuit RBUF shown in FIG.
FIG. 3 is a circuit diagram in a case where the circuit is configured using transistors.
As shown in the figure, the buffer circuit RBUF includes a basic amplification unit BUF and a differential amplification unit PBU operating as positive feedback.
F and a differential amplifier NBUF that operates as a negative feedback, an emitter follower EF, and a feedback control buffer CBUF that controls the current of the differential amplifier PBUF / NBUF.

The basic amplification unit BUF includes a load resistance RL
A transistor pair TR having a common emitter with 1 / RL2
1 / TR2, which includes a diode D1 for withstand voltage protection of a transistor TR3 that operates as a current source. The resistor RE is connected to the emitter of the current source transistor TR3.
1 is connected to apply the voltage VB to the base and control the current. The differential amplifier PBUF is composed of a transistor pair TR4 / TR5 having a common emitter, and the differential amplifier NB
UF is a transistor pair TR7 / TR like PBUF.
8. The emitter follower EF is connected to the output terminals O1 / O of the load resistors RL1 / RL2 of the basic amplifier.
A transistor TR11 / TR12 having 2 as an input and load resistors RE3 / RE4 are output from a terminal 3/4.

The feedback amount control buffer CBUF comprises transistors TR6 / TR9, emitter resistors RD1 / RD2, a current source transistor TR10 and its emitter resistor RE2. The current of the differential amplifiers PBUF and NBUF as a whole is
Controlled by the base voltage VB of the current source transistor TR10, currents flowing through PBUF and NBUF are input terminals 5 and 6 connected to the bases of TR6 and TR9, respectively.
Is controlled by The emitter resistors RD1 and RD2 may not be provided, but by adding them, the dynamic range of the voltage input from the terminals 5 and 6 can be improved, and as a result, the modulation sensitivity of the VCO can be controlled. .

FIG. 5 is a block diagram showing a PLL-IC having the VCO shown in FIG. 2 or 3 built therein. This PLL-IC has an amplifying unit AMP1 / AM as shown in the figure.
An identification unit including P2, a flip-flop FF and an output amplifier AMP3, a phase shifter PS for finely adjusting a locked clock phase with respect to a data phase, an output amplifier AMP4 for a clock signal, a phase comparator PDI / PDQ, and a frequency comparator F
D, a selector SEL for switching output signals of the phase comparator PDI and the frequency comparator FD, a control signal generation circuit CONT for generating a control signal for switching the selector SEL,
It comprises a loop filter LOOP and a voltage controlled oscillator VCO.

The data signal is input from the data input terminal DIN, and the waveform is shaped by the flip-flop FF in the identification section, and reaches the data output terminal DOUT. The data signal is branched after passing through the amplifying unit AMP1.
Input to I and PDQ. The phase comparator PDI has VC
O, a clock signal C0 of a certain frequency is input to the phase comparator PDQ, and a clock signal C9 having a phase difference of 90 degrees from the clock signal C0 input to the phase comparator PDI.
0 is input. When the data transmission speed and the clock frequency are different, the frequency comparator FD operates based on the output signals of the phase comparators PDI and PDQ.
DI and the output signal of the frequency comparator FD are switched. A control voltage threshold adjustment terminal VC is connected to the control signal generation circuit CONT.
By inputting a voltage from, the threshold value for signal switching can be controlled. The input phase and the output phase to the phase shifter PS are controlled by the voltage from the phase adjustment terminal VP. The output of the phase shifter PS reaches the clock output terminal COUT via the flip-flop FF and the output amplifier AMP4. Since the PLL-IC described here has a configuration using the frequency comparator FD, two clock signals having phases different from each other by 90 degrees are required. According to the configuration of the VCO of the present invention,
Two clock signals can be easily generated. By incorporating this VCO in the PLL-IC, the cost of the optical transmission system can be further reduced.

FIG. 6 is a characteristic diagram of the ring oscillator type voltage controlled oscillator. This figure shows the output waveform of the VCO in FIG. 3 when the current of the differential amplifier PBUF is larger than NBUF. The voltage V (2) of the output terminal 2 and the voltage V (3) of the output terminal 3 are 90 degrees out of phase, and the voltage V (RO) at the terminals RO2 / RO3 after passing through the output buffer.
(RO2) and V (RO3), Peak-t
Approximately 0.4 V is amplified by o-peak. The center bias level of V (2) and V (3) is -1.08V.

FIG. 7 is another characteristic diagram of the ring oscillator type voltage controlled oscillator. This figure shows the output waveform of the VCO of FIG. 3 when the current of the differential amplifier NBUF is larger than that of PBUF. The center bias level of the voltages V (2) and V (3) is -1.08V as in the case of FIG.
This indicates that there is no level change due to the feedback amount. At the terminals RO2 / RO3 after passing through the output buffer,
A peak-to-peak amplified waveform up to about 0.4 V was observed.

The output clock frequency is 8. in FIG.
The frequency is 6 GHz, and in the case of FIG. 7, it is 10.9 GHz, which indicates that the frequency can be controlled by the feedback amount control buffer. The difference between the amplitude of the output voltage in FIG. 6 and FIG. 7 is due to the current flowing through the differential amplifier PBUF / NBUF.
This can be dealt with by increasing the number of stages of the output buffer.

By configuring the voltage controlled oscillator using the buffer circuit according to the present invention, it is possible to expand the control voltage range so that the modulation sensitivity of the voltage controlled oscillator becomes a value conforming to ITU-T. Further, the output DC bias level due to the difference in the frequency of the output clock signal can be kept constant, and the input level of the buffer connected to the next stage can be stabilized.

[0027]

According to the present invention, a voltage-controlled oscillator capable of controlling the modulation sensitivity can be obtained. Further, it is possible to obtain a voltage-controlled oscillator that can stabilize the input level of the buffer connected to the next stage.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a buffer circuit constituting a voltage controlled oscillator according to the present invention.

FIG. 2 is a block diagram showing one embodiment of a ring oscillator type voltage controlled oscillator in which two stages of buffer circuits are connected.

FIG. 3 is a block diagram in a case where the amplitude of a clock oscillation output of a voltage controlled oscillator is increased.

FIG. 4 is a circuit diagram in the case where a buffer circuit is formed using transistors.

FIG. 5 shows a PLL-I having a built-in voltage-controlled oscillator.
It is a block diagram which shows C.

FIG. 6 is a characteristic diagram of a ring oscillator type voltage controlled oscillator.

FIG. 7 is another characteristic diagram of the ring oscillator type voltage controlled oscillator.

[Explanation of symbols]

 1, 2 input terminal 3, 4 output terminal 5, 6 feedback amount control terminal O1, O2 differential amplifier output terminal BUF, PBUF, NBUF differential amplifier EF emitter follower CBUF feedback amount control buffer

Claims (10)

[Claims] A first buffer circuit configured to control a feedback amount of a feedback path, wherein an opposite-phase output terminal of the first buffer circuit is connected to a positive-phase input terminal of the second buffer circuit; And the positive-phase output terminal of the first buffer circuit is connected to the second
Connected to the negative-phase input terminal of the second buffer circuit, the negative-phase output terminal of the second buffer circuit is connected to the negative-phase input terminal of the first buffer circuit, and the positive-phase output terminal of the second buffer circuit is connected to the negative-phase input terminal. A voltage-controlled oscillator connected to the positive-phase input terminal of one of the buffer circuits. 2. The voltage controlled oscillator according to claim 1, wherein said feedback path comprises a positive feedback path and a negative feedback path, and is configured to control a feedback amount of said positive feedback path and said negative feedback path. 3. The voltage controlled oscillator according to claim 1, wherein the feedback amount is a current amount. 4. The voltage controlled oscillator according to claim 1, wherein a third buffer circuit is connected to at least one output side of the first and second buffer circuits. 5. A voltage controlled oscillator configured to control the modulation sensitivity for outputting first and second clock signals having different phases, and a first phase comparator for inputting a data signal and a first clock signal. A second phase comparator that inputs a data signal and a second clock signal, a frequency comparator that operates based on output signals of the first and second phase comparators,
A selector for switching the output signals of the phase comparator and the frequency comparator to output to the voltage controlled oscillator, and a phase shifter for inputting the first and second clock signals and adjusting the locked clock phase with respect to the data phase And a phase locked loop integrated circuit. 6. A data input terminal for inputting a data signal, a data output terminal for outputting a data signal, and a threshold for switching an input signal of a voltage controlled oscillator configured so that a band of a phase locked loop can be set within a predetermined range. A threshold adjustment terminal for adjusting a value, a phase shift amount adjustment terminal for adjusting a phase shift amount of a phase shifter for inputting an output clock of the voltage controlled oscillator, and a clock output to which an output of the phase shifter is transmitted. A phase-locked loop integrated circuit having a terminal. 7. The phase-locked loop integrated circuit according to claim 6, wherein said voltage controlled oscillator has a feedback amount control terminal. 8. A first differential amplifier connected to an input terminal, an emitter follower receiving an output of the first differential amplifier as an input, an output terminal of the emitter follower and a first differential amplifier. And second and third differential amplifiers provided between the output terminals of the first and second amplifiers, and a fourth differential amplifier for controlling a current flowing through the second and third differential amplifiers. Characteristic buffer circuit. 9. The fourth differential amplifying unit has first and second transistors, each base of the first and second transistors as an input terminal, each collector as an output terminal, and both emitters as emitters. 9. The buffer circuit according to claim 8, wherein the buffer circuit is connected to a common source, and a current source is connected to the common connected emitter. 10. The fourth differential amplifying section has first and second transistors, each base of the first and second transistors as an input terminal, each collector as an output terminal, and both emitters as emitters. 9. The buffer circuit according to claim 8, wherein each of the buffers is connected via a resistor, and a current source is connected between the two resistors.