JP2000049325A - Output amplifier of solid-state image-pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output amplifier of a solid-state image-pickup device which can convert electric charges into voltage with high sensitivity. SOLUTION: This output amplifier of a solid-state image-pickup device includes the source having sufficient diffusion capacitance for storing electric charges, a first transistor Tr1 for releasing the electric charges stored in the diffusion capacitance to the drain according to the gate voltage, and a second transistor Tr2 using the gate as an input terminal and the source as an output terminal. Also included in this device are an amplifier (Tr2, Tr3, Tr4, Tr5) which is inputted with voltage according to the electric charges stored in the diffusion capacitance and amplifies the voltage, an interconnection 13 for connecting the gate of the second transistor and the source of the first transistor, and a shield line 18 connected to the source of the second transistor, being arranged along the interconnection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a solid-state imaging device, and more particularly, to an output amplifier that outputs a voltage corresponding to the amount of charge generated in the solid-state imaging device.

[0002]

FIG. 6 is a plan view of a solid-state imaging device 1. FIG.

The photoelectric conversion elements 2 are, for example, photodiodes, and are arranged in a large number in a two-dimensional matrix. For example, 492 photodiodes 2 are arranged in the vertical direction and 660 in the horizontal direction.

[0004] The photodiode 2 converts received light into electric charge. The vertical charge transfer path (VCCD) 3 reads out charges from the photodiode 2 and transfers the charges in the vertical direction. Specifically, the four-phase drive pulses φV1 to φV
The charge is transferred from the top to the bottom according to (4).

A horizontal charge transfer path (HCCD) 4 receives charges from the vertical charge transfer paths 3 and transfers the charges in the horizontal direction. Specifically, the two-phase driving pulses φH1 and φH2
, The charge is transferred from right to left.

The output amplifier 5 receives charges from the horizontal charge transfer path 4 and outputs a voltage corresponding to the charge amount. The output amplifier 5 outputs an image signal. The photodiodes 2 arranged two-dimensionally correspond to pixels forming an image.

In recent years, the number of pixels of the solid-state imaging device 1 has been increased. If the number of pixels is increased without changing the area of the semiconductor chip on which the solid-state imaging device 1 is formed, the light receiving area (opening area) of the photodiode 2 decreases. On the other hand, miniaturization of a semiconductor chip on which the solid-state imaging device 1 is formed is progressing. Even if the number of pixels is the same, if the area of the semiconductor chip is reduced, the light receiving area of the photodiode 2 is also reduced.

When the light receiving area of the photodiode 2 decreases, the amount of light received by the photodiode 2 decreases, and the output voltage of the output amplifier 5 decreases. To increase the output voltage, it is necessary to increase the sensitivity of the output amplifier 5.

FIG. 7 is an equivalent circuit diagram of the output amplifier 5 shown in FIG. The capacitance C1 is equal to the floating diffusion FD formed at the pn junction of the transistor Tr1.
And stores the charges transferred from the horizontal charge transfer path 4. A reset drain voltage RD (for example, 15 V) is applied to the drain of the n-type MOS transistor Tr1.

When the reset pulse RS is applied to the gate of the transistor Tr1, the transistor Tr1 is turned on, and the electric charge accumulated in the floating diffusion FD is discharged to the drain of the transistor Tr1,
The output amplifier 5 is initialized. After the initialization, the charges transferred from the horizontal charge transfer path 4 are accumulated in the floating diffusion FD.

The transistors Tr2 and Tr3 are normally-off n-type MOS transistors, and a drain voltage OD (for example, 15 V) is applied to both drains. The transistors Tr4 and Tr5 are normally-on p-type M
It is an OS transistor and functions as a resistor.

Transistors Tr2, Tr3, Tr4, T
r5 constitutes a source follower amplifier. The voltage input to the gate of the transistor Tr2 is current-amplified and output as the voltage Vout from the source of the transistor Tr3.

The wiring 13 is a wiring connecting the source of the transistor Tr1 and the gate of the transistor Tr2, and has a wiring capacitance C2. A slight gate capacitance C3 exists between the gate and the source of the transistor Tr2.

The output amplifier 5 has capacitors C1, C2, C3. Electric charges are mainly stored in the capacitor C1. Capacity C1
When the electric charge Q is accumulated in the transistor Tr2, a voltage Vin of the following equation is applied to the gate of the transistor Tr2.

Vin = Q / C1 This voltage Vin is amplified by a source follower amplifier and output as a voltage Vout.

The charge Q is generated according to the amount of light received by the photodiode 2 (FIG. 6). When the charge Q has a predetermined value, it is necessary to reduce the capacitances C1, C2, and C3 in order to increase the input voltage Vin (to increase the sensitivity of the output amplifier 5).

FIG. 8 is a timing chart for explaining the operation of output amplifier 5 shown in FIG.

The two-phase driving pulses φH1 and φH2 are pulses for driving the horizontal charge transfer path 4 (FIG. 6). For example, a pulse φH2 is supplied to the last stage of the horizontal charge transfer path 4. When the pulse φH2 is at a low level, the gate between the horizontal charge transfer path 4 and the output amplifier 5 is closed.

When the reset pulse RS goes high, the transistor Tr1 shown in FIG.
1, C2 and C3 are charged to the drain voltage RD. The drain voltage RD of the transistor Tr1 is supplied to the gate of the transistor Tr2. The output voltage Vout is substantially equal to the drain voltage RD. For example, if the drain voltage RD is 15V, the voltage V1 is also 15V.

Next, when the reset pulse RS goes low, the transistor Tr1 turns off. The voltage V2 is applied to the gate of the transistor Tr2. For example,
If the drain voltage RD is 15V, the voltage V2 is 14V
become. The output voltage Vout is also the voltage V2 (for example, 14
V).

Next, when the drive pulse φH2 goes high, the gate between the horizontal charge transfer path 4 and the output amplifier 5 opens, and the capacitors C1, C2 and C3
Is supplied with electric charges (electrons). Capacities C1, C2 and C3
Is discharged, and the output voltage Vout falls from the voltage V2 to V3. The voltage V3 is, for example, 12V. Voltages V2 and V3
Is equivalent to the charge amount (pixel value) photoelectrically converted by the photodiode 2.

FIG. 9 is a plan view of the output amplifier 5 shown in FIG. 7, and FIG. 10 is a sectional view of the output amplifier 5 of FIG. 9 taken along the line AA.

As shown in FIG. 9, the horizontal charge transfer path (HC
CD) 4 is formed as an n-type region in the semiconductor substrate,
Connected to transistor Tr1. Transistor Tr1
Has a source S, a gate G and a drain D. The wiring 16 is connected to the drain D, and the reset drain voltage RD is supplied to the drain D via the wiring 16. A wiring 17 is connected to the gate G, and a reset pulse RS is supplied to the gate G via the wiring 17. The wiring 13 is connected to the source S, and the source S is connected to the gate G of the transistor Tr2 via the wiring 13.

The transistor Tr2 has a drain D, a gate G and a source S. The wiring 15 is connected to the drain D, and the drain voltage OD is supplied to the drain D via the wiring 15. A wiring 14 is connected to the source S,
The source S is connected to the transistors Tr3 and T
r4 (FIG. 7).

As shown in FIG. 10, a p-type well region 11 of a semiconductor substrate (Si substrate) is grounded. In the p-type well region 11, a source S composed of an n-type region is formed. This source S is the source of the transistor Tr1. A diffusion capacitor C1 is formed between the source S of the n-type region and the p-type well region 11. The diffusion capacitance C1 is
This is a so-called floating diffusion FD.

The gate G of the transistor Tr2 is connected to the wiring 1
3 and is coupled to the p-type well region 11 via a gate insulating film (SiO ₂ film) 12a. A gate capacitance C3 is formed between the gate G and the p-type well region 11.

The wiring 13 connects the gate G of the transistor Tr2 and the source S of the transistor Tr1. Wiring 13 is coupled to p-type well region 11 via insulating film 12. A wiring capacitance C2 is formed between the wiring 13 and the p-type well region 11.

[0028]

The wiring length of the wiring 13 (the distance in the horizontal direction in the figure) and the wiring width (the distance in the depth direction in the figure)
Is larger, the wiring capacitance C2 is larger. Therefore, by reducing the wiring length and the wiring width, the wiring capacitance C2
Can be reduced. If the wiring capacitance C2 is reduced, the sensitivity of the output voltage Vout can be increased from the relationship of V = Q / C. That is, in FIG. 8, the difference between the voltages V2 and V3 can be increased.

However, there is a limit in reducing the length and width of the wiring 13, and it is difficult to make the wiring capacitance C2 smaller than a predetermined value. As a result, there is a limit in improving the sensitivity of the output voltage.

An object of the present invention is to provide an output amplifier of a solid-state imaging device capable of converting a charge amount into a voltage with high sensitivity.

[0031]

According to one aspect of the present invention, there is provided a source having a diffusion capacitance capable of storing electric charges,
A first transistor capable of discharging charges accumulated in the diffusion capacitor to a drain according to a gate voltage, and a second transistor having a gate as an input terminal and a source as an output terminal, and An amplifier for inputting and amplifying a voltage corresponding to the received electric charge,
Output amplifier of a solid-state imaging device, comprising: a wiring connecting the gate of the first transistor to the source of the first transistor; and a shielded line connected to the source of the second transistor and arranged along the wiring. Is provided.

The wiring connects the gate of the second transistor and the source of the first transistor. By providing the shield line along the wiring, the capacitance of the wiring can be substantially eliminated. By eliminating the capacitance of the wiring, the voltage can be increased when the charge is a predetermined amount, so that the sensitivity of the output amplifier can be improved.

[0033]

FIG. 1 is an equivalent circuit diagram of an output amplifier 5 of a solid-state imaging device according to an embodiment of the present invention.

In this embodiment, a shield line 18 is provided along the wiring 13. The shield line 18 is connected to the transistor Tr
2 sources. The wiring 13 is shielded from the semiconductor substrate (the horizontal charge transfer path 4 in FIG. 6) by the shield line 18. By shielding the wiring 13, the sensitivity of the output amplifier can be improved. Hereinafter, a specific configuration of the output amplifier 5 will be described.

The diffusion capacitance C1 exists at the source of the transistor Tr1. The diffusion capacitance C1 is a so-called floating diffusion FD,
The charge transferred from FIG. 6 is accumulated. A reset drain voltage RD (for example, 15 V) is applied to the drain of the n-type MOS transistor Tr1.

When the reset pulse RS is applied to the gate of the transistor Tr1, the transistor Tr1 is turned on, and the charges (electrons) accumulated in the floating diffusion FD are discharged to the drain of the transistor Tr1, and the floating diffusion FD (output amplifier) 5) is initialized. After initialization, the horizontal charge transfer path 4
Are transferred to the floating diffusion FD.

The transistors Tr2 and Tr3 are normally-off n-type MOS transistors, and a drain voltage OD (for example, 15 V) is applied to both drains. The transistors Tr4 and Tr5 are normally-on p-type M
It is an OS transistor and functions as a resistor.

Transistors Tr2, Tr3, Tr4, T
r5 constitutes a source follower amplifier. In the source follower amplifier, the input terminal is the gate of the transistor Tr2, and the output terminal is the source of the transistor Tr3. An output voltage Vout is output from the output terminal.
That is, the voltage input to the gate of the transistor Tr2 is current-amplified and output as the voltage Vout from the source of the transistor Tr3.

There is a slight gate capacitance C3 between the gate and the source of the transistor Tr2.

The wiring 13 is a wiring connecting the source of the transistor Tr1 and the gate of the transistor Tr2. One end of the shield line 18 is connected to the source of the transistor Tr2, and is disposed along the wiring 13 to shield the wiring 13.

A capacitance C4 exists between the wiring 13 and the shield line 18, and a capacitance C5 exists between the shield line 18 and the ground level. Due to the characteristics of the transistor Tr2, the gate and the source of the transistor Tr2 have substantially the same potential.

The gate of the transistor Tr2 is connected to the wiring 13, and the source of the transistor Tr2 is the shield line 1.
8 is connected. Therefore, the wiring 13 and the shield wire 1
8 also has substantially the same potential. If the wiring 13 and the shield line 18 have the same potential, no charge is accumulated in the capacitor C4 between the two, so that the capacitor C4 can be ignored.

The capacitance C5 is connected to the shield line 18 and does not affect the wiring 13. That is, the capacitance C5 does not affect the gate voltage of the transistor Tr2.

Since the capacitors C4 and C5 do not affect the output voltage Vout, they can be ignored. The output voltage Vout is equal to the floating diffusion FD (C
1) and the gate capacitance C3.

The output amplifier 5 has capacitors C1 and C3. Charges transferred from the horizontal charge transfer path are accumulated in the capacitors C1 and C3. The capacitance C3 is extremely smaller than the capacitance C1. When the charge Q is accumulated in the capacitor C1, a voltage Vin represented by the following equation is applied to the gate of the transistor Tr2.

Vin = Q / C1 This voltage Vin is amplified by a source follower amplifier and output as voltage Vout.

The output amplifier 5 of FIG. 7 has capacitors C1, C2 and C3. The output amplifier 5 of this embodiment (FIG. 1)
Since it has the capacitances C1 and C3, it is smaller than the capacitances C1, C2 and C3 of the output amplifier 5 of FIG. In the output amplifier 5 of the present embodiment, the wiring capacitance C2 is substantially eliminated.

The voltage V, the charge Q and the capacitance C are given by V = Q / C
Has the relationship When a predetermined amount of charge Q is supplied from the horizontal charge transfer path, the voltage V can be increased as the capacitance C decreases. Therefore, in this embodiment, the sensitivity of the output voltage Vout can be improved by eliminating the wiring capacitance C2 and reducing the capacitance in the output amplifier.

The operation of the output amplifier 5 will be described with reference to FIG. When the reset pulse RS goes high, the transistor Tr1 turns on, as shown in FIG.
The capacitors C1 and C3 are charged to the drain voltage RD.

The drain voltage RD is supplied to the gate of the transistor Tr2. The output voltage Vout becomes substantially the same voltage V1 as the drain voltage RD. For example, if the drain voltage RD is 15V, the voltage V1 is also 15V.

Next, when the reset pulse RS goes low, the transistor Tr1 turns off. The voltage V2 is applied to the gate of the transistor Tr2. The gate capacitance C3 is extremely smaller than the capacitance C1. For example, if the drain voltage RD is 15V, the voltage V2 will be 14V. The output voltage Vout also becomes the voltage V2.

Next, when the drive pulse φH2 goes high, the gate between the horizontal charge transfer path 4 and the output amplifier 5 opens, and charges (electrons) are supplied from the horizontal charge transfer path 4 to the capacitors C1 and C3. You. The capacitors C1 and C3 discharge, and the output voltage Vout decreases from the voltage V2 to V3. Voltage V3
Is, for example, 11V. The difference between the voltages V2 and V3 corresponds to the amount of charge (pixel value) photoelectrically converted by the photodiode 2.

Since there is no wiring capacitance C2 (FIG. 7), the capacitance C
1 increases, and the difference between the voltages V2 and V3 can be increased. That is, the sensitivity of the output amplifier 5 (output voltage Vout) can be improved.

If the sensitivity of the output amplifier 5 is improved, the number of pixels of the solid-state imaging device can be increased, and the size of the solid-state imaging device can be reduced (the semiconductor chip area can be reduced). When the number of pixels is increased or the size of the solid-state imaging device is reduced, the light receiving area of the photodiode 2 (FIG. 6) decreases. Even if the amount of charge generated by the photodiode 2 is small, the sensitivity of the output amplifier 5 is good, so that the amount of charge can be converted to a sufficiently large voltage (V2−V3).

FIG. 2 is a plan view of the output amplifier 5 shown in FIG. FIG. 3 is a cross-sectional view of the output amplifier 5 of FIG. 2 along the line AA.

In this embodiment, the insulating film 22 is
By providing the shield wire 18 via (FIG. 3),
The output voltage sensitivity can be improved. The shield line 18 is connected to the source S of the transistor Tr2.
Hereinafter, a specific configuration of the output amplifier 5 will be described.

As shown in FIG. 2, the horizontal charge transfer path (HC
CD) 4 is formed as an n-type region in the semiconductor substrate,
Connected to transistor Tr1. The n-type MOS transistor Tr1 has a source S, a gate G, and a drain D. The wiring 16 is connected to the drain D, and the reset drain voltage RD is supplied to the drain D via the wiring 16. A wiring 17 is connected to the gate G, and a reset pulse RS is supplied to the gate G via the wiring 17. The wiring 13 is connected to the source S, and the source S is connected to the wiring 13
To the gate G of the transistor Tr2.

The n-type MOS transistor Tr2 has a drain D, a gate G and a source S. A wiring 15 is connected to the drain D, and the drain voltage O
D is supplied to the drain D. A wiring 14 is connected to the source S, and the source S is connected to the transistor T via the wiring 14.
r3 and Tr4 (FIG. 1).

The shield line 18 is connected to the source S of the transistor Tr2, and is provided below the wiring 13 via an insulating layer 22 (FIG. 3). The shield wire 18 is
From the ground level.

It is preferable that the shield wire 18 covers as much area as possible of the portion where the wiring 13 is projected downward.
However, for reasons of the characteristics of the transistors Tr1 and Tr2 or restrictions on the manufacturing process, the transistors Tr1 and Tr2
It is preferable that the shield wire 18 is not provided near r2.

As shown in FIG. 3, a semiconductor substrate (for example, S
The p-type well region 11 of the (i-substrate) is grounded. In the p-type well region 11, a source S composed of an n-type region is formed. This source S is the source of the transistor Tr1. A diffusion capacitance C1 exists between the source S of the n-type region and the p-type well region 11. The diffusion capacitance C1 is
This is a so-called floating diffusion FD.

The gate G of the transistor Tr2 is connected to the wiring 1
3 and a gate insulating film (eg, SiO ₂ film) 12
It is coupled to p-type well region 11 through a. A gate capacitance C3 is provided between the gate G and the p-type well region 11.
Exists.

The wiring 13 connects the gate G of the transistor Tr2 and the source S of the transistor Tr1. Wiring 13 is coupled to shield line 18 via insulating film 22. A capacitance C4 exists between the wiring 13 and the shield line 18.

As described with reference to FIG. 1, the gate G and the source S of the transistor Tr2 have substantially the same potential. Since the gate G is connected to the wiring 13 and the source S is connected to the shield line 18, the wiring 13 and the shield line 18 have substantially the same potential.

If both are at the same potential, no charge is stored in the capacitor C4, so that the capacitor C4 can be ignored. Even if charges are transferred from the horizontal charge transfer path 4 (FIG. 2), no charges are accumulated in the capacitor C4.

The shield wire 18 is connected to the p
It is coupled to the mold well region 11. A capacitance C5 exists between the shield line 18 and the p-type well region 11. Since the capacitor C5 is connected to the shield line 18, it does not affect the wiring 13. The output of the output amplifier 5 is not affected by the capacitance C5. The capacitances C4 and C5 have no effect on the output of the output amplifier 5, so that the capacitances C4 and C5 can be ignored.

In the output amplifier 5 of FIG. 10, the wiring 13 has the wiring capacitance C2, but in the output amplifier 5 of FIG.
The capacitance of the wiring 13 can be substantially eliminated. By eliminating the capacitance of the wiring capacitance 13, the sensitivity of the output amplifier can be improved.

In FIG. 3, a microlens layer 23 is formed on wiring 13. The microlens layer 23 is formed of, for example, a synthetic resin. Next, the micro lens layer 23
The microlens formed by will be described.

FIG. 4A is an enlarged plan view of the photodiode 2 of the solid-state imaging device shown in FIG. 6 and the vertical charge transfer paths 3 on both sides thereof. FIG. 4B is a plan view of FIG. 3B
It is sectional drawing which follows the -3B line.

On the surface of the p-type well region 11, an n-type region 24 forming the photodiode 2 and an n-type region 25 forming the vertical charge transfer path 3 are formed. Between the n-type region 24 and the n-type region 25 to the left of the n-type region 24, ap ⁺ -type region 20 constituting a channel stop region is formed.
The channel stop region 20 prevents the charge generated by the photodiode 2 from leaking to the left vertical charge transfer path 3.

N-type region 25 constituting vertical charge transfer path 3
A shift gate electrode 28 is formed on the substrate with an insulating film 27 interposed therebetween. When a positive potential is applied to the shift gate electrode 28, the charges generated by the photodiode 2 are transferred to the vertical charge transfer path 3 on the right.

First metal layer 29 and second metal layer 30
Is a light shielding film. The light shielding film 30 is formed of the photodiode 2
Cover other than the opening 31. Since the light shielding film 30 is a thin film, the light shielding film 29 enhances the light shielding of the vertical charge transfer path 3.

The microlens layer 23 is formed on the surface of the solid-state image sensor, and forms a microlens 23 a above the photodiode 2. The micro lens 23a condenses the external light 32 and guides it to the opening 31. The photodiode 2 receives the external light 32 via the opening 31 and generates an electric charge.

When a positive potential is supplied to the shift gate electrode 28, charges generated by the photodiode 2 are transferred to the vertical charge transfer path 3. The charge on the vertical charge transfer path 3 is
It is supplied to an output amplifier via a horizontal charge transfer path.

The microlens layer 23 shown in FIG.
This is the same layer as the microlens layer 23 of FIG. FIG.
Since the microlens layer 23 is made of, for example, a synthetic resin, its surface may be charged. Then, the microlens layer 23 has the capacitance C6. Capacity C
6 is connected to the wiring 13, so that the sensitivity of the output amplifier 5 is reduced.

Micro lens 2 on photodiode 2
If the microlens layer 23b (the area within the broken line in the drawing) on the wiring 13 is removed while leaving 3a, the capacitance C6 disappears,
The sensitivity of the output amplifier 5 can be improved. next,
A method for improving the sensitivity of the output amplifier 5 without removing the microlens layer 23 will be described.

FIG. 5 is a sectional view of an output amplifier 5 according to another embodiment of the present invention. In the output amplifier 5 of the present embodiment, the wiring 13 and the portion below it are the same as the output amplifier 5 shown in FIG. Wiring 13
Is covered with an insulating film 41.

The shield line 42 is coupled to the wiring 13 via the insulating film 41, and shields the wiring 13 from the microlens layer 23. Since the shield line 42 is connected to the source S (FIG. 2) of the transistor Tr2, similarly to the shield line 18, the shield line 42 and the wiring 13 have substantially the same potential.

The microlens layer 23 has a shield wire 42
Cover the surface. Between the wiring 13 and the shield wire 42,
There is a capacitance C7. A capacitance C8 exists between the shield line 42 and the surface of the microlens layer 23.

The wiring 13 and the shield line 42 have substantially the same potential, and no charge is stored in the capacitor C7.
7 can be ignored.

Since the capacitor C8 is connected to the shield line 42, it does not affect the wiring 13. Regarding the output of the output amplifier 5, the capacitors C7 and C8 can be ignored.

According to this embodiment, the two shielded wires 18
And 42 shield the wiring 13. Shield wire 18
Shields the wiring 13 from the grounded p-type well region 11. The shield line 42 shields the wiring 13 from the surface potential of the microlens layer 23. By shielding the wiring 13, the capacitance of the wiring 13 can be substantially eliminated, and the sensitivity of the output amplifier 5 can be improved.

The microlens layer 23 for forming the microlenses 23a is not always necessary, but it is preferable to form the microlenses 23a in order to increase the optical sensitivity.

Instead of the microlens layer 23, a color filter layer may be provided, or both a microlens layer and a color filter layer may be provided. The color filter layer is a filter that allows only light of a predetermined wavelength to pass.
By forming the color filter layer, a color image can be captured. Also in the case of forming the color filter layer, the sensitivity of the output amplifier 5 can be improved as in the case of the micro lens layer 23.

Next, a method of manufacturing the output amplifier 5 shown in FIG. 5 will be described. The SiO ₂ film 12 is formed, for example, by forming a film by a CVD method and patterning the film by photolithography and etching. SiO ₂ film 1
The film thickness of No. 2 is, for example, 600 nm.

The shield line 18 is a first polysilicon layer and is formed by a CVD method. The film thickness of the shield wire 18 is 370 nm.

The SiO ₂ film 22 is formed by thermally oxidizing the surface of the shield wire 18. The thickness of the SiO ₂ film 22 is, for example, 150 nm.

The wiring layer 13 is a second polysilicon layer and is formed by a CVD method. The thickness of the wiring layer 13 is
For example, it is 370 nm. The first polysilicon layer 18 and the second polysilicon layer 13 are formed in the same step as the formation of the two-layer superposed electrode on the vertical charge transfer path.

The insulating film 41 is a laminated film of a SiO ₂ film (150 nm) formed by thermally oxidizing the surface of the wiring layer 13 and a PSG film (400 nm) formed by the CVD method.

The shield wire 42 is a first metal layer such as Al or W, and is formed by, for example, a sputtering method. The first metal layer 42 is formed in the same step as the step of forming the first metal layer 29 in FIG.

The microlens layer 23 is formed by spin-coating a synthetic resin with a spinner. The thickness of the microlens layer 23 is, for example, 2 μm from the surface of the substrate (p-type well region 11).

Although the method of manufacturing the output amplifier 5 shown in FIG. 5 has been described above, the output amplifier 5 shown in FIG. 3 can be manufactured by a similar method.

According to the present embodiment, the wiring 1 is shielded by the shield wires 18 and / or 42, so that the wiring 1
3 can be substantially eliminated, and the sensitivity of the output amplifier 5 can be improved.

If the sensitivity of the output amplifier 5 is improved, the number of pixels of the solid-state imaging device can be increased, and the size of the solid-state imaging device can be reduced (the semiconductor chip area can be reduced).

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0096]

As described above, according to the present invention,
By providing a shield line along a wiring connecting the gate of the second transistor and the source of the first transistor, the capacitance of the wiring can be substantially eliminated. By eliminating the capacitance of the wiring, the voltage can be increased when the charge is a predetermined amount, so that the sensitivity of the output amplifier can be improved.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of an output amplifier of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a plan view of an output amplifier of the solid-state imaging device according to the embodiment.

FIG. 3 is an AA diagram of an output amplifier of the solid-state imaging device shown in FIG. 2;
It is sectional drawing which follows a line.

FIG. 4A is a plan view of a photodiode and a vertical charge transfer path, and FIG. 4B is a plan view of FIG.
It is sectional drawing which follows the 3B line.

FIG. 5 is a sectional view of an output amplifier of a solid-state imaging device according to another embodiment of the present invention.

FIG. 6 is a plan view of the solid-state imaging device.

FIG. 7 is an equivalent circuit diagram of an output amplifier of a conventional solid-state imaging device.

FIG. 8 is a timing chart for explaining the operation of the output amplifier of the solid-state imaging device.

FIG. 9 is a plan view of an output amplifier of a conventional solid-state imaging device.

10 is a diagram illustrating A- of the output amplifier of the solid-state imaging device illustrated in FIG. 9;
It is sectional drawing which follows the A line.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 solid-state imaging device 2 photodiode 3 vertical charge transfer path 4 horizontal charge transfer path 5 output amplifier 11 p-type well region 12 insulating film 13, 14, 15, 16, 17 wiring 18 shield line 20 p ⁺ type region 22 insulating film 23 Microlens layer 23a Microlens 24, 25 n-type region 27 Insulating film 28 Shift gate electrode 29 First metal layer (shielding film) 30 Second metal layer (shielding film 31 Opening 32 External light 41 Insulating film 42 Shield wire

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA10 AB01 BA10 CA03 DB06 DB08 DC05 DD09 DD12 FA06 FA35 GB11 GB15 GB17 GD04 5C024 AA00 CA12 DA01 EA04 EA08 FA01 GA01 GA03 GA11 GA23 GA26 GA27 GA31 GA41

Claims (2)

[Claims] 1. A first transistor including a first source having a diffusion capacitance capable of accumulating charge, and discharging the charge accumulated in the diffusion capacitance to a drain according to a voltage of a first gate. An amplifier including a second transistor having a second gate as an input terminal and a second source as an output terminal, for inputting and amplifying a voltage corresponding to the charge accumulated in the diffusion capacitance; A wiring connecting the second gate of the second transistor to the first source of the first transistor; and a wiring connected to the second source of the second transistor and arranged along the wiring. An output amplifier of a solid-state imaging device having a shield line. 2. The output amplifier of a solid-state imaging device according to claim 1, wherein said shield line is formed below said wiring or above and below said wiring.