JP2000049283A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, wherein the current consumption difference due to the trimming difference of a reference potential can be reduced, and in a semiconductor device which steps down the power voltage, the operation at the time of power switch on can be stabilized, and required reference potential can be surely generated. SOLUTION: A reference potential Vbgr generated by a BGR circuit 11 is fed to an inversion input of a differential amplifier OP. The gate of a PMOS transistor P1 having a source connected to an external power source is connected to the output of the differential amplifier OP, and the drain of the PMOS transistor P1 is connected to a node N1. A resistor Raf and variable resistors Ra which are controllable according to trimming signals S1,..., Sn are connected in parallel between the nodes N1, N2. A resistor Rb is connected between the node N2 and ground, the node N2 is connected to a non-inverting input of the differential amplifier OP, and a trimmed reference potential Vref is outputted from the node N1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, for example, and more particularly to a power supply of a semiconductor memory device.
The present invention relates to a trimming circuit for trimming a reference potential generated by a BGR (Band Gap Reference) circuit to a required potential.

[0002]

2. Description of the Related Art In a semiconductor memory device such as a nonvolatile memory, a required voltage is generated by increasing or decreasing a power supply voltage in the semiconductor memory device. In order to set a voltage generated in the semiconductor memory device such as the boosted voltage to a predetermined potential, a reference voltage independent of a power supply voltage and a temperature is required.

The BGR circuit is a circuit for generating such a reference voltage, and outputs a reference voltage of about 1.2 V. However, there is a possibility that the output voltage of the BGR circuit shifts due to process variations. The variation of the output voltage is about 0.1 V. When a potential of, for example, 24 V is generated using this reference potential,
The variation in the potential of 24 V is amplified to 0.1 × 24 / 1.2 = 2 (V), which is an unacceptable level.

Also, due to the nature of a circuit using a reference potential, a reference potential other than 1.2 V (for example, 1 V
Or 1.5 V) may be required. Therefore, a reference potential trimming circuit for converting a reference potential created by the BGR circuit is required.

FIG. 10 shows a conventional reference potential trimming circuit. This circuit is used for a non-volatile memory that does not lower the power supply voltage, and generates a reference potential Vref (= 1.5 V) based on a voltage Vbgr (about 1.2 V) output from the BGR circuit 101. This reference potential trimming circuit includes a differential amplifier OP and a P-channel MOS transistor (hereinafter referred to as PMO
S1) P1, resistor Ra, this resistor Ra
Variable resistor Rb connected to, a trimming signal generating circuit 1
02 output signals T1 to Tn (n = 2 ^m , m = positive integer)
, A decoder 103 for switching the variable resistor Rb according to the above, a monitor pad 104, and capacitors C1 to C4. The resistor Ra is connected between the nodes N1 and N2, and the variable resistor Rb is connected between the node N2 and ground. An external power supply voltage Vext is supplied to each circuit.

In such a configuration, the reference potential Vref has the relationship shown in equation (1). Vref = (Ra + Rb) · Vbgr / Rb (1) When trimming the reference potential Vref, the value of the reference potential Vref is monitored from the monitoring pad 104, and the value of the variable resistor Rb is adjusted so that the reference potential Vref becomes 1.5V. Adjust it. The trimming of the resistor Rb is performed by cutting a fuse (not shown) in the trimming signal generating circuit 102. That is, when the state of the fuse is determined by cutting the fuse, the decoder 103 decodes the signals T1 to Tn output from the trimming signal generation circuit 102 in accordance with the state of the fuse.
As a result, one of the output signals S1 to Sn of the decoder 103 becomes high level. According to the high level output signal, one of a plurality of N-channel MOS transistors (hereinafter, referred to as NMOS transistors) constituting the variable resistor Rb is turned on, and the value of the variable resistor Rb is determined. . For example, when the signal Sj is at the high level, the value of the resistor Rb is as shown in the equation (2).

[0007]

(Equation 1)

[0008]

The conventional reference potential trimming circuit has a problem when used in the following manner. The first problem is that the voltage Vbgr = 1.2
This is a case where trimming is performed in the vicinity of V. In this case, the value of the current flowing through the path of the resistor Ra and the variable resistor Rb greatly changes depending on the trimming state. This is node N
This is because the variable resistor Rb away from 1 has been changed. In order to quantitatively observe the amount of change in the current, consider a case in which a reference potential Vref of 1.5 V is generated from the output voltage Vbgr of the BGR circuit 101 which fluctuates in a range of 1.1 V to 1.3 V. From equation (1), Vbgr = 1.1 V
In the case of Vref = 1.5V, the variable resistor Rb
Needs to be Rb = 2.75Ra. When the output voltage Vbgr of the BGR circuit 101 is 1.3 V, the value of the variable resistor Rb needs to be Rb = 6.5 Ra in order to set Vref = 1.5 V. Therefore, when the combined resistance R = Ra + Rb is Vbgr = 1.1 V, R = 3.75 Ra, Vbg
When r = 1.3V, R = 7.5Ra.

The current flowing through the paths of the resistors Ra and Rb is I =
Vref / R. Therefore, when Vbgr = 1.1 V, twice the current flows when Vbgr = 1.3 V. The difference between the two becomes even greater when the values of Vbgr and Vref are close. When the current value changes, the response characteristic of the feedback system including the differential amplifier OP, the PMOS transistor P1, and the resistor changes. For this reason, depending on the trimming value, the response is too fast and the value of the reference potential Vref rapidly increases,
Alternatively, on the contrary, the response is too slow and the reference potential Vref
Can rise slowly. In addition, when the trimming circuit is operated from the standby state, the standby current changes depending on the trimming value, which is not preferable.

The second problem occurs when this trimming circuit is applied to a semiconductor memory device which generates a required voltage by stepping down a power supply voltage. In a method of generating an internal power supply potential by stepping down an external power supply voltage by a step-down circuit, an internal power supply potential is used as a power supply for a logic circuit including the trimming signal generation circuit 102 and the decoder 103. If the power supply of the logic circuit is an external power supply, the hot electron resistance of the transistors constituting the logic circuit deteriorates. Therefore, when the circuit as shown in FIG. 10 is applied, it is necessary to supply the internal power supply voltage Vint to the trimming signal generation circuit 102 and the decoder 103 as shown in FIG. However, a step-down circuit (not shown) generates an internal power supply voltage based on the reference potential Vref generated by the trimming circuit. Therefore, the following problem occurs when the power is turned on. First, when the external power supply voltage rises, the BGR circuit 101 and the differential amplifier OP using this as a power supply operate. However, at this stage, the internal power supply voltage has not yet been generated. Therefore, the output levels of the trimming signal generation circuit 102 and the decoder 103 are not fixed, and are in a state close to 0V. Therefore, the reference potential Vref is not determined. But,
The step-down circuit attempts to generate an internal power supply voltage based on the uncertain reference potential. For this reason, it takes time until the internal power supply voltage is determined, or the internal power supply voltage does not increase in the worst case. For the above reasons, the circuit configuration shown in FIG. 11 cannot be applied to a semiconductor memory device that steps down a power supply voltage.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to reduce a difference in current consumption due to a difference in reference potential trimming. It is an object of the present invention to provide a semiconductor device that steps down a voltage, stabilizes the operation at the time of power-on, and can surely generate a required reference potential.

[0012]

According to the present invention, there is provided a semiconductor device for generating an internal power supply voltage to be supplied to an internal circuit by reducing an external power supply voltage supplied from the outside. A reference potential generating means for generating a potential, a trimming signal generating means for generating a trimming signal for trimming the reference potential generated by the reference potential generating means, and a reference potential generating means at a first input terminal. A differential amplifier to which the reference potential is input, the external power supply voltage is supplied to one end of a current path, a gate is connected to an output terminal of the differential amplifier, and the other end of the current path is connected to a first terminal. A connected MOS transistor, a first resistor connected between the first terminal and the second terminal,
A second resistor connected between the second terminal and ground; and a third resistor connected in parallel with the first resistor, the resistance value of which is changed in accordance with an output signal of the trimming signal generator. And the second terminal is a second terminal of the differential amplifier.
And outputs the trimmed reference potential from the first terminal.

According to another aspect of the present invention, there is provided a semiconductor device for generating an internal power supply voltage to be supplied to an internal circuit by lowering an external power supply voltage supplied from the outside, comprising: a reference potential generating means for generating a reference potential; Trimming signal generating means for generating a trimming signal for trimming the reference potential generated by the reference potential generating means; and a differential amplifier having a first input terminal to which the reference potential generated by the reference potential generating means is input. The external power supply voltage is supplied to one end of a current path, a gate is connected to the output terminal of the differential amplifier,
A MOS transistor having the other end of the current path connected to a first terminal, a first resistor connected between the first terminal and the second terminal, and a connection between the second terminal and ground. And a third resistor connected in parallel with the first resistor, the resistance of which is changed in accordance with an output signal of the trimming signal generator. The first terminal Is connected to a second input terminal of the differential amplifier, and outputs a trimmed reference potential from the second terminal.

Further, the present invention is a semiconductor device for generating an internal power supply voltage to be supplied to an internal circuit by stepping down an external power supply voltage supplied from the outside, comprising: a reference potential generating means for generating a reference potential; Trimming signal generating means for generating a trimming signal for trimming the reference potential generated by the reference potential generating means; and a differential amplifier having a first input terminal to which the reference potential generated by the reference potential generating means is input. A MOS transistor having one end of a current path supplied with the external power supply voltage, a gate connected to the output terminal of the differential amplifier, and the other end of the current path connected to a first terminal; Connected between a terminal and a second terminal, the resistance value of which is changed in accordance with an output signal of the trimming signal generating means 1 of the resistor, the second terminal is connected between the ground, the resistance value and a second resistor which is varied in response to an output signal of the trimming signal generator hand throw,
The first terminal is connected to a second input terminal of the differential amplifier, outputs a trimmed reference potential from the second terminal, and outputs a reference value of a resistance value of the first resistor and a resistance value of the second resistor. The sum is constant regardless of the output signal of the trimming signal generating means.

Further, the present invention is a semiconductor device for generating an internal power supply voltage to be supplied to an internal circuit by stepping down an external power supply voltage supplied from the outside, comprising: a reference potential generating means for generating a reference potential; Trimming signal generating means for generating a trimming signal for trimming the reference potential generated by the reference potential generating means; and a differential amplifier having a first input terminal to which the reference potential generated by the reference potential generating means is input. The external power supply voltage is supplied to one end of a current path, a gate is connected to the output terminal of the differential amplifier,
The other end of the current path is connected to a MOS transistor connected to a first terminal, and is connected between the first terminal and the second terminal, and has a resistance value changed in accordance with an output signal of the trimming signal generator. And a second resistor connected between the second terminal and ground, the second resistor having a resistance value changed in accordance with an output signal of the trimming signal generator. Is connected to a second input terminal of the differential amplifier, and outputs a trimmed reference potential from the first terminal. The sum of the resistance values of the first resistor and the second resistor is equal to the trimming value. It is constant regardless of the output signal of the signal generating means.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. 2 and 3 show a power supply circuit of a semiconductor device to which the present invention is applied. 2, the external power supply power-on detection circuit 21 is supplied with an external power supply voltage Vext. The external power supply power-on detection circuit 21 detects an external power supply voltage and outputs a signal LVc.
cn is output. This signal LVccn is equal to the external power supply voltage V
When ext is equal to or lower than a predetermined level, it is at a low level, and when power is turned on and the external power supply voltage Vext is equal to or higher than a predetermined level, it is at a high level.

The internal power supply power-on detection circuit 22 has an internal power supply voltage V
int is supplied. The internal power supply power-on detection circuit 22 outputs a signal LVdd according to the level of the internal power supply voltage Vint. When the internal power supply voltage Vint is lower than a predetermined level, the signal LVdd is at a low level, and when the internal power supply voltage Vint is higher than a predetermined level, the signal LVdd is at a high level. The signal LVdd and the signal LVccn output from the external power supply power-on detection circuit 21 are supplied to the NAND circuit 23. An inverter circuit 24 is connected to an output terminal of the NAND circuit 23. The NAND circuit 23 and the inverter circuit 24 are supplied with the internal power supply voltage Vint. A signal LVddn is output from the output terminal of the inverter circuit 24. This signal LVddn is used when the external power supply voltage Vext and the internal power supply voltage Vint are lower than a predetermined level, and when the external power supply voltage Vext is higher than a predetermined level and the internal power supply voltage Vint is lower than a predetermined level.
It is at a low level according to cn and LVdd. Further, when the internal power supply voltage Vint becomes higher than a predetermined level, the signal LVddn becomes high level.

In FIG. 3, a reference potential trimming circuit 31 including a BGR circuit 11 has an external power supply voltage Ve.
xt is supplied. The reference potential trimming circuit 31 includes the external power supply power-on detection circuit 21.
Thus, the signal LVccn is supplied. The reference voltage Vref output from the reference potential trimming circuit 31 is supplied to a step-down circuit 32 and a step-up circuit 33. The step-down circuit 32 has a reference voltage Vref.
, The external power supply voltage Vext is reduced to generate the internal power supply voltage Vint. The booster circuit 33 boosts the external power supply voltage Vext based on the reference voltage Vref to generate a predetermined voltage.

The internal power supply voltage Vint generated by the step-down circuit 32 is supplied to a trimming signal generating circuit 34 for generating a trimming signal. The signal LVddn is supplied to the trimming signal generating circuit 34. The trimming signal generating circuit 34 outputs the signal LVd
A trimming signal of the level of the internal power supply voltage Vint is generated according to dn. This trimming signal is decoded by the decoder 35. The decoded trimming signals S1, S2,... Sn are supplied to the level shifter 36. The level shifter 36 shifts the level of each trimming signal from the internal power supply voltage Vint to the external power supply voltage Vext. The trimming signals S1 to Sn whose levels have been converted by the level shifter 36 are supplied to the reference potential trimming circuit 31. The trimming signal generating circuit 34 is configured to generate a trimming signal according to, for example, a fuse or a command (not shown).

FIG. 4 shows an example of a circuit configuration of the level shifter 36. This level shifter 36 is a PMOS transistor 3 driven by an external power supply voltage Vext.
6a and 36b, NMOS transistors 36c and 36d driven by the internal power supply voltage Vint, and an inverter circuit 36e. This circuit is provided, for example, in the same number as the number of trimming signals, and the level of each trimming signal can be shifted.

FIG. 1 shows a configuration of the reference potential trimming circuit according to the first embodiment of the present invention. The external power supply voltage Vext is supplied to the BGR circuit 11 from a power supply terminal 12 to which the external power supply voltage Vext is supplied via a low-pass filter LPF. The low-pass filter LPF includes a resistor R31 and a capacitor C1. The output terminal of the BGR circuit 11 is grounded via a capacitor C2 and the differential amplifier OP
Is connected to the inverting input terminal of The non-inverting input terminal of the differential amplifier OP is grounded via the capacitor C3, and the output terminal is connected to the gate of the PMOS transistor P1. The source of the PMOS transistor P1 is connected to the output node N3 of the low-pass filter LPF, and the gate and the drain are connected via a capacitor C5. The PMOS transistor P2 is connected in parallel to the PMOS transistor P1. A signal LVccn output from the external power supply power-on detection circuit 21 is supplied to the gate of the PMOS transistor P2.

The drain (node N1) of the PMOS transistor P1 is grounded via a variable resistor Ra and a resistor Rb, and a connection node N between the variable resistor Ra and the resistor Rb.
2 is connected to the non-inverting input terminal of the differential amplifier OP. The trimming signals S1, S2 to Sn output from the level shifter 36 are supplied to the variable resistor Ra. Further, a resistor Raf is connected in parallel to the variable resistor Ra. A reference voltage Vref is output from the connection node N1. A capacitor C4 is connected between the connection node N1 and the ground.
1 is connected to a monitoring pad 13 for monitoring a voltage.

The capacitors C1 to C4 are capacitors for stabilizing a voltage, and the capacitor C5 is a capacitor for phase compensation. The trimming circuit shown in the first embodiment has a BGR
The voltage Vbgr output from the circuit 11, for example, about 1.2
A higher reference voltage Vref, for example 1.5 V, is generated from V. The main difference from the conventional example shown in FIGS. 10 and 11 is that a variable resistor Ra is connected between nodes N1 and N2, and a resistor R is connected in parallel with the variable resistor Ra.
af is connected.

FIG. 5A shows an example of the variable resistor Rb. This variable resistor Ra is composed of a resistor R1 and an NMOS.
A series circuit of a transistor N1, a series circuit of a resistor R2 and an NMOS transistor N2, and a series circuit of a resistor Rn and an NMOS transistor Nn are connected in parallel with each other. Each N
The gates of the MOS transistors N1, N2,... Nn have trimming signals S output from the level shifter 36.
1, S2... Sn are supplied.

FIG. 5B shows another example of the variable resistor Ra. This variable resistor Ra is similar to the circuits shown in FIGS. 10 and 11, and includes resistors R1 and R2 connected in series.
Rn are connected in parallel between the connection nodes of... Rn and ground, and the gates of the NMOS transistors N1, N2... Nn receive the trimming signals S1, S2. Supplied.

According to the first embodiment, the resistor Ra in the equation (1) is trimmed. Therefore, the fluctuation of the current value due to the difference of the trimming signal can be small. For example, as described above, considering the case where the reference voltage Vref of 1.5 V is generated from the voltage Vbgr fluctuating in the range of 1.1 V to 1.3 V, the voltage Vbgr =
At 1.1V, R = 1.36Rb, voltage Vbgr = 1.
Since R = 1.15Rb at 3V, the difference between the two current values is 18%, which is smaller than the conventional example. However, when the resistance between the nodes N1 and N2 is made variable,
Care must be taken so that the transfer potential does not decrease by the threshold voltage due to the NMOS transistor in FIG. 5A or FIG. 5B. In the first embodiment, the level of the signal output from the trimming signal generation circuit 34 is shifted by the level shifter 36 and the high level is set to the external power supply potential Vext in order to avoid the decrease in the threshold voltage.
Therefore, a decrease in the threshold voltage of the NMOS transistor can be prevented.

Next, the operation at the time of turning on the power in the first embodiment will be described with reference to FIGS. 1, 2 and 3. FIG. First, the external power supply voltage Vext rises, and when this level becomes equal to or higher than the detection level of the external power supply power-on detection circuit 21, the output signal LVccn changes from a low level to a high level. The PMOS transistor P2 shown in FIG. 1 is turned off from on as the signal LVccn changes from low level to high level. Signal LVccn
With the above change, the BGR circuit 11 starts up, and the voltage Vbgr is determined. At this time, the internal power supply potential Vint has not yet been generated, and the trimming signals S1, S2,... Sn shown in FIG. However, the reference voltage Vref becomes as shown in Expression (3) by the variable resistor Rb and the resistor Raf connected in parallel.

Vref = (Raf + Rb) Vbgr / Rb (3) The difference between this provisional reference voltage (referred to as Vrefp) and the final reference voltage Vref adjusts the distribution between Raf and the variable resistor Rb. By doing so, it can be made smaller. The step-down circuit 32 generates an internal power supply voltage based on the temporary reference voltage Vrefp. When the internal power supply voltage becomes equal to or higher than the detection level of the internal power supply power-on detection circuit 22, the output signal LVddn changes from a low level to a high level. The output of the trimming signal generation circuit 34 is determined by this signal LVddn, and the trimming signal is input to the reference potential trimming circuit 31 via the decoder 35 and the level shifter 36. As a result, the reference potential trimming circuit 31 corrects the value of the provisional reference voltage Vrefp and outputs the final reference voltage Vref.

According to the first embodiment, the node N
A variable resistor Ra is arranged between 1 and N2. For this reason, even when the value of the variable resistor is changed according to the difference in the reference potential serving as the reference, the difference in current consumption can be reduced.

Further, the provisional reference voltage Vrefp is output even when the internal power supply voltage is not output. Therefore, the operation from when the power is turned on until the final values of the internal power supply voltage and the reference voltage are determined can be stabilized.

Next, a second embodiment of the present invention will be described. In the first embodiment, the case where the value of the reference potential Vref is made larger than Vbgr using the circuit shown in FIG. 1 has been described. On the other hand, in the second embodiment, the value of the reference potential Vref is set to Vbg.
The case where a voltage smaller than r, for example, Vref = 1.0 V is generated is shown.

FIG. 6 shows a second embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described. 6 differs from FIG. 1 in that the connection relationship between nodes N1 and N2 is different. That is, the capacitor C3 is connected to the node N1, and the capacitor C4 and the monitor pad 13 are connected to the node N2.
Is connected. Reference voltage Vref is output from node N2. The operation of the circuit shown in FIG. 6 is the same as that of FIG.

With such a configuration, the BGR circuit 11
Reference voltage Vre lower than the output voltage Vbgr of
f can be generated. FIG. 7 shows a third embodiment of the present invention. The same parts as those in FIG. 6 are denoted by the same reference numerals, and only different parts will be described. In this embodiment,
A first variable resistor VR1 is provided between nodes N1 and N2.
R11... R1n and n NMOSs
A series circuit of transistors N11 to N1n is connected in parallel. The gates of the NMOS transistors N11 to N1n are supplied with trimming signals S1 to Sn. A series circuit of n resistors R21... R2n and n NMOS transistors N21... N21n forming a second variable resistor VR2 is connected in parallel between the node N2 and the ground. The gates of the NMOS transistors N21 to N2n are supplied with trimming signals S1 to Sn.

According to the third embodiment, the combined resistance of the first variable resistor VR1 and the resistor Raf and the second variable resistor V
By determining the value of the variable resistor so that the sum of the combined resistance of R2 and the resistor Rb becomes constant, it is possible to eliminate a difference in current consumption due to a difference in trimming. That is, by determining the combined resistance so that the following equation is satisfied, the current consumption in different trimmings can be made equal.

R1j · Raf / (R1j + Raf) + R
2j · Rb / (R2j + Rb) = constant (j = 1... N) FIG. 8 shows a fourth embodiment of the present invention. 4th
Is a combination of the circuit shown in FIG. 1 with a first variable resistor VR1 and a second variable resistor VR2 shown in FIG. 7, and the same parts as those in FIGS. With
Description is omitted. Even with such a configuration, the same effect as that of the third embodiment can be obtained.

FIG. 9 shows a fifth embodiment of the present invention, in which the configuration shown in FIG. 7 is applied to a semiconductor device of a system that does not lower the power supply voltage. In this case, the resistors constituting the resistance values of the first variable resistor VR1 and the second variable resistor VR2 may be set such that R1j + R2j = constant (j = 1... N). The present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the spirit of the invention.

[0037]

As described above in detail, according to the present invention, it is possible to reduce the difference in current consumption due to the difference in the reference potential trimming. It is possible to provide a semiconductor device capable of stabilizing an operation at the time of turning on and capable of reliably generating a required reference potential.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a power supply circuit of a semiconductor device to which the present invention is applied;

FIG. 3 is a configuration diagram showing a power supply circuit of a semiconductor device to which the present invention is applied;

FIG. 4 is a circuit diagram showing an example of the level shifter shown in FIG. 3;

5 (a) and 5 (b) are circuit diagrams showing examples of the variable resistor shown in FIG. 1, respectively.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a conventional reference potential trimming circuit.

FIG. 11 is a circuit diagram showing another example of a conventional reference potential trimming circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... BGR circuit, OP ... Differential amplifier, P1 ... PMOS transistor, Raf, Rb ... Resistance, Ra, VR1, VR2 ... Variable resistance, 21 ... External power supply power-on detection circuit, 22 ... Internal power supply power-on detection circuit, 31 ... Reference potential trimming circuit, 32 ... Step-down circuit, 33 ... Boost circuit, 34 ... Trimming signal generation circuit, 36 ... Level shifter, Vext ... External power supply voltage, Vint ... Internal power supply voltage.

Claims (6)

[Claims] 1. A semiconductor device for generating an internal power supply voltage to be supplied to an internal circuit by lowering an external power supply voltage supplied from the outside, comprising: a reference potential generating means for generating a reference potential; and the reference potential generating means. A trimming signal generating means for generating a trimming signal for trimming the reference potential generated by the reference potential generator; a differential amplifier having a first input terminal receiving the reference potential generated by the reference potential generating means; A MOS transistor having one end supplied with the external power supply voltage, a gate connected to the output terminal of the differential amplifier, and the other end of the current path connected to a first terminal; A first resistor connected between the first and second terminals; a second resistor connected between the second terminal and a ground; And a third resistor having a resistance value changed in accordance with an output signal of the trimming signal generating means, wherein the second terminal is connected to a second input terminal of the differential amplifier. And outputting a trimmed reference potential from the first terminal. 2. A semiconductor device for generating an internal power supply voltage to be supplied to an internal circuit by stepping down an external power supply voltage supplied from the outside, comprising: a reference potential generating means for generating a reference potential; and the reference potential generating means. A trimming signal generating means for generating a trimming signal for trimming the reference potential generated by the reference potential generator; a differential amplifier having a first input terminal receiving the reference potential generated by the reference potential generating means; A MOS transistor having one end supplied with the external power supply voltage, a gate connected to the output terminal of the differential amplifier, and the other end of the current path connected to a first terminal; A first resistor connected between the first and second terminals; a second resistor connected between the second terminal and a ground; And a third resistor having a resistance value changed in accordance with an output signal of the trimming signal generating means, wherein the first terminal is connected to a second input terminal of the differential amplifier. And outputting a trimmed reference potential from the second terminal. 3. A fourth resistor connected in parallel with said second resistor and having a resistance value changed in accordance with an output signal of said trimming signal generating means. 3. The semiconductor device according to 2. 4. A semiconductor device for generating an internal power supply voltage to be supplied to an internal circuit by stepping down an external power supply voltage supplied from the outside, comprising: a reference potential generating means for generating a reference potential; and the reference potential generating means. A trimming signal generating means for generating a trimming signal for trimming the reference potential generated by the reference potential generator; a differential amplifier having a first input terminal receiving the reference potential generated by the reference potential generating means; A MOS transistor having one end supplied with the external power supply voltage, a gate connected to the output terminal of the differential amplifier, and the other end of the current path connected to a first terminal; A first resistor connected between the terminals of which the resistance value is changed in accordance with the output signal of the trimming signal generating means; A second terminal connected between the second terminal and ground, the resistance value of which is changed in accordance with an output signal of the trimming signal generator;
Wherein the first terminal is connected to a second input terminal of the differential amplifier, outputs a trimmed reference potential from the second terminal, and outputs the first resistor and the first resistor. 2. The semiconductor device according to claim 2, wherein the sum of the resistance values of the resistors is constant irrespective of the output signal of the trimming signal generating means. 5. A semiconductor device for generating an internal power supply voltage to be supplied to an internal circuit by lowering an external power supply voltage supplied from the outside, comprising: a reference potential generating means for generating a reference potential; and the reference potential generating means. A trimming signal generating means for generating a trimming signal for trimming the reference potential generated by the reference potential generator; a differential amplifier having a first input terminal receiving the reference potential generated by the reference potential generating means; A MOS transistor having one end supplied with the external power supply voltage, a gate connected to the output terminal of the differential amplifier, and the other end of the current path connected to a first terminal; A first resistor connected between the terminals of which the resistance value is changed in accordance with the output signal of the trimming signal generating means; A second terminal connected between the second terminal and ground, the resistance value of which is changed in accordance with an output signal of the trimming signal generator;
The second terminal is connected to a second input terminal of the differential amplifier, outputs a trimmed reference potential from the first terminal, and outputs the first resistor and the first resistor. 2. The semiconductor device according to claim 2, wherein the sum of the resistance values of the resistors is constant irrespective of the output signal of the trimming signal generating means. 6. The apparatus according to claim 1, further comprising a level shifter connected to an output terminal of said trimming signal generating means for shifting a trimming signal output from said trimming signal generating means to an external power supply voltage. The semiconductor device according to any one of the above.