JP2000049165A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To thermally stabilize the emitter resistance of a bipolar semiconductor device without increasing the resistance uselessly by positioning the quantization energy level formed in a quantum well in a thermal equilibrium state between the forbidden band end of a semiconductor on the outside of the quantum well and Fermi energy. SOLUTION: Since cap layers 6 and 8 on both sides of a quantum well structure 7 are doped at high concentration, Fermi energy becomes higher than the energy at the forbidden band end of a semiconductor and electrons degenerate and form so-called electron seas 106 and 107. A quantum well layer 103 is composed of InGaAs and the energy at the forbidden band end of the layer 103 is lower than that at the forbidden band end of GaAs constituting the contacting parts of the cap layers 6 and 8 with the quantum well structure 7. In the structure 7, however, the energy at a quantization level 104 becomes an intermediate value between the energy at the forbidden band end of the GaAs constituting the contacting parts of the cap layers 6 and 8 with the structure 7 and Fermi energy due to the effect of confinement.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a bipolar semiconductor device suitable for high-speed and high-output signal amplification.

[0002]

2. Description of the Related Art A conventional bipolar semiconductor device is described in, for example, Gallium Arsenide Icy Symposium, Technical Digest, pp. 91-94 (1996).
posiumTechnical Digest 1996 pp91-94), and its thermal stabilization was described in 1995 Gallium Arsenide Icy Symposium Technical Digest pp.147-150.
Page (GaAs IC Symposium Technical Digest 1995 pp147
-150)

[0003]

In a bipolar transistor, thermal instability easily occurs due to its characteristics. The reason is as follows.

The current of a bipolar transistor is generally proportional to the exponential function of the voltage applied between the base and the emitter divided by the absolute temperature. Therefore, when the base of a bipolar transistor is driven using a voltage source, first, (1) the temperature rises due to heat generation accompanying power consumption. Accordingly, the index increases (2), and the element current increases. As a result, (3) the power consumption increases and the temperature further increases. By repeating (1) to (3), the temperature rises until the heat radiation balances the heat generation. Insufficient heat radiation will lead to destruction of the device. This is thermal instability, and its suppression is indispensable especially for high-power transistors that consume large power.

In the above conventional example, in order to eliminate this thermal instability, a resistor called a ballast resistor is inserted in series with the base or the emitter terminal. The effect of this ballast resistor on thermal instability is as follows.

When the current increases due to heat generated by power consumption, the voltage drop at the ballast resistor increases. as a result,
The voltage between the base and the emitter decreases, and the increase in current is suppressed. Therefore, an increase in power consumption and an increase in temperature can be avoided.

However, since the ballast resistor acts as a parasitic resistance of the element, there is a problem that performance degradation such as reduction of high-frequency gain is caused. Further, when the ballast resistor is formed using a resistor such as a metal outside the transistor region, there is a problem that the accuracy of the resistance value is high but the area is increased. Further, when a low-doped semiconductor region is provided in the emitter region and a ballast resistor is formed by using a semiconductor resistor as in the second conventional example, the emitter region becomes thicker, which makes it difficult to form an element, and also increases the resistance value. However, there is a problem that it is difficult to increase the precision of the method.

[0008]

In order to solve the above-mentioned problems, in the present invention, a current-saturated nonlinear element having a quantum well structure in an emitter region is formed.

That is, the semiconductor device according to the present invention is: (1) In a bipolar semiconductor device comprising an emitter region, a base region, and a collector region, a potential barrier layer having dimensions equal to or less than the Debye length of electrons in the emitter region is provided. It has a quantum well region composed of a potential well layer, and in a thermal equilibrium state, a quantization energy level formed in the quantum well is located between a band gap edge of a semiconductor outside the quantum well and Fermi energy. It is characterized by the following.

(2) In the above (1), the quantum well region is located outside the depletion layer of the emitter-base junction. (3) In the above (1),
The differential resistance between the emitter and the base is positive or zero in all current regions. (4) In the above (2), the energy of the carrier at the forbidden band edge of the material forming the potential well layer is lower than the energy of the carrier in the semiconductor outside the quantum well region. (5) A plurality of semiconductor devices described in (1) to (4) are connected in parallel on the same substrate.

In the quantum well structure, when the quantization energy level formed therein is located between the forbidden band edge of the semiconductor outside the quantum well structure and the Fermi energy (resonance state), the quantum well structure is larger due to the resonance tunnel effect. Current flows, that is, low resistance. When an electric field is applied to deviate from the above resonance conditions, the resonance tunnel current does not flow, so that the current decreases and the resistance increases, and further, a negative resistance may occur. Actually, since there is a current component flowing non-resonantly, such as a current component flowing over the potential barrier, by adjusting the thickness of the barrier layer, a current saturation type current-voltage characteristic easily occurs.

In the present invention, by designing the quantum well structure such that the quantum well structure is in a resonance state at the time of normal operation current, the parasitic resistance can be increased very little at the time of normal operation. The voltage drop in the quantum well structure having a saturated current-voltage characteristic increases, and the increase in current can be suppressed. Further, it is not necessary to form a resistor outside the transistor region, and it is possible to avoid an increase in area.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a schematic sectional view of a bipolar semiconductor device according to the present invention. In FIG. 1, 1 is an n-type GaAs substrate, 2 is an n-type GaAs subcollector (n = 2 × 10 ¹⁸ / cm ³ , 0.5 μm in thickness), and 3 is an n-type GaAs collector (n = 2 × 10 ¹⁶ / C
m ³ , thickness 0.3 μm), 4 is p-type GaAs
Base (0.1 micrometer thick, p = 4 × 10 ¹⁹
/ Cm ³ ), 5 is an n-type InGaP emitter (n = 5 × 10
¹⁷ / cm ³ , thickness 0.05 μm, In composition ratio 0.5), and 6 is an n-type GaAs cap (n = 5 × 10 ^18).
/ Cm ³ , thickness 0.05 μm), 7 is an undoped quantum well structure, 8 is n-type composition graded InGaAs.
s cap (n = 0.5 to 2 × 10 ¹⁹ / cm ³ , thickness: 0.0
5 micrometers, In composition ratio 0-0.5), 9 is A
u / Mo laminated emitter electrode (thickness Au: 0.2 micrometer / Mo: 0.05 micrometer), 10: base extraction electrode (AuZn: Zn 0.1 mol%), 1
1 is a collector extraction electrode (AuGe: Ge 6 mol%)
It is.

As shown in FIG. 3, the quantum well structure 7 has AlGaAs potential barrier layers 101 and 102 (thickness 10 nm, Al
It has a three-layer structure of a composition ratio of 0.2) and a strained InGaAs quantum well layer 103 (5 nm thick, In composition ratio of 0.2).

The preparation process is as follows. First, n
The semiconductor layers 3 to 8 in FIG. 1 are crystal-grown on the type GaAs substrate 1. This growth can be achieved by the usual MBE method or MOMB
E method and Si or Sn as n-type dopant
And Be or C may be used as the p-type dopant. If Zn is used as a p-type dopant, MOCVD
It is possible to perform the deposition by a method. After the growth, the substrate is taken out of the growth apparatus, and the layers 5 to 8 on the surface side are removed from the emitters in the regions other than the emitter region by using ordinary photolithography and chemical etching. Subsequently, the layers 2 to 4 on the front surface side are similarly etched and removed from the collector in the region other than the base region by using ordinary photolithography and chemical etching. Thereafter, the emitter electrode 9 and the base electrode 10 are formed by ordinary photolithography and a lift-off method, and further, a collector electrode 11 is formed on the back surface of the substrate to form a transistor.

Thereafter, an insulating layer is further provided on the electrode to form a contact hole with the wiring, and then a wiring metal is applied and processed to complete the transistor.

The operation of the transistor thus formed will be described below. FIG. 2 is an energy band diagram of the transistor of the present invention, which is the same as a normal heterojunction bipolar transistor except for the quantum well structure 7.

The operation of the quantum well structure 7 is as follows. First, in the quantum well structure shown in FIG. 3, the motion of electrons in the quantum well layer 103 is quantized in a direction perpendicular to the layers due to the electron confinement effect by the barrier layers 101 and 102. The quantization level indicated by. Now, the layers 6 and 8 on both sides of the quantum well structure 7
Is doped at a high concentration of n = 5 × 10 ¹⁸ / cm ³ , the Fermi energy becomes higher than the forbidden band edge, and the electrons are degenerated to form so-called electron seas 106 and 107. The quantum well layer 103 is InGaAs
As shown in FIG. 3, the energy at the forbidden band edge is lower than the energy at the forbidden band edge of GaAs constituting the portions of the cap layers 6 and 8 in contact with the quantum well structure. However, due to the confinement effect described above, in this structure, the energy of the quantization level 104 is intermediate between the energy of the GaAs forbidden band edge and the Fermi energy constituting the portion of the cap layers 6 and 8 that are in contact with the quantum well structure. Value.

When a current is applied to this structure, electrons flow from 107 to 104 as shown in FIG. 4 while the current is small. This is the resonance tunnel current. When the current is gradually increased, an electric field is generated inside the quantum well structure 7, and finally, the energy of the quantization level 104 becomes lower than the energy of the forbidden band edge of the cap layer 8 as shown in FIG. The tunnel current stops flowing. Therefore, the flowing current is the sum of the current flowing through the quantization level 105 shown in FIG. 5, the current flowing through the quantum well structure 7 in a non-resonant tunnel, and the current generated by electrons having high energy exceeding the barrier. .

In the case of this embodiment, the barrier layers 101 and 1
Since a material having a relatively low energy barrier, such as AlGaAs having an Al composition ratio of 0.2, was used for 02, a relatively large amount of current other than the above-described resonance tunnel current was obtained. Therefore, the current-voltage characteristic of only the quantum well structure portion is not the negative differential resistance characteristic often observed when the resonance tunnel current stops flowing, but the current saturates with a rise in voltage as shown in FIG. Characteristics. In the structure of this embodiment, the current density at which the current saturation occurs is about 40 kA / cm ² , and the voltage applied to the quantum well structure at that time is about 20 mV. Further, current saturation occurs up to a voltage applied to the quantum well structure of about 100 mV.

The operation of the semiconductor device having such a quantum well structure will be described below. Since the semiconductor device of this embodiment is basically a bipolar transistor, its current is generally proportional to the exponential function of the voltage applied between the base and the emitter divided by the absolute temperature. Therefore, as described in the section of the subject of the present invention, when the base is driven by using the voltage source, there is a possibility that thermal instability may occur. However, in the present embodiment, the introduction of the quantum well structure has eliminated this thermal instability as described below.

As shown in FIG. 6, when the current increases due to the heat generated by the power consumption, the voltage drop increases at the current density at which the current saturation occurs in the quantum well structure. As a result, the base
The voltage at the emitter junction is reduced and the increase in current is suppressed.
Therefore, an increase in power consumption and an increase in temperature can be avoided.

Comparing this effect with the thermal stabilization by the ballast resistor described in the section of the subject of the present invention, (1) 40 k
Compared with a ballast resistor that generates a voltage rise of about 100 mV at about A / cm ² , the series resistance is as small as about ５, and performance deterioration such as a decrease in high-frequency gain is minimized. In fact, the transistor of the present example showed a cutoff frequency of 40 GHz at a current of 10 mA in a device having an emitter size of 3 μm × 10 μm.

On the other hand, in a transistor having the same emitter dimensions and a ballast resistor, an 8 ohm ballast resistor is formed to generate a voltage drop of 100 mV at a current of 12 mA (current density of 40 kA / cm ² ). The cutoff frequency was 32 GHz at a current of 10 mA due to the deterioration of the high frequency characteristics.

(2) There is no need to form a ballast resistor using a resistor such as a metal outside the transistor region.
There is no increase in area. Actually, when the above-mentioned ballast resistor of 8 ohms is formed using a resistor having a resistivity of 100 ohms / square, the area is 10 micrometers × 25 micrometers, which is almost the same as the transistor area.

Further, in this embodiment, a quantum well structure having a thickness of 25 nanometers is provided in comparison with the case where (3) a lightly doped semiconductor region is provided in the emitter region and a ballast resistor is formed using a semiconductor resistor. Used, usually between 0.1 and
The total thickness of the emitter and the cap layer is smaller than when only a thickness of 0.2 μm is required for the low concentration semiconductor layer used for the ballast resistor. The thickness of the upper layers 5 to 8 from the emitter of this embodiment is 0.175 micrometers in total. Even if this value is summed with the thickness of the emitter electrode metal, since it is smaller than the thickness of the ordinary wiring metal layer of about 0.5 to 1 micrometer, there is no difficulty in forming the element.

In this embodiment, a transistor using an n-type GaAs substrate has been described. However, when a semi-insulating GaAs substrate is used, a step of exposing the subcollector layer from the substrate surface side is provided, and an electrode is taken out therefrom. Of course, the same effect can be obtained by performing.

Further, the material, thickness and doping concentration of each layer constituting the transistor are not limited to those described in the present embodiment, but the materials, thickness and doping concentration used for ordinary heterojunction bipolar transistors. Should be fine. For example, In _0.53 Ga on an InP substrate
_0.47 As / InP combination, GaAs on GaAs substrate
In the combination of / AlGaAs and the like, a similar quantum well structure, that is, a quantum well in which the quantization energy level formed in the quantum well is located between the forbidden band edge of the semiconductor outside the quantum well and the Fermi energy. The same effect can be obtained by using a well structure. At this time, the current value at which current saturation occurs depends on the energy difference between the quantization energy level formed in the quantum well and the forbidden band edge of the semiconductor outside the quantum well, so that the energy difference is adjusted. This makes it possible to adjust the saturation current value.

<Embodiment 2> In Embodiment 1, n-type GaAs was used.
Using a semi-insulating GaAs substrate instead of the s substrate, a step of exposing the subcollector layer from the substrate surface side was provided, and electrodes were taken out therefrom. Further, the unit transistor has an emitter size of 3 μm × 10 μm and the unit transistor 120 formed on the same substrate.
The pieces were connected in parallel using metal wiring.

In the operation of the transistors connected in parallel in this way, since the terminal voltage of each transistor is common, even if the power supply for driving each terminal is not a voltage source but has an internal resistance, it is not thermally ineffective. Stability may occur. This means that if any one of the transistors becomes thermally unstable, even if the base-emitter voltage of that transistor decreases,
The emitter current can increase, with the current concentrated in one transistor and the current in the other transistor decreasing. Therefore, in such a parallel-connected transistor, a measure against thermal instability is indispensable.

In this embodiment, since the quantum well structure effectively suppresses thermal instability, the device operates without any problem up to a total device current of 1.2 A, particularly in the same structure as in the case of single operation. On the other hand, when a ballast resistor is provided for each element in a similar parallel-connected transistor, a ballast resistance similar to the differential resistance at zero bias of the quantum well structure of the present embodiment, that is, a ballast resistance of about 2 ohms for each element is not thermally effective. Due to the instability, it was impossible to flow a total of 1.2 A of the element current, and a ballast resistor of about 6 to 8 ohms was required for each element.

In this embodiment, the power supply voltage is 1.9 GHz at a power supply voltage of 3 V because of the high frequency performance caused by the low series resistance.
Achieved a maximum output of 2.4 W and a linear gain of 15 dB. On the other hand, in a parallel element provided with a ballast resistor, under the same conditions, the maximum output is 2.0 W and the linear gain is 12.7 dB.
Met.

[0033]

According to the present invention, thermal stability can be achieved without increasing the emitter resistance of the bipolar semiconductor device. Further, it is not necessary to form a resistor outside the transistor region, and it is possible to avoid an increase in area.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an energy band structure diagram of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is an energy band structure diagram of a quantum well structure portion of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is an energy band structure diagram of a quantum well structure during operation of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is an energy band structure diagram of a quantum well structure during a current limiting operation of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a voltage-current density characteristic diagram of a quantum well structure portion of a semiconductor device according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... n-type GaAs substrate, 2 ... n-type GaAs subcollector, 3 ... n-type GaAs collector, 4 ... p-type GaAs base, 5 ... n-type InGaP emitter, 6 ... n-type GaAs cap, 7 ... undoped quantum well structure, 8 ... n-type composition graded InGaAs cap, 9 ... Au / Mo laminated emitter electrode, 10 ... base extraction electrode, 11 ... collector extraction electrode, 101, 102 ... AlGaAs potential barrier layer,
103: strained InGaAs quantum well layer.

Claims (5)

[Claims] 1. A bipolar semiconductor device comprising an emitter region, a base region, and a collector region, wherein a quantum well region comprising a potential barrier layer and a potential well layer having dimensions equal to or smaller than the Debye length of electrons is provided in the emitter region. A semiconductor device having a thermal energy equilibrium and wherein a quantization energy level formed in the quantum well is located between a band gap edge of a semiconductor outside the quantum well and Fermi energy. 2. The semiconductor device according to claim 1, wherein the quantum well region is located outside a depletion layer of the emitter-base junction. 3. The semiconductor device according to claim 1, wherein the differential resistance between the emitter and the base is positive or zero in all current regions. 4. The semiconductor device according to claim 2, wherein the energy of the carrier at the forbidden band edge of the material forming the potential well layer is lower than the energy of the carrier in the semiconductor outside the quantum well region. 5. A semiconductor device wherein a plurality of the semiconductor devices according to claim 1 are connected in parallel on the same substrate.