JP2000049119A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize low resistance and high density in a wiring by forming a metal on the inner surface of a via hole formed in an insulation layer on an LSI semiconductor substrate, by means of a barrier layer formed of an inorganic compound layer or a high melting-point metallic layer. SOLUTION: An insulation film 2 is deposited on an LSI semiconductor substrate 1, and a via hole 3 reaching the LSI silicon substrate 1 is formed in the insulation film 2. Then, a titanium nitride 4 as an inorganic compound layer or a high melting-point metallic layer is deposited entirely over the via hole 3 to the surface so as to form a barrier layer. Next, after the surface treatment is applied thereto, the surface is subject to electroless copper plating in an electroless copper plating liquid 5 without washing by water. Thus, a copper thin film 9 is formed as a seed layer on the surface of the titanium nitride 4 as well as in the via hole 3 and on the surface thereof. Then, after washing by pure water, the entire body is treated by a dilute sulfuric acid solution, and a copper body 10 is embedded in the via hole 3 by electroplating. Further, it is ground and a via stud 12 is made independent.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a novel plating method, and more particularly to a plating method used for forming wiring on a substrate in a semiconductor device such as an LSI.

[0002]

2. Description of the Related Art Conventionally, a metal film serving as a wiring in a semiconductor device has been deposited by a sputtering method of aluminum, a CVD method of tungsten, or the like. However, it is expected that further miniaturization of wiring will be further advanced in the future along with the high integration of LSI.
In the case of wiring materials such as aluminum and tungsten, problems such as a delay in signal transmission speed due to a high resistance value and a decrease in reliability due to low migration resistance become problems. On the other hand, copper is expected to be an alternative wiring material because it can realize low resistance and high electromigration resistance, but there are many problems to be solved.

In general, when copper is used as a wiring material, it is difficult to use the same dry etching method as that for aluminum as a wiring forming technique. Therefore, a method of forming an insulating layer in advance, processing the insulating layer at a portion corresponding to the wiring or the interlayer connection conductor into a concave shape, and filling the concave portion with copper is used.

As a filling method, there is a method of selectively filling only the concave portions. However, a general method is to metallize the entire surface of the substrate including the concave portions and then perform chemical mechanical polishing (CMP polishing). The metallization method for filling the recesses includes a dry metallization method such as a sputtering method and a chemical vapor deposition method (CVD method), and a wet metallization method such as electroless plating and electroplating.

[0005] The wet metallization method is more advantageous in embedding into fine recesses for high-density wiring.
In recent years, a process combining the wet metallization method and the CMP polishing has attracted attention. Japanese Patent Application Laid-Open No. 8-83796 describes a method of filling wiring grooves by electroless plating of silver, copper, gold, nickel, cobalt, and palladium.

If the purpose is to make the resistance lower than that of aluminum wiring, the metals that can be used in these are:
These are considered to be about silver, copper, and gold, but all of them form a seed layer of palladium by collimator sputtering, and form various electroless platings thereon. In such a method, a step of forming a palladium seed layer by collimator sputtering becomes a bottleneck, and it is not possible to sufficiently achieve fine wiring. Also, palladium easily reacts with these electroless plating metals and easily enters the wiring metal,
This leads to an increase in the resistance, with contradictory consequences for the introduction of low resistance metals in place of aluminum.

Japanese Patent Application Laid-Open No. 6-29246 discloses a method in which a substance serving as a catalyst for an electroless plating reaction is applied to grooves and holes by wet processing, and the holes are filled with metal by electroless plating. . In this case, palladium is used as a catalyst, but in the case of lowering the resistance from aluminum, electroless copper plating is the most effective, but palladium and copper easily react and bring about an increase in resistance, The original purpose of lowering the resistance cannot be achieved.

Further, a zinc oxide layer is formed by spray pyrolysis on a silicon oxide film (insulating film) having fine concave portions formed thereon, and the zinc oxide layer is dissolved and plated with palladium or the like, and the palladium is used as a seed layer. There is known a method of forming copper, gold, or the like by electroplating or electroless plating. However, in this method, palladium is used as described above, so that the resistance of the wiring metal increases,
It is a problem. In addition, there is a possibility that the element characteristics may be deteriorated due to the mixing of zinc.

In JP-A-7-283219, JP-A-7-122556 and JP-A-8-83796, titanium, titanium nitride, and tantalum are sequentially formed on a surface of an insulating layer in which a concave portion is formed by sputtering. A method of forming a wiring by performing electroplating of copper and the like are disclosed. In this case, unlike the above-described method, it is considered that the resistance of the copper wiring is not increased by a different element such as palladium. However, since the electric resistance of the multilayer thin film of titanium, titanium nitride, and tantalum is large, electroplating using these as a cathode is considered. In this case, there is a disadvantage that the embedding property of the concave portion is poor.

[0010] In electroplating, it is necessary for uniform deposition that an electric field is applied uniformly. However, in the case of a cathode having a high resistance as described above, an electric field is hardly applied to the vicinity of the bottom of the concave portion. It is expected that the fillability will decrease as the depth increases (the aspect ratio increases).
This is a fatal defect in forming fine wiring.

[0011]

As described above, various methods have been studied for embedding fine concave portions by a wet metallizing method which is advantageous in embedding properties, but each has its own problems. Since the purpose is to make the resistance lower than that of aluminum wiring, alternative metal materials are limited to copper, silver and gold.

However, these metals may react with the insulating layer or Si, so that it is necessary to protect all surfaces with a barrier layer which is a conductor. Materials that exhibit their function as barrier layers of these metals include titanium nitride,
Metal nitrides such as tungsten nitride and tantalum nitride; refractory metals such as tantalum and tungsten; and alloys thereof. However, these nitride metals and refractory metals and their alloys,
Since they are inert to the electroless plating reaction, it has not been possible to apply electroless plating directly on these nitride metals, high melting point metals and their alloys.

Further, since these nitride metals, high melting point metals and their alloys have high electric resistance, it has been difficult to directly electroplate these nitride metals, high melting point metals and their alloys.

Therefore, in order to enable the filling of the minute recesses by plating, it is necessary to form a seed layer serving as a catalyst by electroless plating of copper, palladium or the like. The seed layer formed by the dry metallization method has a poor uniform deposition property on the bottoms and side walls of fine grooves, which hinders miniaturization.

Therefore, the method for forming the seed layer is as follows.
There has been a long-felt need for an invention of a forming method which is excellent in uniform precipitation and can replace dry metallization. Although there is an example in which a displacement plating method of palladium is examined for forming a seed layer, as described above, palladium causes an increase in wiring resistance, and there is a problem in forming finer wiring.

There is also an example in which a displacement plating method of copper has been studied, but there is a problem that adhesion is poor. Furthermore, in these displacement plating methods, a barrier layer is eluted with the deposition of a plating metal, so that there is a fatal problem that sufficient reliability cannot be secured. It is an object of the present invention to provide a semiconductor device in which a metal is directly filled in a minute concave portion of a via hole or a groove on a semiconductor substrate without forming a seed layer having a high resistance by a dry metallization method, and a module and a large-scale computer using the same. Is to do.

It is another object of the present invention to provide a semiconductor substrate having excellent uniform deposition properties with respect to a fine concave portion of a via hole or a groove.
It is another object of the present invention to provide a method of manufacturing a semiconductor device in which a via hole or a trench is filled with metal without elution of a barrier layer accompanying the progress of a plating reaction.

[0018]

SUMMARY OF THE INVENTION According to the present invention, a surface of a conductor, which is a barrier layer made of an inorganic compound or a high melting point metal, which covers the surface of a dielectric layer on an LSI semiconductor substrate is treated with a processing solution containing a complexing agent. After the treatment, the conductor is electrically connected to a substance in which the electroless plating reaction is in progress or a substance in which the electroless plating reaction is in progress, and electroless plating is performed on the conductor surface to form a plated metal. The via hole or groove formed in the insulating layer is entirely filled with copper plating.

The present invention preferably comprises an insulating layer having holes or / and grooves for forming via studs and / or wiring on an LSI semiconductor substrate, wherein the holes or / and grooves are formed on the inner surfaces of the holes or / and grooves. A semiconductor device is characterized by being formed of the same metal via a formed inorganic compound layer or a barrier layer formed of a high melting point metal layer.

Further, the present invention is preferably a semiconductor device in which insulating layers having via studs and insulating layers having wiring are alternately formed on an LSI semiconductor substrate. And
The via stud according to the present invention is characterized in that the whole is formed of the same metal by electroplating followed by electroplating or electroless plating.

According to the present invention, there is provided a surface-mounted type wherein the semiconductor device described above is sealed with a composition containing epoxy resin, spherical quartz powder and a silicone polymer or containing no silicone polymer. It is a non-surface mounting type resin-sealed semiconductor device. The spherical quartz powder accounts for 70% by weight or more, more preferably 80 to 95% by weight of the whole composition. In particular, according to the present invention, as a logic or memory semiconductor device, 82 to 90% by weight of quartz powder is used for a thin type having a thickness of 1.5 mm or less.
And 90% or more of the quartz powder is made of fused spherical quartz powder, and 3 to 10% of non-spherical (square) quartz powder is used.

Further, the present invention provides a logic or memory semiconductor device which is a surface-mount type QFP and a non-surface-mount type DILP for a logic having a thickness of 1.5 mm or more, and a SOJ and TSOP for a memory. Filler, preferably quartz powder is 75 ~
It is sealed with an epoxy resin composition having 81% and silicone. Particle size 5μm ~
Fused spherical quartz powder is used for 60 to 80% of the 100 μm powder, and it is preferable to use square quartz powder (crushed quartz powder) having a particle size of less than 5 μm, preferably 3 μm or less. The spherical quartz powder is preferably 65 to 75%.

According to the present invention, there is provided a module having a multilayer thin film wiring board in which a plurality of insulating layers each having a wiring layer on the surface are stacked, and a semiconductor device mounted on the wiring board, wherein the semiconductor device is the same as the semiconductor device described above. The module is characterized in that:

According to the present invention, a module substrate connected via connection pins is mounted on a printed wiring board, and a multilayer thin film wiring board in which a plurality of insulating layers having wiring layers are stacked on the module substrate is mounted. A large computer characterized in that the semiconductor device described above is mounted on the wiring board.

According to the present invention, there is provided an insulating layer having a via stud on a semiconductor substrate, wherein the via stud is formed via a barrier layer made of an inorganic compound or a high melting point metal formed on an outer surface thereof, and has a diameter of A semiconductor device having a thickness of 0.3 μm or less.

According to the present invention, there is provided an insulating layer formed of a dielectric having a groove or a via hole formed on a semiconductor substrate, and an inorganic compound or a high melting point metal covering the surface of the insulating layer including the side and bottom surfaces of the groove or the via hole. A plating method for forming a plating metal on the conductor surface of a semiconductor substrate having a conductor that is a barrier layer made of an electroless plating solution, wherein the conductor surface is coated with a complex in the electroless plating solution. After being treated with a processing solution containing a forming agent, the conductor is electrically connected to a substance in which the electroless plating reaction is progressing or a substance in which the electroless plating reaction is proceeding. The groove or the via hole is filled with a metal by electroless plating, and a metal is further deposited thereon.

Further, according to the present invention, after the electroless plating is performed on the surface of the conductor, a metal is buried in the via hole or the groove by electroplating as described above, and a metal is deposited thereon.

The electroless plating is preferably copper plating, and its thickness is preferably 1 to 100 nm.

The electroplating is preferably an electrocopper plating.

The inorganic compound or the high melting point metal is made of an electric conductor. In particular, the latter has a melting point of 1490 ° C. or more of titanium, tantalum, tungsten, cobalt, or a nitride thereof, or an alloy of titanium, tantalum, tungsten, and cobalt. Among them, a conductor containing any one of them is preferable.

The complexing agent is preferably ethylenediaminetetraacetic acid, the electroless plating is an electroless copper plating, and the treatment liquid before the electroless copper plating is performed is at least the ethylenediaminetetraacetic acid 0.001 to 0.001. 1 mol /
1, an aqueous solution containing 0 to 1 mol / l of hydrogen peroxide is preferred.

The substance electrically connected to the conductor is
It consists of a metal on which a plating metal is deposited by electroless plating, and copper, platinum and palladium are preferable.

That is, in the present invention, the conductive layer is a substance on which a plated metal is not formed by the electroless plating as described above. The plating metal can be formed by immersing a metal member formed of a plating metal by electroless plating in a plating solution and electrically connecting the metal member and the conductive layer.

As described above, there are various combinations of a barrier layer and electroless plating to which the present invention can be applied. Here, titanium nitride is used as the barrier layer, and electroless plating is used as the plating for forming the seed layer. The case where copper plating is used will be described.

After forming an insulating layer as a dielectric layer on a silicon substrate, forming a groove in the insulating layer, a barrier layer of titanium nitride as a conductor is formed. The barrier layer is formed by a sputtering method or a CVD method. The CVD method is more advantageous in consideration of uniform precipitation in the groove,
Unlike the seed layer, the barrier layer does not need to be uniform on the surface and in the groove, and it is sufficient that the barrier layer has at least a sufficient thickness to exhibit barrier properties. Therefore, the sputtering method is also sufficiently applicable.

Thereafter, a seed layer is formed on the surface of the barrier layer. The seed layer desirably has a uniform thickness on the surface and in the groove. This is because, when a uniform seed layer is not formed on the surface and in the groove, the resistance of the seed layer is different between the surface and the groove during electroplating to fill the groove, and the resistance in the thin groove of the seed layer is This is because the resistance becomes higher than the resistance of the thick surface of the seed layer, an electric field is hardly applied to the groove, and filling by plating becomes impossible.

It is impossible to form the surface and the inside of the groove with a uniform seed layer by the conventional sputtering method. In the current method to which the present invention is not applied, the difference between the resistance in the surface and the groove is apparently reduced by increasing the thickness of the sputtered film.However, if the sputtered film is too thick, the opening of the groove or hole is closed,
It becomes a void.

The present invention is an epoch-making method for forming a seed layer by electroless copper plating capable of forming a uniform film even in a complicated form. The electroless copper plating reaction can be represented by the following reaction formula (Formula 1).

Cu ²⁺ (L) + 2HCHO + 4OH ⁻ → Cu + 2HCOO ⁻ + 2H ₂ O + H ₂ + L (Formula 1) where L is a complexing agent that forms a complex with copper, and when ethylenediaminetetraacetic acid (EDTA) is used There are many.

This reaction proceeds selectively on metals such as copper and palladium, because these metals show catalytic activity for the oxidation reaction of formaldehyde. When formaldehyde is oxidized, it emits electrons, and the electrons are received by copper ions, reduced to metallic copper and deposited.

However, the titanium nitride in the barrier layer is inactive to the electroless copper plating reaction, and the plating reaction proceeds even when the silicon substrate having titanium nitride formed on the surface is immersed in the electroless copper plating solution. No copper is deposited.

However, we have found that the surface of titanium nitride is ED
By treating with a surface treatment solution containing TA, and then electrically connecting to the copper plate and immersing it in the electroless copper plating solution together with the copper plate, it is possible to perform electroless copper plating directly on the titanium nitride surface. I found it.

At this time, after the surface treatment with the EDTA aqueous solution,
It is desirable to immerse directly in the electroless copper plating solution without going through the washing step. The electrically connected copper plate desirably has a larger surface area than the wafer which is the substrate to be plated, and more preferably 1.5 times or more.

As described above, the surface of the barrier layer serving as a base for electroless plating is treated with a surface treatment solution containing a complex-forming agent which forms a complex with the plating metal with an electroless plating solution in the next step. By electrically connecting the barrier layer of the substrate to be plated and the substance undergoing the plating reaction and immersing it in the electroless plating solution, a seed layer can be formed directly on the barrier layer surface by electroless plating. Will be possible. The seed layer formed by electroless plating has a film thickness distribution of about ± 5% or less even in the surface portion and in the groove.
Very good for the uniformity of the film thickness.

In forming the seed layer for forming the wiring on the semiconductor substrate, in addition to the above-described electroless copper plating, electroless nickel plating, electroless gold plating, and electroless cobalt plating can be applied.

As the insulating layer according to the present invention, for example, heat C
SiO ₂ , BPSG, PSG, formed by VD method, etc.
BSG, AsSG, NSG, SOG, LTO, SiN, Si
ON, Si-containing compound film such as SiOF, amorphous Te
flon (poly-tetra-fluoro-ethylene), BCB (benzo-cy
clo-butent), Parylene, Flare (fluorinated-arylene-e
ther) or other organic low-dielectric-constant material films, or a laminated film thereof.

Hereinafter, an example of a method for forming an insulating layer will be specifically described.

(1) “Thermal CVD-SiO ₂ film formation conditions” Gas: SiH ₄ / O ₂ / N ₂ = 250/250/100 s
ccm Pressure: 13.3 Pa Substrate heating temperature 420 ° C. (2) “Plasma CVD SiN film formation conditions” Gas: SiH ₄ / N ₂ O = 50/10 sccm Pressure: 330 Pa RF: Power 190 W Substrate heating temperature 400 ° C (3) “Plasma CVD TEOS-SiO ₂ film formation conditions” ・ Gas: TEOS = 50 sccm ・ Pressure: 333 Pa ・ RF: Power 190 W ・ Substrate heating temperature 400 ° C. (4) “ECR plasma CVD SiON film formation conditions” ・ Gas : SiH ₄ / N ₂ O = 50/25 sccm ・ Pressure: 330 Pa ・ RF: Power 800 W ・ Substrate heating temperature 360 ° C. (5) “Magnetron sputtering SiO ₂ film forming conditions” ・ Gas: Ar = 100 sccm ・ Pressure: 0.4 Pa・ RF: Power 5kW ・ Substrate heating temperature 150 ℃ As via hole forming technology that becomes a contact hole,
Using a lithography tool and an etching technique, a contact hole having a hole diameter of 0.3 μm or less, preferably 0.15 to 0.25 μm can be formed in the insulating layer under the following conditions.

Gas: C ₄ F ₈ / CO / Ar = 10/10
0/200 sccm ・ Pressure: 6 Pa ・ RF: Power 1600 W ・ Substrate temperature 20 ° C. The copper chemical mechanical polishing (CMP) conditions are preferably as follows.

"Cu (+ TiN / Ti) CMP conditions" Polishing pressure: 100 g / cm ² Rotation speed: platen 30 rpm Polishing head: 30 rpm Polishing pad: IC-1000 (trade name) Slurry: H ₂ O ₂ Base (containing alumina) ・ Flow rate: 100 cc / min ・ Temperature: 25 to 30 ° C. [Embodiment of the invention] [Embodiment 1] FIG. 1 is a diagram showing a plating method for an LSI silicon substrate according to the present invention. . First, as shown in FIG. 1A, an S by thermal CVD is formed on an LSI silicon substrate 1.
An insulating film 2 made of iO ₂ was deposited to a thickness of 0.9 μm, and a via hole 3 reaching the silicon substrate 1 was formed in the insulating film 2. At this time, the diameter of the via hole 3 was φ0.3 μm. afterwards,
Titanium nitride 4 was deposited as a barrier layer, covering the entire surface from the via hole 3 to the surface. In a usual manner, the plating metal is not directly formed on the titanium nitride surface by electroless plating.

Next, the substrate was immersed in an aqueous solution containing 0.1 mol / l of EDTA and 0.08 mol / l of hydrogen peroxide at 65 ° C. for 2 minutes to perform a surface treatment.

Thereafter, as shown in FIG. 1B, the substrate was not washed with water but was immersed in an electroless copper plating solution 5 shown below. At this time, the titanium nitride 4 on the surface of the silicon substrate and the copper plate 7 were connected with the copper wire 8. A plating metal is formed on the surface of the copper plate 7 by electroless plating. At this time, the surface area of the titanium nitride 4 on the surface of the silicon substrate was about 30 cm ² , and the surface area of the connected copper plate 7 was about 50 cm ² on both sides. FIG. 1 (c) shows the surface of titanium nitride 4 by electroless copper plating for about 2 minutes.
As shown in FIG. 7, a copper thin film 9 having a thickness of about 70 nm was formed uniformly on both the inside and the surface of the via hole 3 as a seed layer.

[Electroless copper plating solution] Copper sulfate: 0.04 mol / l Disodium ethylenediaminetetraacetate: 0.1 mol / l
l formaldehyde ... 0.03 mol / l sodium hydroxide ... 0.1 mol / l 2,2'-bipyridyl ... 0.0002 mol / l polyethylene glycol (average molecular weight 600) ...
0.03 mol / l pH = 12.8 Solution temperature 70 ° C. Next, the substrate on which the copper thin film 9 was formed
It was taken out from the inside and washed with pure water. Then, it was treated with a 10% dilute sulfuric acid aqueous solution for 2 minutes, immersed in an electroplating solution, and electroplated. FIG. 1D is a cross-sectional view in which a copper conductor 10 is buried in the via hole 3 by electroplating and a copper thin film is formed on the insulating film 2 using the following liquid.

[Electrolytic copper plating solution] Copper sulfate: 0.3 mol / l Sulfuric acid: 1.9 mol / l Solution temperature: 25 ° C. Next, in order to separate the conductor 10, a chemical machine (CMP)
Polishing was performed. FIG. 1E is a cross-sectional view after the via stud 12 is made independent by CMP polishing. As described above, by using the plating method of this embodiment, it is possible to form a seed layer without using a dry method such as a sputtering method, and to easily fill copper microholes by electroplating. Thus, the effect of the present invention was confirmed.

[Embodiment 2] FIG. 2 is a view showing an example applied to plating for filling holes for interlayer connection and grooves for wiring formation.

[0056] First, as shown in FIG. 2 (a), depositing an insulating film 2 of SiO ₂ on the LSI silicon substrate 1, a via hole 3 extending in the insulating film 2 on the LSI silicon substrate 1,
A groove 11 for forming a wiring was formed.

Thereafter, titanium nitride 4 was used as a barrier layer.
Was deposited, and the entire surface was covered from the via hole 3 to the wiring forming groove 11 and the surface.

Next, the substrate was immersed in an aqueous solution containing 0.1 mol / l of EDTA and 0.08 mol / l of hydrogen peroxide at 65 ° C. for 2 minutes to perform a surface treatment.

Thereafter, as shown in FIG. 2B, the substrate was not washed with water but was immersed in the same electroless copper plating solution 5 as in Example 1. At this time, the titanium nitride 4 and the copper plate 7
And were connected by a copper wire 8. At this time, the surface area of the titanium nitride 4 on the surface of the silicon substrate was about 30 cm ² , and the surface area of the connected copper plate 7 was about 50 cm ² on both sides.

As shown in FIG. 2C, a copper thin film having a thickness of about 70 nm in both the inside of the via hole 3 and the surface of the wiring forming groove 11 was formed on the surface of the titanium nitride 4 by electroless copper plating for about 2 minutes. 9 was uniformly formed.

Next, the substrate on which the copper thin film 9 was formed was taken out of the electroless copper plating solution 5 and washed with pure water. Then, it was treated with a 10% dilute sulfuric acid aqueous solution for 2 minutes, immersed in an electroplating solution, and electroplated. FIG. 2D is a cross-sectional view after the conductor 10 is buried in the via hole 3 by electroplating using the same liquid as in the first embodiment.

Next, as shown in FIG. 2E, a sectional view after forming the via studs 12 by CMP polishing.

As described above, by using the plating method of this embodiment, it is possible to form a seed layer without using a dry method such as a sputtering method. Can be easily filled,
The effect of the present invention was confirmed. Example 3 The same procedure as in Example 1 was carried out except that each of the barrier layers was replaced by titanium nitride 4, tantalum nitride, tungsten, and tungsten nitride. As a result, a substrate having a cross-sectional structure similar to that of Example 1 is obtained. By using the plating method of this example, a seed layer can be formed without using a dry method such as a sputtering method. It was found that the fine holes of copper could be easily filled by plating, and the effect of the present invention was confirmed.

[Embodiment 4] FIG. 3 schematically shows this embodiment. As shown in FIG. 3A, similar to the first embodiment, the LSI
An insulating film 2 of SiO ₂ was formed on a silicon substrate 1, and a via hole 3 was formed in the insulating film 2. Thereafter, titanium nitride 4 was deposited as a barrier layer, and the entire surface was covered from the via hole 3 to the surface.

Then, the substrate was immersed in an aqueous solution containing 0.08 mol / l of hydrogen peroxide and an aqueous solution not containing 0.08 mol / l of EDTA at 65 ° C. for 2 minutes with the former and 30 minutes with the latter for 30 minutes. , Surface treatment.

Thereafter, as shown in FIG. 3B, the substrate was not washed with water but was immersed in the same electroless copper plating solution 5 as in Example 1. At this time, the titanium nitride 4 and the copper plate 7
And were connected by a copper wire 8. At this time, the surface area of the titanium nitride 4 on the surface of the silicon substrate was about 30 cm ² , and the surface area of the connected copper plate 7 was about 50 cm ² on both sides. Electroless copper plating having a thickness of about 1 μm was performed by plating for about 30 minutes.

As a result, as shown in FIG. 3C, all the via holes 3 were completely filled with the copper conductor 10.

Next, as shown in FIG.
Polishing was performed to form via studs 12.

As described above, by using the plating method of this embodiment for any of the treatments, it is possible to fill the copper fine holes by electroless plating without using a dry method such as a sputtering method. It was found that the process was easily performed, and the effect of the present invention was confirmed.

Comparative Example 1 For comparison, an example in which the present invention is not performed will be described.

A via hole was formed in the same manner as in Example 1, and a barrier layer of titanium nitride was formed. Thereafter, the substrate was immersed in the electroless plating solution. At this time, ED before plating
The surface treatment of the substrate with the TA-based treatment liquid was not performed. As a result, no electroless copper plating reaction occurred on the titanium nitride surface, and an electroless copper plating film could not be formed. Therefore,
Even in the copper copper plating in the next step, almost no copper was deposited inside the via hole, and the via hole could not be filled with metal.

Further, in the same manner as in Example 1, up to the plating pretreatment with an EDTA-based aqueous solution, the substrate was immersed in an electroless plating solution. At this time, the silicon substrate was immersed alone in the electroless copper plating solution without connecting the titanium nitride and the copper plate with a conductive wire. As a result, no electroless copper plating reaction occurred on the titanium nitride surface, and an electroless copper plating film could not be formed. Therefore, even in the copper electroplating in the next step, almost no copper was deposited inside the via hole, and the via hole could not be filled with metal.

As described above, it was found that the object of the present invention could not be achieved in any case where the present invention was not carried out. This proved the effectiveness of the present invention.

[Embodiment 5] FIG. 4 shows a multilayer wiring layer formed on an LSI silicon substrate 1 by forming via studs 12 of Embodiments 1 to 4 and manufacturing the wiring layer 13 and the insulating film 2 alternately and repeatedly. FIG. 4 is a cross-sectional view of a semiconductor device according to the present invention.
As shown in the figure, a W bear 34 is formed in an insulating layer 2 on an LSI silicon substrate 1, and an insulating layer 2 and a wiring layer 13 are formed thereon.
Are formed, and via studs 12 and wiring layers 13 are formed alternately. On the uppermost wiring layer 13, a titanium nitride 4 formed by sputtering and an Al-Si alloy layer 36 formed thereon are formed.
A protective film 37 made of a polyimide resin is formed on the surface of the uppermost SiO ₂ insulating film 2. The W bear 34 is formed by CVD. In this embodiment, five wiring layers 13 are used.

[Embodiment 6] FIG. 5 is a perspective view of a surface-mount type resin-sealed semiconductor device in which a semiconductor device 20 in which multilayer wiring is formed on the LSI silicon substrate obtained in Embodiment 5 is resin-sealed with epoxy resin. FIG. The epoxy resin 19 uses a resin having a filler described below.
15 is an Au wire, 16 is its die bonding, 17 is an outer lead, and 18 is a support bar. Copper or a 42 alloy is used for the lead frame.

The various fillers and epoxy resin compositions shown in Table 1 were kneaded with a biaxial roll heated to 80 ° C. for 10 minutes.

The composition using the obtained spherical filler has a very low melt viscosity and a large fluidity even though the gelation time is almost the same as that of the composition using the square filler.
Further, a composition containing a filler having a smaller gradient n represented by an RRS particle size diagram has a lower melt viscosity and a higher fluidity. When the n value is 0.6 or less, the melt viscosity (18
0 ° C.) is undesirably increased.

[0078]

[Table 1]

Further, a spherical filler (sphere-1) is used as the filler.
Was used to prepare 70, 75, 80 and 85% by weight of a resin composition, respectively.

Transfer molding was performed using these resin compositions, post-curing was performed at 180 ° C. for 6 hours, and the linear expansion coefficient, flexural modulus and thermal stress at room temperature were measured.

Further, the semiconductor element having the aluminum zigzag wiring formed on the surface is subjected to transfer press sealing, and is then subjected to −55 ° C./30 minutes⇔ + 150 minutes / 30/2000.
A cycle thermal cycle test was performed to evaluate the crack resistance of the sealing resin layer and the connection reliability of the lead / gold wire bonding / aluminum wiring (if the resistance value changed by 50% or more was judged to be defective). Table 2 shows the results.

According to Table 2, the composition containing the silicone polymer and containing 80% by weight or more of the filler had a linear expansion coefficient of 1.3 × 1.
It is as small as 0 ^-5 / ° C or less, and the increase in elastic modulus is small. Therefore, it can be seen that the thermal stress generated in the insert is also small.

The resin-encapsulated semiconductor device using the resin composition as in this embodiment is extremely excellent in crack resistance and wiring connection reliability due to a thermal shock applied in a thermal cycle test.

In this example, spherical silica powder having a particle size of 100 μm or less was used as 95% of the filler with respect to the resin composition containing no siloxane, and the remainder was made of square quartz powder having a particle size of 10 μm or less. It was 85% by weight. Further, spherical quartz powder having a particle size of 100 μm or less was used as 70% of the filler in the resin composition containing siloxane, and the remainder was made up of square quartz powder having a particle size of 5 μm or less, and the total was 80.5% by weight. Each of the resin-sealed semiconductor devices had the same characteristics as those of the above-described embodiment.

[0085]

[Table 2]

The RRS particle size diagram is a particle size diagram showing a particle size distribution according to the Rosin-Rammler equation (distributed by the Japan Powder Industry Association: Powder Engineering Handbook, pp. 51-53). R (Dp) = 100exp (-b · Dp n) ... (1) [where, R (Dp): cumulative weight percent of the maximum particle size to the particle size Dp, Dp: particle size, b and n: constants] RRS The gradient in the particle size diagram is the value of the Rosin-Rammler formula n represented by a straight line connecting two points, 25% and 75%, from the maximum particle size of the RRS particle size diagram. I say

The particle size distribution when the filler ore is pulverized finely matches the Rosin-Rammler equation, and the RRS particle size diagram showing the particle size distribution based on this equation shows an almost straight line.

The present inventors measured the particle size distribution of various fillers. As a result, 90% by weight or more of all fillers showed an RRS particle size diagram and showed almost linearity unless special sieving was performed. It has been confirmed that the above formula is well matched.

The spherical fused quartz powder used in the present invention is a high-temperature fused quartz powder, which has been previously ground to a predetermined particle size distribution, is generated from a thermal spraying apparatus using a combustible gas such as propane, butane, acetylene, or hydrogen as a fuel. Spherical ones that are fed into a flame in a fixed amount and melted and then cooled are most preferred. The above-mentioned fused quartz has a relatively small coefficient of linear expansion by itself and an extremely small amount of ionic impurities, and thus is suitable as a resin composition material for semiconductor element sealing.

90% by weight or more of the filler has a particle size of 0.5 to 1
It is preferably in the range of 00 μm. When the number of fine particles having a particle size of less than 0.5 μm increases, the thixotropic properties of the resin composition increase, and the particle size increases and the fluidity decreases. Also,
If the number of particles exceeding 100 μm increases, the Au wire of the semiconductor element may be deformed or cut during sealing, or coarse particles may cause clogging in the mold, and resin filling failure may easily occur. is there.

Next, the gradient n shown in the RRS particle size diagram is set to 0.
Most preferably, it is 6 to 0.95. When n is larger than 0.95, the filler becomes bulky, the viscosity of the resin composition increases, and the fluidity decreases. Therefore, it is desirable that n is as small as possible. In the present invention, it is desirable that 90% or more of the filler is in the particle size range of 0.5 to 100 μm, and the n value of 0.6 is defined within this condition. This is the smallest possible value.

The silicone polymer used in the present invention is a polydimethylsiloxane having a functional group such as an amino group, a carboxyl group, an epoxy group, a hydroxyl group, or a pyrimidine group at a terminal or a side chain.

Epoxy resins which are solid at room temperature are cresol novolak type epoxy resins, phenol novolak type epoxy resins, bisphenol A as semiconductor encapsulating materials.
Type epoxy resin, etc., and using novolak resins such as phenol novolak and cresol novolak, acid anhydrides such as pyromellitic anhydride and benzophenone anhydride as curing agents, and further, curing accelerators, flexibilizing agents, coupling agents, A coloring agent, a flame retardant, a release agent, and the like can be added as needed.

This epoxy resin composition was prepared by adding 70% to each material.
The mixture can be kneaded with a biaxial roll or an extruder heated to １００100 ° C. and molded by a transfer press at a mold temperature of 160 to 190 ° C., a molding pressure of 30 to 100 kg / cm ² , and a curing time of 1 to 3 minutes.

As described above, the coefficient of linear expansion of the cured product is 1.3 ×
The elastic modulus can be reduced by reducing the value to 10 ⁻⁵ / ° C. or less. Therefore, the deformation and disconnection of the Au bonding wire of the semiconductor element at the time of sealing are small, and the thermal stress based on the difference in linear expansion coefficient is small, so that the temperature cycle resistance, heat resistance, moisture resistance and the like are good.

By melting and spheroidizing quartz powder as a filler, the bulk is reduced and the filler is easily filled. Further, at the time of sealing the semiconductor element, it is possible to prevent the corners of the filler from damaging the element and adversely affecting the element characteristics.
Furthermore, the elastic modulus can be reduced by blending the silicone polymer, and the thermal stress caused by the difference in linear expansion coefficient can be further reduced.

[Embodiment 7] FIG. 6 is a flow chart based on a schematic cross-sectional view of a substrate in each step showing an example of a manufacturing process of a copper / polyimide thin-film multilayer wiring board according to the present invention.

Step (a): Cr / Cu / Cr serving as a first metal wiring layer is formed on a glass ceramic substrate 21 having a thickness of 6 mm.
(Cr: 500 ° thick, Cu: 5 μm thick) was formed by sputtering in Ar. 25 is a through hole for connection.

Step (b): A resist pattern (positive resist) was formed on the Cr / Cu / Cr conductor film, and a first metal wiring layer 29 was formed by wet etching.

Step (c): A 20 μm-thick semi-cured polyimide-based adhesive sheet as the insulating film 22 was pressure-bonded as the insulating film 22 on the first metal wiring layer 29 at 250 ° C. and 15 kg / cm ² , and cured. .

Step (d): Next, an Al film 32 having a thickness of 2000 .ANG. Was formed as a dry etching mask by a vacuum evaporation method.

Step (e): A dry etching mask 28 for forming a via hole is formed by a photoetching method, and then a parallel plate type dry etching apparatus (not shown) using an oxygen gas plasma having a gas pressure of 3 Pa and an RF output of 500 W As a result, a via hole 27 was formed.

Step (f): Next, a barrier layer 4 of titanium nitride was formed on the entire surface of the substrate. At this time, the entire surface of the polyimide and the inner wall surfaces of the via holes were covered with titanium nitride.
After that, as a pretreatment, after treatment in an aqueous solution containing EDTA in the same manner as in Example 1, electroless copper plating was performed in the same manner as shown in FIG. As a result, the via holes were all filled with copper.

Step (g): Next, as in Example 1, CM
P polishing was performed to form a via stud 23.

Note that a C having a diameter of 30 μmφ × a height of 25 μm was used.
The electroless chemical copper plating time required for forming the u-via stud was about 5 hours.

Step (h): Cr / Cu / Cr is formed on the insulating layer 22 in the same manner as in the steps (a) and (b).
(Cr: 500 ° thick, Cu: 5 μm thick), and a second metal wiring layer 30 was formed by a sputtering method.

By repeating the above, a thin film multilayer wiring board having three or more layers can be manufactured.

[Embodiment 8] FIG. 7 is a schematic sectional view of a mounting board in which an LSI 20 having a multilayer wiring formed on the surface thereof in Embodiment 5 is mounted on a thin-film multilayer wiring board 44 obtained in this embodiment. A thin-film wiring layer made of polyimide / copper was formed on a ceramic substrate 35, and an LSI 20 having multilayer wiring formed by solder bumps 26 was mounted and connected to a thin-film multilayer wiring board 44 connected to via studs 23. The wiring layer 24, the via stud 23, and the insulating layer 22 are manufactured in the same manner as in the seventh embodiment.

[Embodiment 9] FIG. 8 is a schematic cross-sectional view showing an example in which a thin-film multilayer wiring board on which the above-described LSI is mounted is used as a board for a large computer, and a pin insertion type module is mounted on a large printed wiring board 41. This is an example in which a substrate 42 is mounted.

The module substrate 42 is made of a multilayer sintered body of glass ceramics and a copper layer, and has connection pins 43 on the lower surface.
Is provided. The thin film multilayer wiring board 44 according to the present invention is formed on the module board 42, and the LSI 20 is connected and mounted by the solder bumps 26.

According to the mounting board of this embodiment, the total number of wirings can be reduced to about 1/4, and the wiring density can be increased. Also, the signal transmission speed can be increased about 1.5 times as compared with the conventional one.

The thin-film multilayer wiring board according to the present embodiment can achieve high-speed signal transmission by increasing the mounting density and shortening the wiring length. In addition, by employing a sheet-like insulating layer (for example, the above-mentioned polyimide-based composite sheet), the manufacturing process can be significantly reduced.

[Embodiment 10] FIG. 9 is a sectional view of a semiconductor device in which solder balls 38 are formed on a multilayer wiring layer of the semiconductor device having the multilayer wiring layer formed in FIG. The solder ball 38 is Au.

FIG. 10 is a cross-sectional view of flip-chip mounting in which the semiconductor device of FIG. 9 is joined to a large-sized printed wiring board 41 by the solder balls 38 described above. As shown in the figure, after being joined by the solder balls 38, it is filled with an underfill material made of epoxy resin. Also in this embodiment, as shown in FIG. 9, the via studs 12 having a diameter of 0.3 μm and the wiring layers 13 described in the first to fourth embodiments are alternately formed.

[Embodiment 11] FIG. 11 is a sectional view of a ball grid array type semiconductor device. Also in this embodiment, the semiconductor device 20 having the multilayer wiring layer obtained in the fifth embodiment was used. It is made of ceramics and the like. The above-described semiconductor device 20 is bonded to the base 47 with an adhesive 45 such as a resin,
The inner leads 46 are bonded by the Au wires 15. The electrode 48 is formed by sequentially forming a titanium nitride and an Al—Si alloy layer on a Cu wiring by sputtering, pole-bonding the semiconductor element, and wedge-bonding the inner lead 46. The electrode 40 is obtained by forming Sn plating on a Cu wiring.

[0116]

According to the present invention, minute recesses on a substrate can be directly filled by electroless plating without forming a seed layer by a conventional dry metallization method such as a sputtering method, thereby enabling high-density wiring.

In addition, by electroless plating, a seed layer which is excellent in uniform deposition property on minute concave portions on the substrate and which does not involve elution of the barrier layer as the plating reaction proceeds, is formed.
Next, by filling the minute recesses on the substrate on which the seed layer has been formed by electroplating, fine wiring with stable quality can be formed.

As a result, it is possible to form high-density wiring with stable quality on a substrate, and to obtain a highly reliable semiconductor device, module and large computer.

The thin-film multilayer wiring board according to the present invention is excellent as a board for a large-sized computer, a board for a work station, and a board for small electronic devices such as a video camera.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a method for plating a substrate according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view of a method for plating a substrate according to an embodiment of the present invention.

FIG. 3 is a schematic sectional view of a method for plating a substrate according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor device having a multilayer wiring layer according to the present invention.

FIG. 5 is a perspective view of a surface-mounted resin-sealed semiconductor device according to the present invention.

FIG. 6 is a manufacturing process diagram of the thin-film multilayer wiring board of Example 1.

FIG. 7 is a schematic sectional view of a mounting structure using the thin-film multilayer wiring board of the present invention.

FIG. 8 is a schematic sectional view showing a mounting example of a large-sized computer board according to the present invention.

FIG. 9 is a sectional view of a semiconductor device on which a multilayer wiring layer according to the present invention is formed.

FIG. 10 is a sectional view of flip-chip mounting according to the present invention.

FIG. 11 is a sectional view of a ball grid array type semiconductor device according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... LSI silicon substrate, 2 ... Insulating film, 3, 27 ... Via hole, 4 ... Titanium nitride, 5 ... Electroless copper plating solution, 6 ...
Plating bath, 7 copper plate, 8 copper wire, 9 copper thin film, 10 conductor, 11 groove, 12, 23 via stud, 13 wiring layer, 15 Au wire, 16 die bonding, 17 outer Lead, 18 support bar, 19 epoxy resin, 20 semiconductor device, 21 substrate, 22 insulating layer, 2
4 metal wiring layer, 25 connection through hole, 26 solder bump, 28 etching mask, 29 first metal wiring layer, 30 second metal wiring layer, 31 resist
32 ... Al film, 33 ... Land, 34 ... W bare, 35 ... Ceramic substrate, 36 ... Al-Si alloy film, 37 ... Protective film, 38 ... Solder ball, 39 ... Underfill material, 4
0 ... electrode, 41 ... large printed wiring board, 42 ... module board, 43 ... connection pin, 44 ... thin film multilayer wiring board
45: adhesive, 46: inner lead, 47: base.

Claims (13)

[Claims] 1. An insulating layer having a hole or / and a groove on a semiconductor substrate, wherein the hole or / and the groove comprises an inorganic compound layer or a high melting point metal layer formed on the inner surface of the hole or / and the groove. A semiconductor device, wherein the whole is formed of the same metal via a barrier layer. 2. In a semiconductor device in which insulating layers having via studs and insulating layers having wirings are alternately formed on a semiconductor substrate, the via studs and the wirings are inorganic compounds formed on inner surfaces of via holes and trenches. A semiconductor device, wherein the whole is formed of the same metal via a layer or a barrier layer made of a high melting point metal layer. 3. An insulating layer having a via stud and / or wiring on a semiconductor substrate, wherein said via stud and / or wiring is an inorganic compound layer or a high melting point metal layer formed on an inner surface of a via hole or / and trench. A semiconductor device formed entirely by electroplating after electroless plating of the same metal via a barrier layer made of the same metal. 4. An insulating layer having a via stud and / or a wiring on a semiconductor substrate, wherein the via stud and / or the wiring is an inorganic compound layer or a high melting point metal layer formed on an inner surface of a via hole or / and a trench. A semiconductor device characterized by being entirely formed by electroless plating via a barrier layer composed of: 5. A semiconductor device in which insulating layers having via studs and insulating layers having wirings are alternately formed on a semiconductor substrate, wherein the via studs and the wirings are inorganic compounds formed on inner surfaces of via holes and trenches. A semiconductor device characterized by being formed by electroplating after electroless plating of the same metal via a barrier layer made of a layer or a refractory metal layer. 6. A semiconductor device in which insulating layers having via studs and insulating layers having wirings are alternately formed on a semiconductor substrate, wherein the via studs and the wirings are inorganic compounds formed on inner surfaces of via holes and trenches. A semiconductor device characterized by being formed directly by electroless plating via a layer or a barrier layer made of a high melting point metal layer. 7. An insulating layer having a via stud on a semiconductor substrate, wherein said via stud is formed via a barrier layer made of an inorganic compound or a high melting point metal formed on an outer surface thereof, and has a diameter of 0.1 mm. A semiconductor device having a thickness of 3 μm or less. 8. A resin-sealed semiconductor device, wherein the semiconductor device according to claim 1 is sealed with a composition containing epoxy resin, spherical quartz powder, and a silicone polymer. 9. The resin-encapsulated semiconductor device according to claim 7, wherein the spherical quartz powder accounts for 80% by weight or more of the whole composition. 10. A module having a multilayer thin-film wiring board on which a plurality of insulating layers each having a wiring layer on its surface are stacked, and a semiconductor device mounted on the wiring board, wherein the semiconductor device is any one of claims 1 to 8. A module comprising the semiconductor device according to any one of the preceding claims. 11. A multi-layer thin-film wiring board in which a module board connected via connection pins is mounted on a printed wiring board, and a plurality of insulating layers having a wiring layer are stacked on the module board, and A large-scale computer comprising the semiconductor device according to claim 1 mounted on a substrate. 12. A method of manufacturing a semiconductor device in which a conductive material is filled in said via hole or / and trench of an insulating layer having a via hole or / and trench on a semiconductor substrate by plating. After forming a barrier layer composed of a conductive inorganic compound or a high melting point metal, the substrate is treated with a treatment solution containing a complexing agent, and then the substrate is immersed in an electroless plating solution and the same as the metal formed by the electroless plating. A method of manufacturing a semiconductor device, comprising: bringing a member made of metal into contact with the electroless plating solution, electrically connecting to the barrier layer, and filling the substrate by electroless plating. 13. A method of manufacturing a semiconductor device, wherein a conductive material is filled in the via hole of an insulating layer having a via hole on a semiconductor substrate by plating, wherein a barrier layer made of a conductive inorganic compound or a high melting point metal is provided on the inner surface of the via hole. After forming, the substrate is treated with a treatment solution containing a complexing agent, and then the substrate is immersed in an electroless plating solution and a member made of the same metal as the metal formed by the electroless plating is brought into contact with the electroless plating solution. Forming a plating layer by electroless plating after being electrically connected to the barrier layer, and then filling the layer by electroplating.