JP2000046910A - Function test method for integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a function test method in which the function of an IC in an actual operation can be verified even when a test pattern for an actual frequency is not created, by a method wherein an expected output pattern before the portion of the detected number of cycles is collated with an output pattern from an output terminal, and the abnormality of the function is discriminated. SOLUTION: In the same manner as in conventional cases, an input test pattern for a low frequency is used. Whether an IC is operated normally or not and whether the test pattern is not problematic or not are tested preliminarily. At this time, when their test result is good, the input test pattern for the low frequency is inputted to the IC, and the propagation delay time elapsed until the input test pattern is outputted actually from an output terminal is measured. After that, the function of the IC in an actual operation is verified. That is to say, the number of cycles of the input test pattern for the low frequency is detected at an actual frequency which is contained in the propagation delay time at a time when the input test pattern for the low frequency is used. Then, an expected output pattern before the portion of the number of cycles is read out. Then, the expected output pattern in compared and collated with the output test pattern. When both patterns agree, it is judged that the function of the IC is not abnormal. When both patterns disagree, it is judged that the function of the IC is abnormal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function test method for confirming, using a test pattern, whether or not an integrated circuit normally operates when a specified operating condition is given to the integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a function test of an integrated circuit is performed, for example, according to a procedure shown in FIG. First, a test pattern in which data periodically changes (hereinafter, referred to as an “input test pattern”) and a pattern of an output value that is expected to be output when the integrated circuit operates normally (hereinafter, “expected A "test pattern" is created in combination with the "output pattern" (S401).

At the time of a functional test, an input test pattern is applied to an input terminal of an integrated circuit. At this time, in order to confirm whether there is no mistake in the design of the integrated circuit or whether there is a mistake in the frequency setting of the test pattern. First, a preliminary test is performed using a low-frequency test pattern. More specifically, a pattern actually output from an output terminal when an input test pattern for low frequency is applied to an input terminal of an integrated circuit (hereinafter, referred to as an “output test pattern”) is used as an expected output at that time. Compare with the pattern (S402).

If the two patterns do not match, it means that the integrated circuit is defective or there is a problem with the low-frequency test pattern (S403: NO). Is recreated, and if there is a problem with the low-frequency test pattern, the low-frequency test pattern is corrected, and the functional test is performed again.

If the two patterns match, it means that the integrated circuit is good and there is no problem with the low-frequency test pattern (S403: YES). Therefore, in order to confirm whether or not the integrated circuit operates normally at the time of the actual frequency (at the time of inputting the high-frequency signal), a test pattern for the actual frequency is prepared (S404), and the test pattern for the actual frequency is used. Perform a functional test. Specifically, when the input test pattern for the actual frequency is applied to the input terminal of the integrated circuit, the output test pattern actually output from the output terminal is compared with the expected output pattern at that time (S405).

If the two patterns do not match, it means that there is a malfunction in the integrated circuit or a problem in the test pattern for the actual frequency (S406: NO). Is recreated, and if there is a problem with the test pattern for the actual frequency, the test pattern is corrected and the functional test is performed again. If both patterns match,
Since the integrated circuit at the actual frequency operates normally and there is no problem with the test pattern (S406: YE
S) The function test ends.

The contents of the above function test will be described more specifically with reference to FIGS. FIG. 5 is a schematic diagram of an integrated circuit to be tested. The input test pattern applied to the input terminal (IN # 1) of the integrated circuit 51 is delayed when passing through the circuit blocks # 1 and # 2 having delay elements and reaches the output terminal (OUT # 1). The delay time at this time is called “propagation delay time”. Other input terminal IN #
Similarly, a propagation delay time occurs until the output terminals (# 2 and # 3) reach output terminals (not shown). Such an integrated circuit 5
1, the input test pattern is sufficiently slow, that is, the propagation delay time TP is longer than the cycle T of the input test pattern.
FIG. 6 shows a timing chart when D1 is sufficiently small. In FIG. 6, "Data *" actually consists of a combination of logic 0 and logic 1, but here, for convenience, it is represented by a symbol to clarify the positional relationship.
The “expected output pattern matching point” represents data of a matching position (matching point) of an expected output pattern defined for each input test pattern. As shown in the figure, when the input test pattern is sufficiently slow, if the integrated circuit 51 is operating properly, each reference point (Data0, Data1, D1) of the expected output pattern is obtained.
data1, data2) and an output test pattern (Dat
a0, Data1, Data1, and Data2).

However, when the cycle of the input test pattern approaches the cycle of the actual frequency (when the cycle becomes faster), the cycle of the input test pattern becomes shorter than the propagation delay time TPD1. FIG. 7 shows a sequence chart in this case. In the case of FIG. 7, since the expected output pattern matching point is synchronized with the cycle T2 of the input test pattern, the output test pattern at the output terminal (OUT # 1) does not match the expected output pattern matching point. That is, if the output test pattern is “Da
ta0 "," Data1 "," Data1 "," Data
a2, while the matching point of the expected output pattern is
"Data0", "Data0", "Data1",
"Data1", and they do not match.

Therefore, conventionally, when testing the function of an integrated circuit at a real frequency, a test pattern for a high frequency in consideration of a frequency and a propagation delay time is prepared separately from a test pattern for a low frequency, and FIG. As shown, it was necessary to collate the output test pattern with the expected output pattern collation point for each pattern.

[0010]

As described above, conventionally, when a functional test of an integrated circuit is performed, a test pattern for an actual frequency is separately prepared in addition to a test pattern for a low frequency used in a test at a preliminary stage. And there is a problem that the test process cannot be reduced. If the expected output pattern matching point does not match when a function test of the integrated circuit is performed at the actual frequency, it is determined whether the check point is due to a defect in the test pattern or an abnormality in the function of the integrated circuit. There was also a problem that it was difficult. This is because the test pattern is for a real frequency and cannot be verified under a low frequency.

SUMMARY OF THE INVENTION An object of the present invention is to provide an improved function test method which can reduce the number of test steps and can easily identify the cause of an abnormal condition.

[0012]

A function test method according to the present invention for solving the above-mentioned problems comprises a test pattern in which data changes periodically and an integrated circuit to be tested when a test pattern in each cycle is input. A set of an expected output pattern expected to be output is prepared, and a test pattern of a predetermined frequency included in a propagation delay time until the input test pattern is actually output from the integrated circuit is prepared. It is characterized in that the presence or absence of a function abnormality of the integrated circuit is determined by detecting the number of cycles and comparing the expected output pattern before the detected number of cycles with the pattern output from the output terminal.

According to another function test method of the present invention, a test pattern in which data periodically changes at a frequency at which a propagation delay time in an integrated circuit to be tested does not matter, and a test pattern in each cycle are described. Preparing a set of expected output patterns expected to be output from the output terminal when input to the input terminal, and performing a preliminary test of the integrated circuit using the test pattern, When the preliminary test result is good, the number of periods of the test pattern at the frequency of the actual operation included in the propagation delay time until the test pattern is output from the integrated circuit is detected, and the detected number of periods The presence / absence of a function abnormality of the integrated circuit is determined by comparing the expected output pattern a minute ago with the output pattern.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an LSI (Large Scale Integrated Circuit)
An embodiment in which a function test of the LSI is performed using an LSI tester for testing the function of the LSI or a logic circuit simulator for simulating the operation of the LSI will be described.

An LSI tester or the like measures a pattern creating section for creating or correcting a test pattern (a set of an input test pattern and an expected output pattern) according to the size and type of a circuit, and measures a propagation delay time of the input test pattern. A time measuring unit, a period detecting unit that detects how many periods of the input test pattern at the actual frequency corresponds, and a pattern matching unit that compares the output test pattern with the expected output pattern. Have The input test pattern is a pattern in which a combination of binary data of predetermined bits is periodically repeated. The repetition period is determined by whether the propagation delay in the integrated circuit to be tested does not matter and whether the test pattern is abnormal. Verification is easy, and corresponds to a low-frequency input test pattern in relation to the conventional method. For the expected output pattern corresponding to the input test pattern for low frequency,
It is recorded in advance in an external or internal storage device such as an LSI tester and can be read out at any time. Note that the cycle detection unit may use another arithmetic unit separated from the LSI tester or the like.

FIG. 1 is a diagram showing a schematic procedure when a function test of an integrated circuit is performed using such an LSI tester or the like, and corresponds to FIG. 4 showing a procedure of a conventional method. In the present embodiment, an integrated circuit to be tested is prepared in advance, and a low-frequency test pattern (input test pattern and expected output pattern) is created (S101). Then, the conventional method (S402 to S40)
As in the case of (3: NO), first, a preliminary test is performed to determine whether the integrated circuit operates normally and whether there is any problem with the test pattern using the input test pattern for low frequency.
At this stage, if the integrated circuit is defective, the integrated circuit is re-created. If there is a problem with the test pattern, the test pattern is corrected (S102, S103: NO).

If the test results are good (S10
3: After the input test pattern for the low frequency is input to the integrated circuit, the propagation delay time until the output test pattern is actually output from the output terminal is measured (S104). If there are multiple output terminals, the propagation delay time to each output terminal is measured. Thereafter, the function verification of the integrated circuit at the time of actual operation is performed (S105). FIG. 2 shows the procedure of the function verification in more detail.

That is, it is determined how many cycles of the test pattern at the actual frequency are included in the propagation delay time when the input test pattern for the low frequency is used (S201). Is read out (S202). Then, the expected output pattern and the output test pattern are compared and collated (S203).

FIG. 3 is a diagram showing the correspondence between the input test pattern, the expected output pattern, and the output test pattern at this time. The example of FIG. 3 is an example of a case where an input test pattern for two periods is included under the actual frequency within the propagation delay time. In this case, the output test pattern is compared with the expected output pattern two cycles before.

If the two patterns match, it is determined that the function of the integrated circuit is normal (S204: YES, S20).
5) If not, it is determined that the function of the integrated circuit is abnormal (S204: NO, S206).

As described above, according to the present embodiment, the function verification of the integrated circuit at the actual frequency can be performed using the low frequency test pattern. Therefore, it is not necessary to create a test pattern for an actual frequency as in the related art, and the test process can be reduced. Also, the presence or absence of a test pattern defect can be determined by a test at a preliminary stage, and even if a defect occurs at the time of function verification (S204), the defect is a test pattern created for a low frequency. It is easy to determine whether the problem is caused by a defective pattern or a malfunction of the integrated circuit.

[0022]

As described above, according to the present invention,
There is an effect that the function verification of the integrated circuit at the time of actual operation can be performed without creating a test pattern for an actual frequency. Further, since the test pattern for the actual frequency becomes unnecessary, the test process is reduced, and when there is a defect, it is easy to determine whether the cause is the integrated circuit or the test pattern.

[Brief description of the drawings]

FIG. 1 is a procedure explanatory view showing an embodiment of a function test method of the present invention.

FIG. 2 is an explanatory diagram of a procedure in a case where a function of an integrated circuit at a real frequency is tested using a low frequency test pattern.

FIG. 3 is an explanatory diagram showing a relationship among an input test pattern, an expected output pattern, and an output pattern according to the embodiment.

FIG. 4 is an explanatory view of a procedure of a conventional function test method.

FIG. 5 is a schematic diagram of an integrated circuit to be tested.

FIG. 6 is a time chart showing a relationship between an output pattern and an expected output pattern when the propagation delay of an input test pattern does not matter.

FIG. 7 is a time chart showing a relationship between an output pattern and an expected output pattern when a propagation delay of an input test pattern becomes a problem.

FIG. 8 is a diagram showing a correspondence between an output pattern and an expected output pattern.

[Explanation of symbols]

 51 Integrated Circuit Under Test IN # 1 to # 3 Input Terminal of Integrated Circuit OUT # 1 Output Terminal of Integrated Circuit

Claims (4)

[Claims] A set of a test pattern whose data changes periodically and an expected output pattern expected to be output from an integrated circuit to be tested when a test pattern of each cycle is input is prepared. In addition, the number of cycles of the test pattern of a predetermined frequency included in the propagation delay time until the input test pattern is actually output from the integrated circuit is detected, and the expected output pattern before the detected number of cycles is detected. A function test method of the integrated circuit, wherein the presence or absence of a function abnormality of the integrated circuit is determined by comparing the function of the integrated circuit with a pattern output from the output terminal. 2. The function test method according to claim 1, wherein the presence or absence of the function abnormality at different frequencies is determined based on the same test pattern. 3. The function test method according to claim 2, wherein when the expected output pattern changes, the expected output pattern corresponding to a test pattern before the change is held. 4. A predetermined test pattern in which data periodically changes at a frequency at which a propagation delay time in an integrated circuit to be tested does not matter, and when a test pattern in each cycle is input to said input terminal, Preparing a set of expected output patterns expected to be output from the output terminals, and performing a preliminary test of the integrated circuit using the test patterns; At the time of detecting the number of cycles of the test pattern at the frequency of the actual operation included in the propagation delay time until the test pattern is output from the integrated circuit, the expected output pattern and the detected number of cycles before A function test method for an integrated circuit, wherein the presence or absence of a function abnormality of the integrated circuit is determined by comparing the output pattern with the output pattern.