JP2000040819A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable selectively forming a region to be turned into silicide and a region not to be turned into silicide, in an MOS type transistor. SOLUTION: In the formation of a source and a drain (source or the like) 17A, 17B by ion implantation, the formation of the source or the like 17B to be turned into non-silicide is performed firstly. An oxide film is thickly formed on the source or the like 17B in which the rate of oxidation is high by ion implantation, and thinly formed on the source or the like 17A and a gate 14. The oxide film is etched. Etching amount is so set that only a thick oxide film 18a on the source or the like 17B is left. After that, metal 19 is deposited on the whole surface and turned into silicide by thermal treatment. Thereby only the source or the like 17B on which the oxide film 18a is left by the above etching can be made non-silicide in a self-alignment manner.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which MOS transistors are formed on a silicon wafer.

[0002]

2. Description of the Related Art In an LSI, a salicide technique for reducing a wiring resistance by siliciding a gate, a source, and a drain of a MOS transistor in response to a demand for a high-speed circuit element is widely used in a Logic LSI. ing. The salicide technique involves depositing a metal such as Ti to silicide the gate, source and drain surfaces.

[0003]

However, in the LSI, there is a circuit in which it is not always desirable that the resistance value is low. For example, in a protection circuit for preventing electrostatic breakdown,
Since the surface resistances of the source and drain diffusion layers are low, there is a possibility that the electrostatic breakdown withstand capability may not reach the required withstand capability, and such a transistor as a protection circuit or the like must be selectively non-salicide.

Further, when a transistor is manufactured by salicide technology, a slight leak current occurs at a junction between a source and a drain. This leakage current is LogicL
Although this is not a problem in SI, the charge retention characteristic of the capacitor is degraded in the switching transistor of the DRAM memory cell. Therefore, the Logic part and D
When the RAM section and the RAM section are mixedly mounted on one chip, it is necessary to separately make a transistor to be salicide and a transistor to be non-salicide.

[0005] The present invention has been made in view of the above circumstances,
It is an object of the present invention to provide a method of manufacturing a semiconductor device in which a region to be silicided and a region not to be silicided can be separately formed in a wafer.

[0006]

According to the first aspect of the present invention, after a transistor forming step of forming a MOS transistor on a silicon wafer, a metal depositing step of depositing a metal over the entire surface of the silicon wafer; And a silicidation step of silicidation by heat treatment. Further, in the transistor forming step, the oxide film formed in the oxide film forming step is formed by forming an oxide film non-silicide in a thick region and forming a silicided region thin. An oxide film etching step is performed in which the entire region to be removed is removed, and an etching is performed with an etching amount that leaves a region to be non-silicide.

[0007] By the oxide film etching step, the thick oxide film in the region to be non-silicide remains at a certain thickness, and the thin oxide film in the region to be silicided is entirely removed.
In the non-silicide region where the oxide film remains, the deposited metal is unreacted due to the presence of the oxide film and does not silicide, and the deposited metal is silicided in the region where the oxide film is to be completely silicided. In this manner, a region to be silicided and a region not to be silicided can be separately formed in the wafer.

According to the second aspect of the present invention, the non-silicide region is used as a source or a drain of the transistor. The oxide film forming step is performed after forming the gate of the transistor. In the oxide film forming step, a first impurity implanting step of implanting an impurity into a silicon wafer at a position where a source or a drain to be non-silicide is to be formed, and a thermal oxidation step of thermally oxidizing the entire surface of the silicon wafer;
A second impurity implantation step of implanting an impurity into the silicon wafer at a position where a source or a drain to be silicided is formed. A diffusion layer serving as a source and a drain of the transistor is formed by both impurity implantation steps.

On the surface of the silicon wafer into which impurities have been implanted in the first impurity implantation step, the oxidation rate is promoted in the subsequent thermal oxidation step in the source or drain portion which is a non-silicide region. An oxide film thicker than the portion grows and remains after the oxide film etching step. Therefore, the source or drain is not silicided. As described above, it is possible to prevent only the source or the drain from being silicided in a self-aligned manner without strict control of the mask accuracy and the overlay accuracy.

In the third aspect of the present invention, the non-silicide region is used as a source and a drain of the transistor. The oxide film forming step is performed after forming a well that defines the transistor region. In the oxide film forming step, a first thermal oxidation step of forming an oxide film on the entire surface of the silicon wafer by thermal oxidation, a gate forming step of forming a gate in a state where the oxide film is formed on the entire surface, A second thermal oxidation step of forming an oxide film on the entire surface of the silicon wafer by oxidation, and an impurity implantation step of implanting an impurity at a position where a source and a drain of the transistor are formed to form a diffusion layer serving as the source and the drain. Do. A gate oxide film of the transistor is formed by a first thermal oxidation step.

Since the first thermal oxidation step is performed before the gate is formed, an oxide film formed at a position where a source and a drain to be non-silicide are formed is formed on a gate to be formed later. It will not be done. Therefore, the thickness of the oxide film can be made thicker at the position where the source and the drain, which are regions where silicide is not to be formed, and thinner on the gate, without strict control of the mask accuracy and the overlay accuracy. Therefore, only the source and drain portions are not silicided. As described above, it is possible to prevent only the source and the drain from being silicided in a self-aligned manner without strictly controlling the mask accuracy and the overlay accuracy.

In the invention described in claim 4, the non-silicide region is used as a source and a drain of some transistors. In addition to the invention according to claim 3, in the first oxidation step, after forming an oxide film on the entire surface of the silicon wafer, a transistor region having a source and a drain as a silicide in the oxide film is selectively formed. An oxide film reduction step of etching to reduce the thickness of the oxide film in the transistor region is performed.

The thickness of the oxide film is reduced by the oxide film reduction process so that the oxide film is thinner at the position where the source and drain to be silicided are formed and thicker at the position where the source and drain to be non-silicide are formed. Is differentiated. Thus, in the same silicon wafer, a transistor in which the gate is silicided and the source and the drain are non-silicide and a transistor in which the source and the drain are silicided can be separately formed.

In the fifth aspect of the present invention, in the oxide film forming step, an oxide film is formed to have a constant thickness on the gates of all the transistors.

Since the oxide film on the gate has a constant thickness, in the oxide film etching step, all the oxide films on the gates of all the transistors are quickly and simultaneously removed. Excessive overetching of some gates can be prevented.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS.
The cross section of a silicon wafer at each stage in an LSI wafer process in which both a Logic portion and a DRAM portion are mounted in one chip is shown. The method of manufacturing a semiconductor device according to the present invention will be described below. Of the silicon wafer 10,
In the figure, the left side is the transistor region 20A of the Logic portion, and the right side is the transistor region 20B of the DRAM portion. In the following description, the transistor is an nMOS
It will be described as. The method of manufacturing a semiconductor device of the present invention
A transistor forming step of forming an OS-type transistor structure, a deposition step of depositing a metal, and a silicidation step of siliciding a metal are performed, and a general wafer process is basically used. .

In the transistor forming step, first, a shallow trench isolation (STI) 11 for insulating and separating each transistor region is formed in a silicon wafer 10 and a P-type well (Pwell) 12 is formed in common in the transistor regions. . And the silicon wafer 1
A gate oxide film 13 is formed on the entire surface of the zero surface by thermal oxidation. Then, the polycrystalline Si doped with phosphorus (P)
(PolySi) is deposited on the entire surface, and a normal photolithography step and an etching step are performed to form the gate oxide film 1.
3 are formed (FIG. 1)
(A)).

Next, a silicon wafer 10 is formed to form the source and drain electric field relaxation layers of the transistor.
Then, impurity ions are implanted into both ends of the gate 14 to form an impurity diffusion region 15 having a lower concentration than the source and drain. Then, an oxide film 16 is formed on the entire surface by the CVD method (FIG. 1B). At this time, an oxide film 16a rising from the surface of the silicon wafer 10 is also formed on the side surface of the gate 14.

Next, the entire surface is dry-etched to leave only the oxide film 16a, thereby forming a SiO ₂ side wall 16a. Next, a first impurity implantation step is performed. The first impurity implantation step is a source / drain formation step for the transistor region 20B. That is, a photolithography process is used to form a photoresist pattern in which the source and drain design positions (on both sides of the gate 14) of the transistor region 20B where silicide is not to be formed are formed, and impurity ions such as As are implanted using this as a mask. Thus, an impurity diffusion region having a high impurity concentration is formed, and the impurity diffusion region is used as a source and a drain 17B (FIG. 1C).

Next, a thermal oxidation step of again performing thermal oxidation on the entire surface to form an oxide film 18 is performed. FIG. 3 shows the thickness of the oxide film 18 formed by the thermal oxidation, which is obtained when the wet oxidation is performed at 850 ° C. "Si
The “up” is on the source and drain design positions of the transistor region 20A, that is, on the Si exposed portions of the silicon wafer 10 on both ends of the gate 14, “n + S / D” is on the source and drain 17A of the transistor region 20B, and “Pol
“On y Si” indicates on the gate 14. Note that the source and the drain 17B are supplied with As at an accelerating voltage of 40 kV by 5 ×
10 ¹⁵ ions / cm ² were implanted.

It is known that the oxidation rate is promoted on a region having a high impurity concentration and a thick oxide film is formed. However, a source / drain formation step is performed before the oxide film formation step, and a transistor is formed. Since the source and drain 17B of the region 20B have already been formed, the impurity concentration is high. As a result, on the source and drain 17B of the transistor region 20B, the oxide film 18
It grows to a film thickness of as much as nm and becomes an oxide film much thicker than 18 nm on the gate 14 and 4 nm at the source and drain design positions of the transistor region 20A.

Then, a second impurity implantation step is performed again by a combination of the photolithography step and the ion implantation step. In the second impurity implantation step, the transistor region 2
This is a source / drain formation process for 0A. This time, the transistor region 20A in which the source and the drain are not formed in the previous source / drain forming step
A photoresist pattern having openings at both ends of the gate 14 is formed, and impurity ions are implanted into the silicon wafer 10 through the oxide film 18 using the photoresist pattern as a mask to form an impurity diffusion region having a high impurity concentration. The diffusion region is a source and drain 17A (FIG. 1D).

By the first impurity implantation step, the thermal oxidation step, and the second impurity implantation step, source and drain 17A and 17B are formed, and an oxide film on gate 14 and on source and drain 17A of transistor region 20A is formed. A difference can be made between the thickness and the oxide film thickness on the source and drain 17B of the transistor region 20B (oxide film forming step).

Next, an oxide film etching step of dry etching the entire surface is performed. By this etching, first, oxide film 18 on source and drain 17A in thinnest transistor region 20A is removed to expose source and drain 17A, and then oxide film 18 on gate 14 is removed to expose gate 14. . Then, when the oxide film 18 on the source and drain 17B of the transistor region 20B remains, the etching is terminated (FIG. 2E). Here, as is known from FIG. 3, even if the etching amount of the oxide film 18 is set to 36 nm by setting the over-etching time so that the oxide film 18 on the gate 14 is completely removed, the source and the transistor of the transistor region 20B are removed. The oxide film 18 on the drain 17B still remains at 36 nm. Therefore, the oxide film 1 is formed by this etching.
8 can be easily left only on the source and drain 17B of the transistor region 20B (the oxide film 18a).

Next, a metal deposition step is performed. That is, Ti / TiN is deposited on the entire surface by sputtering to form a deposited layer 19 (FIG. 2 (f)).

Next, a silicidation step is performed. That is, heat treatment is applied to the whole by RTA. Thereby, the deposited Ti / Ti N is the Ti Si ₂ only silicided portion in direct contact with Si or Poly Si is formed, T
The portion where i / TiN is in contact with oxide film 18a (that is, on oxide film 18a) is not silicided. Further, a metal selective etching step is performed. That is, Ti / TiN on the oxide film 18a is removed by wet selective etching (FIG. 2 (g)).

Thus, the transistor region 20A of the Logic section includes the gate 14, the source and the drain 17A.
In both cases, silicides 141 and 171 are formed on the surface to complete transistor 21A. In transistor region 20B of the DRAM portion, silicide 141 is formed only on the surface of gate 14 and transistor region 21B is completed. Thereafter, a normal wiring process is performed, and the wafer process ends.

As described above, according to the method of manufacturing a semiconductor device of the present invention, a transistor in which the gate, source and drain are silicided and a transistor in which only the gate is silicided can be separately formed on the same silicon wafer. In addition, since the gate can be silicided even in a non-salicide transistor, both lowering the resistance of the gate and preventing leakage current between the source and drain and the gate can be achieved. A suitable structure can be realized.

Further, an oxide film for a mask for preventing silicidation is formed by masking only an area to be made non-silicide by a photolithography step and an etching step after an oxide film is formed on the entire surface after the transistor is completed. The following effects are obtained as compared with the method in which a metal deposition step is performed in this state while leaving an oxide film for use. That is, in the above method, in order to make the source and the drain non-silicide and silicide the gate adjacent thereto, it is necessary to control the accuracy of the mask for photolithography, the overlay accuracy, the dimensional accuracy of the photoresist pattern, and the like considerably strictly. In practice, it is impossible. On the other hand, in the method of the present invention, the source and the drain are regions in which impurity ions are implanted to increase the impurity concentration, and a mask for preventing silicidation is formed on the region in which the impurity concentration is increased. Thick oxide film is formed in a self-aligned manner, so that the
The source and the drain can be prevented from being silicided.

In this embodiment, the Logic part and the DRAM part are mixedly mounted in one chip by the manufacturing method of the present invention, and only the source and the drain of the transistor in the DRAM part among the gate, source and drain of the transistor are provided. Although the silicidation is not performed, the present manufacturing method can be applied to the case where only the gate is silicided in a single DRAM chip.

Further, according to the manufacturing method of the present invention, only the source and the drain of the protection transistor can be prevented from being silicided. In this case, instead of non-silicidation of both the source and the drain, ion implantation is performed only on the drain portion before the oxide film forming step, so that the gate and the source are silicided, and only the drain is not silicided. Is also good. An ESD protection element is also used as a buffer for inputting and outputting signals. However, while it is desired to obtain as much current capability as possible, when high energy such as ESD is input, the gate oxide film at the drain end may be damaged. To prevent this, the resistance of the drain can be increased (no silicidation), and the resistance of the source side can be reduced (salicide) to ensure current capability. Alternatively, the manufacturing method of the present invention is applied to a CMOS transistor, and the Nch transistor and the P
The source and drain of any of the ch transistors may not be silicided.

(Second Embodiment) FIGS. 4, 5, 6, and 7
Shows a cross section of a silicon wafer at each stage in an LSI wafer process. With this, another manufacturing method of the present invention in which only the source and drain of the right transistor in the drawing are non-silicide will be described. Since the basic process is the same as that of the first embodiment, the same reference numerals are given to substantially the same parts as those of the first embodiment, and the description will be focused on the differences from the first embodiment. First, an STI 1 that insulates and separates each transistor region on a silicon wafer 10
1 and the transistor regions 30A, 30A.
A Pwell 12 is formed in common with B (FIG. 4A). Then, the sacrificial oxide film 100 is removed (FIG. 4B).

Next, a first thermal oxidation step is performed. First,
An oxide film 31 is formed on the entire surface of the silicon wafer 10 by thermal oxidation (FIG. 4C).

After this thermal oxidation, an oxide film reduction step is performed. First, a transistor pattern 30B whose source and drain are non-silicide is covered with a resist pattern 32 by photolithography (FIG. 4D). Next, the resist pattern 3 is formed by wet etching.
2 The oxide film 31 in the transistor region 30A where the gate, source and drain are not to be silicided.
Is selectively removed (FIG. 5E).

Next, in the oxide film reduction step, after removing the resist, the entire surface is thermally oxidized. As a result, the oxide film 31a is formed again in the transistor region 30A, but becomes thinner than the oxide film 31b in the transistor region 30B protected by the resist pattern 32 during the wet etching (FIG. 5F). These oxide films 31a, 31b
Become gate oxide films 31a and 31b of transistors formed in the transistor regions 30A and 30B.

Thereafter, a gate forming step for forming the gate 14 insulated by the gate oxide films 31a and 31b is performed (FIG. 5 (g)).

Next, an oxide film 33 is formed on the entire surface by thermal oxidation. In this thermal oxidation, the oxide film 33 forms the gate 14
The upper film thickness is set to be substantially equal to the designed source and drain positions on both ends of the gate 14 in the transistor region 30A. Then, an impurity diffusion region 15 serving as an electric field relaxation layer is formed on both sides of the gate 14 (FIG. 5H).

Thereafter, an insulating film 16 is deposited on the entire surface and dry etching is performed on the entire surface to form a side wall 16a beside the gate 14. The etching amount at this time is set such that the oxide film 33 is completely removed at the designed positions of the source and drain of the thin film in the transistor region 30A and remains constant at the designed positions of the source and drain of the thick film in the transistor region 30B. (FIG. 6 (i)). The oxide film 3
3 has almost the same thickness as the source and drain design positions of the transistor region 30A on the gate 14, so that it is completely removed almost simultaneously with the source and drain design positions of the transistor region 30A, and one of the gates 14 is excessively over-etched. Is prevented.

Next, an oxide film 34 is formed on the entire surface by thermal oxidation.
To form This thermal oxidation constitutes a second thermal oxidation step together with the thermal oxidation forming the oxide film 33. In the above-mentioned dry etching, since the oxide film 33b at the source and drain design positions of the transistor region 30B remains with a certain thickness, a thin oxide film 34 is formed on the source and drain design positions and the gate 14 of the transistor region 30A.
The thick oxide film 34b is formed again at the source and drain design positions of the transistor region 30B.

Next, an impurity implantation step is performed. This impurity implantation step is a source / drain formation step. That is, a photoresist pattern having an opening at a source and drain design position is formed by photolithography, and using this as a mask, impurity ions such as As are implanted to form an impurity diffusion region having a high impurity concentration, and the impurity diffusion region is formed. Sources and drains 17C and 17D are shown (FIG. 6 (j)).

By the first thermal oxidation step, the gate forming step, the second thermal oxidation step and the impurity implantation step, the gate 14 and the source and drain 17C, 17
In addition to forming D, it is possible to make a difference between the oxide film thickness on the gate 14 and the source and drain 17C in the transistor region 30A and the oxide film thickness on the source and drain 17D in the transistor region 30B (oxide film forming step). ).

Next, an oxide film etching step is performed. That is, dry etching is performed on the entire surface. The etching is performed by the thin oxide film 34a on the source and drain 17C of the transistor region 30A and the thin oxide film 3 on the gate 14.
4c is removed and the transistor region 30B is stopped.
A certain amount of the thick oxide film 34b on the source and drain 17D is left (FIG. 6 (k)).

Next, a metal deposition step is performed, and Ti / Ti
An N deposition layer 19 is formed (FIG. 6 (l)). Sedimentary layer 1
9 is the source and drain 1 of the transistor region 30A
7C and the gate 14 are in contact with silicon, and the source and drain 17D of the transistor region 30B are in contact with the oxide film 34b.

Next, a silicidation process is performed. That is, the entire surface is subjected to a heat treatment by RTA, and the deposited layer 19 is silicided only on the source and drain 17C and the gate 14 of the transistor region 30A in contact with silicon, and the transistor region 3 covered with the oxide film 34b is formed.
The source and drain 17D of 0B are not silicided. The Ti / TiN on the oxide film 34b is removed by a subsequent metal selective etching step (wet selective etching).
It is removed (FIG. 7 (m)).

Thus, in the transistor region 30A, both the source and drain 17C and the gate 14 are formed with the silicides 141 and 171 formed on the surfaces thereof.
1A is completed, and the transistor region 30B is
Only on the surface, silicide 141 is formed to complete transistor region 31B. Thereafter, a normal wiring process is performed, and the wafer process ends.

As described above, according to the method of manufacturing a semiconductor device of the present invention, a transistor whose gate, source and drain are silicided, and a transistor whose gate is silicided alone can be separately formed on the same silicon wafer. In addition, since the gate oxide film 31b is formed at the source and drain design positions of the transistor 30B when the gate 14 is formed, the control of the mask precision and the overlay precision is not strictly required, and the source and drain 17D The metal 19 can be deposited with only the oxide film left, the source and drain 17D can be made non-silicide, and the gate 14 can be silicified. By forming the oxide film 31a thinner than the oxide film 31b before forming the gate 14, the transistor 31A in which the source and the drain are silicided and the transistor 31B in which the source and the drain are not silicided are separately formed. Can be.

Since the thicknesses of the gate oxide films 31a and 31b are different between the transistor 31A and the transistor 31B, when it is necessary to adjust the threshold value Vt of the transistor,
For example, ion implantation for controlling the threshold value Vt may be performed before forming the gate.

In the case where the gate and the source are made non-silicide and the gate is made silicide in all the transistors, in the oxide film etching step,
The etching may be terminated when the oxide film only on the gate is completely removed. As a result, in all the transistor regions, the Ti / TiN deposited layer makes contact with silicon on the gate and makes contact with the oxide film on the source and drain. In this case, since it is not necessary to make a difference in the thickness of the oxide film between the source and the drain, the above-described oxide film reduction step can be omitted.

[Brief description of the drawings]

FIGS. 1A, 1B, 1C, and 1D are cross-sectional views of first, second, third, and fourth silicon wafers showing a method for manufacturing a semiconductor device of the present invention. .

FIGS. 2 (e), (f) and (g) are cross-sectional views of fifth, sixth and seventh silicon wafers showing a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a graph showing the thickness of an oxide film in each part of a transistor in the method of manufacturing a semiconductor device according to the present invention.

FIGS. 4A, 4B, 4C, and 4D are cross-sectional views of first, second, third, and fourth silicon wafers showing another method of manufacturing a semiconductor device according to the present invention; FIGS. It is.

FIGS. 5 (e), (f), (g) and (h) are cross-sectional views of fifth, sixth, seventh and eighth silicon wafers showing another method of manufacturing a semiconductor device according to the present invention. It is.

FIGS. 6 (i), (j), (k), and (1) are ninth, tenth, and first views illustrating another method of manufacturing a semiconductor device according to the present invention.
It is sectional drawing of a 1st, 12th silicon wafer.

FIG. 7 (m) is a cross-sectional view of a thirteenth silicon wafer, illustrating another method of manufacturing a semiconductor device according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Silicon wafer 11 STI 12 Pwell 13, 31a, 31b Gate oxide film 14 Gate 141 Silicide 17A, 17B, 17C, 17D Source and drain 171 Silicide 18, 31, 33, 34 Oxide film 19 Ti / TiN film 20A, 20B, 30A, 30B Transistor area 21A, 21B, 31A, 31B Transistor

Continued on the front page (72) Inventor Hidetoshi Muramoto 1-1-1, Showa-cho, Kariya-shi, Aichi, Japan Denso Corporation (72) Inventor Masahiro Ogino 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture F, Denso Corporation Terms (reference) 5F040 DA23 DA24 DB01 DC01 EA08 EA09 EC01 EC04 EC07 EC13 EF02 EF11 EH02 EK05 FA03 FA05 FA19 FB02 FB04 FC00 FC04 FC19

Claims (5)

[Claims] 1. A transistor forming step of forming a MOS transistor on a silicon wafer, a metal depositing step of depositing a metal on the entire surface of the silicon wafer on which the transistor is formed, and a silicidation of silicifying the deposited metal by heat treatment. In the method of manufacturing a semiconductor device having the steps of:
An oxide film forming step of forming a region to be made non-silicide thick and a region to be made silicide thin, and removing an oxide film formed by the oxide film forming process from all the regions to be made to silicide. An oxide film etching step of etching with an etching amount that leaves a region to be etched. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the non-silicide region is used as a source or a drain of the transistor, and the oxide film forming step is performed after forming a gate of the transistor. In the process, a first impurity implantation process of implanting an impurity into a silicon wafer at a position where a source or a drain to be non-silicide is to be formed, a thermal oxidation process of thermally oxidizing the entire surface of the silicon wafer, and a silicidation process of the silicon wafer A second impurity implantation step of implanting an impurity at a position where a source or a drain to be formed is to be formed, and a diffusion layer serving as a source and a drain of the transistor is formed by the two impurity implantation steps. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said non-silicide region is a source and a drain of a transistor, and said oxide film forming step defines said transistor region on said silicon wafer. Performed after forming the well, in the oxide film forming step, a first thermal oxidation step of forming an oxide film on the entire surface of the silicon wafer by thermal oxidation, and forming a gate in a state where the oxide film is formed on the entire surface A gate forming step, a second thermal oxidation step of forming an oxide film over the entire surface of the silicon wafer by thermal oxidation, and a step of forming a source and a drain by implanting an impurity into a position where a source and a drain of the transistor are to be formed. An impurity implantation step is performed, and a gate oxide film of the transistor is formed in a first thermal oxidation step. Construction method. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the non-silicide region is used as a source and a drain of a part of the transistor, and in the first oxidation step, an oxide film is formed on the entire surface of the silicon wafer. After the formation of the oxide film, a transistor region having a source and a drain as a silicide in the oxide film is selectively etched to perform an oxide film reduction step of reducing the thickness of the oxide film in the transistor region. Production method. 5. The method for manufacturing a semiconductor device according to claim 2, wherein in the oxide film forming step, an oxide film is formed to a constant thickness on the gates of all the transistors. .