JP2000040789A - High-q inductor on silicon substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a simple technique (trench) in which the capacity loss of a semiconductor device with regard to a substrate is reduced, whereby the value of the Q-value of an on-chip inductor is further increased. SOLUTION: An integrated circuit 10 comprises a semiconductor substrate 12, a plurality of trenches 30 which are formed in the substrate are substantially parallel to each other and are separated from each other have each sidewall covered with an insulator 32, and are filled with a material 35 forming a continuous upper surface on the plurality of the trenches 30, an insulator layer 15 formed on the plurality of trenches separated from each other, and electronic devices, such as inductors 37, 38 and 39 formed over the plurality of the trenches separated from each other. As a result, a high-resistance region with regard to the substrate is formed of the plurality of trenches, which are located under the electronic devices and are separated from each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to integrated circuits,
More particularly, it relates to spiral inductors and other passive components manufactured on semiconductor substrates.

[0002]

2. Description of the Related Art RF and microwave devices designed for analog and wireless applications generally have I / O frequency and transistor operating speeds.
Manufactured using Group II-V gallium arsenide (GaAs) material.

Conventional silicon bipolar technology and C
As MOS technology continues to advance the state of the art, and especially as bipolar circuits approach the operating frequency of GaAs integrated circuits, circuit designers are turning to low cost, high yield, large wafer diameter silicon foundries used by major manufacturers. It has been used to produce integrated circuits that can match the performance of so-called "III-V" components.

An important component of an analog / mixed signal circuit is the passive component. Passive components, namely inductors and metal-insulator-metal (MIM) capacitors, are needed in high frequency analog devices, especially as part of a tank circuit in a voltage controlled oscillator (VCO).

[0005] One of the major differences between 10-18 ohm-cm silicon and III-V materials is the relatively low substrate resistivity of silicon, which can be as low as one to three orders of magnitude. . Although this low resistivity is necessary for the functioning of bipolar devices, the quality (Q) factor of passive components, especially on-chip inductors, is significantly degraded. For example, the Q of a series resonant LC circuit is determined by the inductor or capacitor reactance at the resonant frequency divided by the series resistance in the circuit, where Q =
It is represented by X / R. X is the reactance of the inductor (2πfL) or the reactance of the capacitor (1/2).
πfC), and R is a resistance. These inductors have a capacitive loss to the substrate and their inductance and Q-factor are significantly reduced in the high frequency range. Simulation (SPICE) models for inductors on silicon substrates list "inductor-substrate capacitance" as a factor that adversely affects quality (Q) values.

[0006] Silicon or silicon germanium technology uses relatively low resistivity substrates (as compared to III-V materials) to reduce crosstalk and noise between devices. On-chip inductors manufactured on low resistivity wafers generally have poor Q-factors, and chip manufacturers have come up with on-chip or extraneous on-chip solutions that add additional manufacturing cost and complexity. You have to do both.

[0007]

SUMMARY OF THE INVENTION The present invention overcomes the problems of passive components such as spiral inductors having low Q and low self-resonant frequency.

[0008]

According to the present invention, there is provided a semiconductor substrate and a plurality of spaced apart trenches substantially parallel to each other formed in the semiconductor substrate, the trenches having sidewalls coated with an insulator. A trench filled with a material that forms a continuous top surface over the plurality of trenches, an insulating layer formed over the plurality of spaced apart trenches, and an electronic device such as an inductor formed over the plurality of spaced apart trenches. , Whereby a plurality of spaced apart trenches below an electronic device form a high resistance region to a substrate and a method of manufacturing are described. The present invention provides a simple technique (trench) that reduces capacitive losses to the substrate, thereby further increasing the Q of the on-chip inductor.

The present invention further replaces the intrinsic silicon semiconductor substrate region on which the electronic device is fabricated with a high resistance region formed by an oxide-coated deep trench filled with intrinsic polysilicon. , Thereby providing a method of reducing the capacitance loss of an electronic device to a substrate. If the electronic device is an inductor, this technique increases the peak Q factor of the inductor.

[0010] The present invention further provides a method of fabricating an array of deep trenches in a substrate on which one or more high-Q inductors are fabricated.

The present invention further provides a method of isolating a bipolar device by forming a deep trench etched into a semiconductor substrate to form a physical barrier to electronic crosstalk between circuits. .

The present invention further provides a trench that is etched into a semiconductor substrate and then coated with oxide deposited by low pressure chemical vapor deposition (LPCVD) and filled with LPCVD intrinsic polysilicon.

The present invention further provides that as much of the intrinsic silicon substrate area as possible is filled with oxide / polysilicon filled deep.
A method is provided that is replaced with a trench and that substantially free of capacitance to the substrate is reduced. A measurable increase in the Q factor is realized.

It is further desirable to maximize the total area of deep trenches under electronic devices, such as inductors, and to maintain design ground rules. Appropriate trench widths and spacing between trenches must be maintained so as not to impact adjacent electronic device elements.

The present invention further provides an area of "cross-hatched" trench that covers the entire area under an electronic device, such as an inductor, to maximize deep trench replacement of a semiconductor substrate, such as silicon.

The present invention further provides a spiral inductor composed of single-level or multi-level metal layers commonly used in CMOS integrated circuits.

[0017]

Referring now to the drawings, FIG. 1 shows a cross-sectional view of an integrated circuit 10. The substrate 12 on which the inductor 20 is formed of a semiconductor such as Si or SiGe is shown. In the substrate 12, an isolation trench 30 is manufactured. Isolation trench 30 is etched into substrate 12 for device isolation or capacitor charge storage. The depth of the isolation trench 30 is variable and is determined by design ground rules and device operation guidelines. A preferred embodiment that maximizes the quality (Q) factor of the inductor is to place the isolation trench 30 as deep as possible in the silicon substrate 12,
For example, etching is performed within a range of 4 μm to 10 μm. The isolation trenches 30 are generally 6 μm deep with respect to the surface 14 of the substrate 12, are typically 1 μm wide, and are separated by a center-to-center spacing of 2.5 μm. Shallow trench 1
5 is filled in the material after it has been formed in the upper surface 14 and the isolation trenches 30 have been formed and filled with the material.

FIG. 2 is an enlarged view of a part of the isolation trench 30. Within the isolation trench 30 there is a layer or layers of semi-insulating or high resistance material, such as in the range of 2 to 500 (kilo ohms). A material 35, for example, intrinsic polysilicon, is filled from the bottom of the trench 30 to the surface 14 of the substrate 12, for example silicon, or by conformal deposition, and the substrate 12 is etched back or planarized. By removing excess film from the surface 14 of the substrate. A preferred embodiment of the present invention is to coat the inner wall of trench 30 with thousands of angstroms of silicon oxide 32, such as by low pressure chemical vapor deposition tetraethylorthosilicate (LPCVD TEOS). Silicon oxide 32 has a high conformity. After depositing or forming silicon oxide 32 or other insulator,
The trench 30 is made, for example, by undoped LPCVD.
Overfill with material 35 such as polysilicon. Material 35 and top surface 14 are planarized by chemical mechanical polishing (CMP). Instead of silicon dioxide 32, silicon nitride can be used.

An additional processing step is performed to form a shallow trench 15 below the top surface 14, for example, 5500 Angstroms deep. The shallow trench 15 is the trench 3
The top of 0 is removed and is wider than all trenches so that the top surface has a rectangular or square shape and is the same length as all trenches or longer than all trenches. Shallow trench 15 is filled with a material such as silicon dioxide, silicon nitride or intrinsic polysilicon.

Also, additional steps are performed to form devices such as bipolar n-type and p-type FETs in substrate 12.

On top surface 14, metal layers 37, 38, 3
Three layers of metallization consisting of 9 are shown. Each of the metal layers 37, 38, and 39 is
1, 42 and 43 are formed. Drilled vias or studs on each of the insulating layers 41, 42 and 43, tungsten, Al, AlCu, and filled with a conductive metal such as a metal selected from the group consisting of Al ₂ Cu, and Cu, in the substrate 12 An electrical interconnect is formed between the device and the metal layer 37 and between the metal layers 37-39. Metal layer 37,
38 and 39 is patterned or etched, followed by the flow of the interlevel dielectric 46, 47, 48 such as SiO ₂ or respectively attached, or flowable oxide. Alternatively, metal layers 37, 38, 39 are blanket deposited in the channel or groove initially formed in the interlevel dielectric and a chemical mechanical polishing (CMP) is performed to separate the metal in the channel. Form a coplanar surface with the inter-dielectric. When the metal layer 39 is the last metal layer,
The interlevel dielectric 48 can be omitted. As shown in FIG.
The metal layer and the interlevel dielectric are planarized by CMP. The insulating layers 41, 42, 43 are also planarized by CMP.

Lithography patterning, subtractive etching of wiring metal layers, or patterning of interlevel layers 41-43, along with metal layers 37-39,
The on-chip inductor 20 is manufactured by dielectric filling with metal and damascene polishing by CMP. Inductors 20, such as spiral inductors, are made of metal layers 37-3.
It can be formed from nine single levels or multiple levels. In FIG. 1, two metal levels, metal layers 38 and 39, are incorporated by reference into M.A. They are shunted together via interlevel vias 45 which are described in detail in US Pat. No. 5,446,311 to Soyuer et al.

FIG. 3 is a plan view of the on-chip inductor 20 as shown in cross section in FIG. The spiral inductor 20 is formed on the shallow trench 15. The shallow trench 15 is on a plurality of isolation trenches 30 parallel to each other. One end of inductor 20 is at terminal 51 and the other end is at terminal 52.

FIG. 4 is a plan view of a shallow trench 15 and a cross-hatch isolation trench formed by parallel isolation trenches 30 and parallel isolation trenches 54 intersecting isolation trenches 30. The inductor 20 formed thereon is not shown in FIG. The so-called "cross hatch" layout reduces the volume of silicon substrate material by three:
Replace at a rate greater than one.

FIG. 5 is a graph showing the inductance of a spiral inductor versus frequency. Spiral inductors are
It was configured according to FIG. Curve 62 shows the inductance of a six-turn spiral inductor with metal layers 38 and 39 bonded. Deep trench 30 directly below
Have a higher peak Q value as indicated by curve 64. Curve 64 also shows a higher Q value for a given frequency.

Curve 63 shows the above inductance without the deep trench 30 below the six-turn spiral inductor.

Curve 65 illustrates the above Q factor without deep trench 30 below the six-turn spiral inductor.

An integrated circuit including a passive component such as an inductor on a high resistance region formed in a semiconductor substrate and including a plurality of parallel isolation trenches or cross hatch isolation trenches having a plurality of high resistance regions or volumes has been described. While shown, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the broad scope of the invention, which is limited only by the claims that follow.

In summary, the following is disclosed regarding the configuration of the present invention.

(1) A semiconductor substrate and a plurality of spaced apart isolation trenches formed in the semiconductor substrate and substantially parallel to each other, filled with a material having a resistance greater than the resistance of the substrate, and A plurality of spaced apart isolation trenches filled up to an upper surface of the trenches to form a continuous surface over the plurality of trenches; an insulating layer formed over the plurality of spaced apart trenches; and the plurality of spaced apart trenches. A passive component formed over the trench, whereby the plurality of spaced apart trenches below the passive component form a region of high resistance to the resistance of the substrate. (2) The integrated circuit according to (1), wherein the isolation trench further includes an insulating layer formed on sidewalls of the plurality of isolation trenches. (3) The integrated circuit according to (2), wherein the insulating layer is selected from the group consisting of silicon dioxide and silicon nitride. (4) The integrated circuit according to (2), wherein the isolation trench is filled with a material selected from the group consisting of silicon dioxide, silicon nitride, and polysilicon. (5) further comprising a shallow trench filled with a material selected from the group consisting of silicon dioxide, silicon nitride, and polysilicon, wherein said shallow trench is wider than three said isolation trenches and said plurality of isolation trenches; The above (1) formed in the substrate in which the trench is arranged
An integrated circuit according to claim 1. (6) intersecting said first plurality of spaced apart trenches;
Second substantially parallel layers formed in the semiconductor substrate;
The integrated circuit of claim 1, further comprising a plurality of spaced apart trenches. (7) the second plurality of spaced apart trenches are formed at the same position as the first plurality of trenches,
The integrated circuit according to (6), wherein the pattern is formed. (8) The integrated circuit of (7), wherein the first and second plurality of spaced apart trenches replace the volume of the substrate at a ratio of 3: 1 or greater. (9) forming a plurality of spaced apart trenches substantially parallel to each other in a semiconductor substrate; filling the trenches with a material having a resistance greater than a resistance of the substrate; Filling the trench to the top surface of the trench to form a smooth surface; forming an insulating layer over the plurality of trenches; forming a passive component over the insulating layer over the plurality of trenches. Forming an integrated circuit.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view (scale is not fixed) of an embodiment of the present invention.

FIG. 2 is an enlarged view of a part of FIG. 1 showing an isolation trench 30;

FIG. 3 is a plan view of the embodiment of FIG. 1;

FIG. 4 is a plan view of the alternative embodiment of FIG. 1 before depositing vias and metal layers 37-39 over the crosshatch isolation trench.

FIG. 5 is a graph showing the inductance of a spiral inductor made according to FIG. 1 as a function of frequency. For reference, the inductance of a spiral inductor made without using isolation trenches below is also shown as being fabricated on the same silicon wafer. Also shown is the Q factor of the inductor as a function of frequency.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Integrated circuit 12 Substrate 14 Surface 15 Shallow trench 20 Inductor 30 Isolation trench 32 Silicon oxide 35 Material 37 Metal layer 38 Metal layer 39 Metal layer 41 Insulation layer 42 Insulation layer 43 Insulation layer 45 Interlevel via 48 Interlevel dielectric 51 Terminal 52 Terminal

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor David Lewis Haram United States 10547 Mohegan Lake Sylvain Lane, New York 1589 (72) Inventor Kenneth Jay Stein United States 06482 Sunday Hook, Connecticut Riverside Road 31 F term (reference) 5E070 AA01 AB06 AB07 CB12 CB17 CB20 CC10 DB08 5F038 AC01 AZ04 DF01 DF12 EZ01 EZ20

Claims (9)

[Claims] 1. A semiconductor substrate and a plurality of spaced apart isolation trenches formed in the semiconductor substrate and substantially parallel to each other, filled with a material having a resistance greater than a resistance of the substrate, and A plurality of spaced apart trenches filled to the top surface of the trench to form a continuous surface on the trench, an insulating layer formed on the plurality of spaced trenches, and the plurality of spaced trenches A passive component formed thereon, whereby said plurality of spaced apart trenches below said passive component form a high resistance region for the resistance of said substrate. 2. The isolation trench further includes an insulating layer formed on sidewalls of the plurality of isolation trenches.
An integrated circuit according to claim 1. 3. The integrated circuit according to claim 2, wherein said insulating layer is selected from the group consisting of silicon dioxide and silicon nitride. 4. The integrated circuit according to claim 2, wherein said isolation trench is filled with a material selected from the group consisting of silicon dioxide, silicon nitride, and polysilicon. 5. The semiconductor device of claim 1, further comprising a shallow trench filled with a material selected from the group consisting of silicon dioxide, silicon nitride, and polysilicon, wherein said shallow trench is wider than three said isolation trenches and 2. The integrated circuit according to claim 1, wherein said isolation trench is formed in said substrate. 6. The semiconductor device of claim 1, further comprising a second plurality of substantially parallel trenches formed in said semiconductor substrate and intersecting said first plurality of spaced apart trenches.
An integrated circuit according to claim 1. 7. The integrated circuit of claim 6, wherein said second plurality of spaced trenches are formed at the same location as said first plurality of trenches to form a crosshatch pattern. 8. The integrated circuit of claim 7, wherein said first and second plurality of spaced apart trenches replace the volume of said substrate by a ratio of three to one or greater. 9. A method for forming a plurality of spaced apart trenches substantially parallel to each other in a semiconductor substrate, filling the trenches with a material having a resistance greater than a resistance of the substrate, and over the plurality of trenches. Filling the trench to the top surface of the trench to form a continuous surface; forming an insulating layer over the plurality of trenches; and passive components over the insulating layer over the plurality of trenches. Forming an integrated circuit.