JP2000040748A - Semiconductor integrated circuit device and designing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect the gate oxide film of an input cell transistor against damages caused by electric charge generated, when a multilayer metal interconnection is formed through an RIE(reactive ion etching) method in a semiconductor integrated circuit device, where output cells and input cells are connected through a multilayer metal interconnection. SOLUTION: For instance, a gate electrode 13a of a MOS transistor 13' of an input cell 13 is not connected at a time, when the first metal wiring 14a of a multilayer metal interconnection 14 is formed, and the gate electrode 13a is connected to the multilayer metal interconnection 14 through the intermediary of an upper wiring 31h of the same layer with a third metal wiring 14c, when the third metal wiring 14c is formed. In this way, a process where the multilayer metal interconnection 14 is formed, and electric charge 18 generated by reactive ions is prevented from flowing excessively into the gate electrode 13a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method for designing the same, and more particularly, to a semiconductor integrated circuit device in which a drain region of an output transistor and a gate electrode of an input transistor are connected by a multilayer wiring. The present invention relates to a semiconductor integrated circuit device having a configuration and a design method thereof.

[0002]

2. Description of the Related Art In recent years, in a semiconductor integrated circuit device,
For example, as shown in FIG. 3, a multilayer metal wiring 14 having at least a first-layer metal wiring and a second-layer metal wiring is provided between an output cell 12 and an input cell 13 provided on the same substrate 11. The connection is made using.
This is very useful in simplifying the routing of wiring accompanying an increase in the size of an integrated circuit device such as multi-functionality, in order to enable three-dimensional crossing of wiring.

Conventionally, however, reactive ion etching (RIE) is generally used to form the multi-layered metal wiring 14 in a semiconductor integrated circuit device. There is a problem that the gate insulating film of the transistor of the input cell 13 is broken by the electric charge.

FIG. 4 schematically shows a process of forming a multilayer metal wiring in a conventional semiconductor integrated circuit device. Here, a multilayer metal wiring having a three-layer structure will be described as an example.

For example, a multi-layer metal wiring 14 connects between an output cell 12 and an input cell 13 formed on a substrate 11 and electrically separated from each other by an insulating region (not shown). In the case of connection, first, an interlayer insulating film (first layer) 15 is deposited on the entire surface, and then the transistor 1 of the output cell 12 is deposited on the interlayer insulating film 15.
A contact hole 16 having a depth reaching the drain region 12a of 2 ′;
Contact hole 1 having a depth reaching gate electrode 13a of 3 '
7. Open 7 holes.

An electrode material such as tungsten (W) is buried in each of the contact holes 16 and 17 to form a drain contact 16 'connected to the drain region 12a of the transistor 12' of the output cell 12, and A gate contact 17 'connected to the gate electrode 13a of the transistor 13' of the cell 13 is formed.

After that, a wiring material such as aluminum (Al) serving as a first-layer metal wiring is deposited on the interlayer insulating film 15. Then, it is referred to as PEP (Photo E
The drain contact 1 is patterned by an activating process and an RIE process.
6 ′, the transistor 1 of the output cell 12
An output-side first-layer metal wiring 14a connected to the drain region 12a of the gate electrode 2 ';
A first-level metal wiring 14a on the input side connected to the gate electrode 13a of the transistor 13 'of the input cell 13 is formed through the above (see FIG. 3A).

In the step of forming the first-layer metal wirings 14a, a charge is generated when Al is etched by reactive ions (ionized etching gas), and the first-layer metal wiring 14a on the output side is charged. The generated charge 18 flows into the drain region 12a of the transistor 12 'of the output cell 12 via the drain contact 16'. In this case, by forming a PN junction between the drain region 12a and the substrate 11, the charge 18 flowing into the drain region 12a can be reduced.
Flows to the ground line or the power supply line, where the accumulation of the electric charge 18 does not occur.

On the other hand, the first ions on the input side are caused by reactive ions.
The charge 18 generated in the layer metal wiring 14a is accumulated in the gate electrode 13a of the transistor 13 'of the input cell 13 via the gate contact 17'.

Next, an interlayer insulating film 1 serving as a second layer is formed on the entire surface.
5 is deposited, a contact hole 19 having a depth reaching the first-level metal interconnection 14a on the output side and the first-level metal interconnection 1 on the input side are formed in the interlayer insulating film 15.
A contact hole 20 having a depth reaching 4a is formed.

Then, W is formed in each of the contact holes 19 and 20.
Then, a contact 19 'connected to the output-side first-layer metal wiring 14a and a contact 20' connected to the input-side first-layer metal wiring 14a are formed by embedding an electrode material such as the above.

Thereafter, a wiring material such as Al to be a second-layer metal wiring is deposited on the second-layer interlayer insulating film 15. Then, it is patterned by PEP and RIE processes, and the output-side second-layer metal wiring 14 b connected to the contact 19 ′ and the contact 2
The input-side second-layer metal wiring 14b connected to 0 ′ is formed (see FIG. 2B).

During the formation of the second-layer metal wirings 14b, the charge 18 generated on the output-side second-layer metal wiring 14b by the reactive ions is transferred to the contact 1
9 ′, the first-layer metal wiring 14a on the output side, and
It flows into the drain region 12a of the transistor 12 'of the output cell 12 via the drain contact 16', and flows to the ground line or power supply line.

On the other hand, the second ions on the input side are caused by reactive ions.
The electric charge 18 generated in the layer metal wiring 14b is applied to the gate electrode of the transistor 13 'of the input cell 13 via the contact 20', the input-side first layer metal wiring 14a, and the gate contact 17 '. 13a.

Next, an interlayer insulating film 1 serving as a third layer is formed on the entire surface.
5 is deposited on the interlayer insulating film 15, the contact hole 21 having a depth reaching the output-side second-layer metal wiring 14 b, and the input-side second-layer metal wiring 1 are formed.
A contact hole 22 having a depth reaching 4b is formed.

Then, W is formed in each of the contact holes 21 and 22.
Then, a contact 21 'connected to the output-side second-layer metal wiring 14b and a contact 22' connected to the input-side second-layer metal wiring 14b are formed by respectively embedding electrode materials such as.

Thereafter, a wiring material such as Al to be a third-layer metal wiring is deposited on the third interlayer insulating film 15. Then, it is patterned by the PEP and RIE processes to form the third-layer metal wiring 14c connected to the contact 21 'and the contact 22', respectively (see FIG. 3 (c)).

In the step of forming the third-layer metal wiring 14c, the formation of the multi-layer metal wiring 14 connecting the output cell 12 and the input cell 13 is completed. The electric charge 18 generated in the wiring 14c is transferred to the output cell via the contact 21 ', the second-layer metal wiring 14b, the contact 19', the first-layer metal wiring 14a, and the drain contact 16 '. It flows into the drain region 12a of the twelve transistors 12 'and flows to the ground line or the power supply line.

At this time, the electric charge 18 stored in the gate electrode 13a of the transistor 13 'of the input cell 13 also becomes
By flowing into the drain region 12a of the transistor 12 'of the output cell 12 and flowing to the ground line or the power supply line, the transistor 1 of the input cell 13
The accumulation of charges in the 3 ′ gate electrode 13a is eliminated.

As described above, conventionally, the multilayer metal wiring 14
Until the uppermost layer (third layer metal wiring 14c in this case) is formed and the formation of the multilayer metal wiring 14 connecting the output cell 12 and the input cell 13 is completed. Gate electrode 13a of thirteen transistor 13 '
The electric charges 18 generated by the reactive ions during the formation of the multilayer metal wiring 14 are accumulated. The charge 18 accumulated in the gate electrode 13a is used for the input cell 1
This causes the gate oxide film 13b of the third transistor 13 'under the gate electrode 13a to be destroyed.

[0021]

As described above, conventionally, when forming a multilayer metal wiring by RIE,
The charge generated when the metal wiring is etched by the ionized etching gas is excessively accumulated in the gate electrode of the transistor of the input cell connected to the multi-layer metal wiring, so that the gate oxide film of the transistor of the input cell is formed. There was a problem of destroying.

Therefore, the present invention relates to a structure in which a drain region of a first transistor and a gate electrode of a second transistor are connected by a wiring having a multilayer structure, and in some cases, a wiring having a multilayer structure formed by reactive ion etching. A semiconductor integrated circuit device capable of preventing a gate insulating film of a second transistor connected to its wiring from being destroyed at the time of forming the same, and improving the yield and reliability, and a method of designing the same. And

[0023]

In order to achieve the above object, in a semiconductor integrated circuit device according to the present invention, a drain region of a first transistor and a gate electrode of a second transistor are formed in a multilayer structure. In this configuration, a protection circuit is provided between the gate electrode of the second transistor and the lowermost wiring layer of the wiring.

Further, in the method of designing a semiconductor integrated circuit device according to the present invention, in the case where the drain region of the first transistor and the gate electrode of the second transistor are connected by a multilayer wiring, In order to prevent the charge generated by the reactive ions from being excessively accumulated in the gate electrode of the second transistor during the formation of the wiring by reactive ion etching, the gate electrode is connected to the gate electrode through a contact. A transistor formed by connecting an upper wiring portion formed of the same wiring layer as the uppermost wiring layer of the wiring is used as the second transistor.

According to the semiconductor integrated circuit device and the design method thereof of the present invention, in the case where the drain region of the first transistor and the gate electrode of the second transistor are connected by a multilayer wiring, Excessive flow of electric charge generated during the formation of a multilayer wiring by reactive ion etching into the gate electrode of the second transistor connected to the wiring can be prevented.
This makes it possible to protect the gate insulating film of the second transistor from being destroyed by charges generated by reactive ions.

In particular, through a contact to the gate electrode,
A transistor formed by connecting an upper wiring portion formed of the same wiring layer as the uppermost wiring layer of a wiring having a multilayer structure,
In the case where the second transistor is used, it is possible to prevent the destruction of the gate insulating film of the second transistor while keeping the wiring structure as it is. Is not required.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

That is, in this semiconductor integrated circuit device, for example, between an output cell (first transistor) 12 and an input cell (second transistor) 13 provided on the same substrate 11, Through the protection circuit 31,
It is configured to be connected by a multilayer metal wiring (wiring of a multilayer structure) 14.

As shown in FIG. 2, for example, the output cell 12 is a MOS (Metal Oxide Semi).
and a multi-layer metal wiring 14 connected to a drain region 12a of the transistor 12 'via a drain contact 16'.

The input cell 13 is composed of, for example, a MOS transistor 13 'as shown in FIG. 2, and the protection circuit 31 is connected to its gate electrode 13a via a gate contact 17'. ,
The protection circuit 31 is connected to the multilayer metal wiring 14.

The multilayer metal wiring 14 includes, for example, at least a first layer metal wiring (lowermost wiring layer) and a second layer metal wiring (uppermost wiring layer). The multi-layered metal wiring 14 is formed by using reactive ion etching (RIE) as in the prior art.

In the protection circuit 31, the charge generated when the multilayer metal wiring 14 is formed by reactive ion etching is transferred to the MOS transistor 13 'of the input cell 13.
2 to prevent excessive accumulation in the gate electrode 13a. For example, as shown in FIG. 13a). The details of the protection circuit 31 will be described later.

According to the semiconductor integrated circuit device having such a configuration, the input cell connected to the multi-layer metal wiring 14 due to the action of the protection circuit 31 when the multi-layer metal wiring 14 is formed by the reactive ion etching. 13
MOS transistor 13 'can be prevented from excessively flowing into gate electrode 13a.

Therefore, the charge generated by the reactive ions is excessively accumulated in the gate electrode 13a, and the MOS transistor 1 of the input cell 13
It is possible to prevent the 3 ′ gate oxide film (gate insulating film) 13b from being broken.

Hereinafter, the outline of the above-described semiconductor integrated circuit device will be described more specifically. FIG. 2 schematically shows a process of forming the multilayer metal wiring 14 in the semiconductor integrated circuit device. Here, a semiconductor integrated circuit device in which the multi-layer metal wiring 14 has a three-layer structure and connects between the output cell 12 and the input cell 13 via the multi-layer metal wiring 14. In FIG. 4, for example, the multilayer metal wiring 14
Of the first layer metal wiring (input side) 14a and the gate electrode 13a of the MOS transistor 13 'of the input cell 13.
The protection circuit 31 is connected to the gate contact 17 'connected to the third metal wiring 14c of the multilayer metal wiring 14 via an upper wiring portion formed of the same wiring layer as the third metal wiring 14c. Will be described as an example.

For example, they are formed on the same substrate 11,
MOS transistor 1 of output cell 12 which is electrically isolated from each other by an insulating region (not shown)
When the drain region 12a of the MOS transistor 2 'and the gate electrode 13a of the MOS transistor 13' of the input cell 13 are connected by the multilayer metal wiring 14 via the protection circuit 31, first, the interlayer insulating film (1 Layer 15) is deposited.

Thereafter, a contact hole 16 having a depth reaching the drain region 12a of the MOS transistor 12 'of the output cell 12 and the MOS transistor 13' of the input cell 13 are formed in the interlayer insulating film 15. A contact hole 17 having a depth reaching the gate electrode 13a is formed.

Then, W is formed in each of the contact holes 16 and 17.
And the like, respectively, and the drain region 12 a of the MOS transistor 12 ′ of the output cell 12 is embedded.
, And a gate contact 17 ′ connected to the gate electrode 13 a of the MOS transistor 13 ′ of the input cell 13.

Further, on the interlayer insulating film 15, a wiring material such as Al to be the first layer metal wiring is deposited. Then, it is patterned by the PEP and RIE processes, and the output-side first-layer metal wiring 14a connected to the drain region 12a of the MOS transistor 12 'of the output cell 12 via the drain contact 16'.
The first-layer metal wiring (lowest wiring layer) 1 connected to the gate electrode 13a of the MOS transistor 13 'of the input cell 13 via the gate contact 17'.
4a, a lower wiring portion 31a formed of the same wiring layer as the wiring layer 4a, and a first input-side first wiring portion independent of the lower-layer wiring portion 31a and the output-side first-layer metal wiring 14a.
The layer metal wiring 14a is formed (see FIG. 1A).

In the step of forming the first-layer metal wirings 14a, 14a and the lower-layer wiring portion 31a, charges are generated when Al is etched by reactive ions, and are generated in the first-layer metal wiring 14a on the output side. Charge 18 is
Through the drain contact 16 ′, the drain region 12 of the MOS transistor 12 ′ of the output cell 12
flows into a. In this case, by forming a PN junction (diode) between the drain region 12a and the substrate 11, the electric charge 18 flowing into the drain region 12a flows to the ground line or the power supply line,
There is no accumulation of charges 18 there.

The first ions on the input side are caused by reactive ions.
The charges 18 generated in the layer metal wiring 14a do not flow to the output side first layer metal wiring 14a and the lower layer wiring part 31a, but are accumulated on the input side first layer metal wiring 14a.

On the other hand, the lower wiring 3
1a is generated by the gate contact 17 '
Through the gate electrode 13a of the transistor 13 'of the input cell 13. At this time, the wiring length of the lower wiring portion 31a is made sufficiently shorter than the other wirings (the first-layer metal wiring 14a on the output side and the first-layer metal wiring 14a on the input side), so that The accumulation of the electric charge 18 on the gate electrode 13a can be made very small.

Next, an interlayer insulating film 1 serving as a second layer is formed on the entire surface.
5 is deposited, a contact hole 19 having a depth reaching the first-level metal interconnection 14a on the output side and the first-level metal interconnection 1 on the input side are formed in the interlayer insulating film 15.
Contact hole 20 having a depth reaching one end (output side) of 4a
The hole is opened.

At the same time, the second interlayer insulating film 1
5, a contact hole 31b having a depth reaching the other end (input side) of the first-layer metal wiring 14a on the input side and a contact hole 31c having a depth reaching the lower-layer wiring portion 31a are formed. .

The contact holes 19, 20,.
An electrode material such as W is embedded in each of 31b and 31c, and a contact 19 'connected to the output-side first-layer metal wiring 14a and a contact 20' connected to one end of the input-side first-layer metal wiring 14a. At the same time, a pair of contacts (first contact portions) 31b 'and 31c' respectively reaching the other end of the input-side first-layer metal wiring 14a and the lower-layer wiring portion 31a are formed.

Thereafter, a wiring material such as Al to be a second-layer metal wiring is deposited on the second-layer interlayer insulating film 15. Then, it is patterned by PEP and RIE processes, and the output-side second-layer metal wiring 14 b connected to the contact 19 ′ and the contact 2
The input-side second-layer metal wiring 14b connected to 0 'is formed.

At the same time, each of the contacts 31
A pair of intermediate-layer wiring portions 31d and 31e formed of the same wiring layer as the second-layer metal wiring (intermediate-layer wiring layer) 14b are formed to be connected to b 'and 31c', respectively.
FIG.

During the formation of the second-layer metal wirings 14b, 14b and the intermediate-layer wiring portions 31d, 31e, the electric charge 18 generated in the second-layer metal wiring 14b on the output side by the reactive ions is transferred to the contacts 19 ', It flows into the drain region 12a of the MOS transistor 12 'of the output cell 12 via the first-layer metal wiring 14a on the output side and the drain contact 16', and flows to the ground line or the power supply line.

Further, the second ions on the input side are caused by the reactive ions.
The charge 18 generated in the layer metal wiring 14b is transferred to the input side first layer metal wiring 14 via the contact 20 '.
a, and is accumulated on the first layer metal wiring 14a on the input side.

Further, of the electric charges 18 generated in the intermediate layer wiring portions 31d and 31e by the reactive ions, the electric charges 18 generated in the intermediate layer wiring portion 31d correspond to the contact 31
The current flows through the input-side first-layer metal wiring 14a via b ′, and is accumulated on the input-side first-layer metal wiring 14a.

On the other hand, the charges 18 generated in the intermediate layer wiring portion 31e by the reactive ions are transferred to the contacts 31c ',
The charge is accumulated in the gate electrode 13a of the MOS transistor 13 'of the input cell 13 via the lower wiring portion 31a and the gate contact 17'. At this time, the accumulation of the electric charges 18 in the gate electrode 13a can be made minute by making the wiring length of the intermediate layer wiring portion 31e sufficiently short as much as the lower layer wiring portion 31a.

Next, an interlayer insulating film 1 serving as a third layer is formed on the entire surface.
5 is deposited on the interlayer insulating film 15, the contact hole 21 having a depth reaching the output-side second-layer metal wiring 14 b, and the input-side second-layer metal wiring 1 are formed.
A contact hole 22 having a depth reaching 4b is formed.

At the same time, the third interlayer insulating film 1
For 5, contact holes 31 f and 31 g having a depth reaching the intermediate layer wiring portions 31 d and 31 e are formed. Then, an electrode material such as W is buried in each of the contact holes 21, 22, 31f, and 31g to form a contact 2 connected to the output-side second-layer metal wiring 14b.
1 'and a pair of contacts (second contact portions) 31f' and 31g respectively reaching the intermediate layer wiring portions 31d and 31e at the same time as forming the contacts 22 'connected to the input-side second layer metal wiring 14b. 'Form.

Thereafter, a wiring material such as Al to be a third-layer metal wiring is deposited on the third interlayer insulating film 15. Then, it is patterned by PEP and RIE processes to form a third-layer metal wiring 14c connected to the contacts 21 'and 22', respectively.

At the same time, the contacts 31f ',
An upper-layer wiring portion 31h is formed, which is the same as the third-layer metal wiring (uppermost wiring layer) 14c and interconnects 31g '(see FIG. 3C).

In the step of forming the third layer metal wiring 14c and the upper layer wiring portion 31h, the output cell 12 and the input cell 1 are formed by forming the third layer metal wiring 14c.
3 is completed, the formation of the multi-layer metal wiring 14 connecting the third metal wiring 14c to the third metal wiring 14c by reactive ions is completed.
The electric charge 18 generated at the contact 21 ′ and the second
Layer metal wiring 14b, the contact 19 ', the first
It flows into the drain region 12a of the MOS transistor 12 'of the output cell 12 via the layer metal wiring 14a and the drain contact 16', and flows to the ground line or the power supply line.

Further, since the formation of the multi-layer metal wiring 14 is completed, the electric charge 18 accumulated on the input-side first-layer metal wiring 14a is transferred to the contact 20 ',
The input-side second-layer metal wiring 14b, the contact 22 ', the third-layer metal wiring 14c, the contact 21', the output-side second-layer metal wiring 14b, the contact 19 ', and the output-side second metal wiring 14b. Single-layer metal wiring 14
a, and via the drain contact 16 ′,
It flows into the drain region 12a of the MOS transistor 12 'of the output cell 12, and flows to the ground line or the power supply line.

On the other hand, the upper wiring 3
The charge 18 generated in 1h is transferred to the MOS transistor of the output cell 12 via the contact 31f ', the intermediate layer wiring portion 31d, the contact 31b', the multilayer metal wiring 14, and the drain contact 16 '. 12 'flows into the drain region 12a, and flows to the ground line or the power supply line.

When the formation of the protection circuit 31 is completed by the formation of the upper wiring portion 31h, the electric charge 18 stored in the gate electrode 13a of the MOS transistor 13 'of the input cell 13 is transferred to the gate electrode 13a. Contact 17 ', protection circuit 31, multilayer metal wiring 1
4, and via the drain contact 16 ',
It flows into the drain region 12a of the MOS transistor 12 'of the output cell 12, and flows to the ground line or the power supply line. Thereby, the accumulation of the electric charge 18 in the gate electrode 13 is eliminated.

As described above, when the first-layer metal wiring 14a is formed, the MOS transistor 13 'of the input cell 13 is formed.
The gate electrode 13a is not connected to the gate electrode 13a, and the gate electrode 13a is not connected to the multilayer metal wiring 14h when the upper layer wiring portion 31h formed of the same wiring layer as the third layer metal wiring 14c is formed.
In the step of forming the multi-layer metal wiring 14, the charges 18 generated by the reactive ions do not excessively flow into the gate electrode 13a.

That is, when the output cell 12 and the input cell 13 are connected via the multilayer metal wiring 14 having the three-layer structure,
For example, the lower layer wiring portion 31 formed of the same wiring layer as the first layer metal wiring 14a which is the lowermost layer of the multilayer metal wiring 14
a, the lower layer wiring portion 31a and the first layer metal wiring 14
a pair of contacts 31b ', 3 respectively connected to
1c ', a second layer which is an intermediate layer of the multi-layer metal wiring 14 and is connected to the contacts 31b' and 31c '.
Intermediate layer wiring portions 31d and 31e formed of the same layer as the layer metal wiring 14b, and a pair of contacts 31f 'and 31 respectively connected to the intermediate layer wiring portions 31d and 31e.
g 'and an upper wiring portion 31h which connects the contacts 31f' and 31g 'to each other and is formed of the same wiring layer as the third metal wiring 14c which is the uppermost layer of the multilayer metal wiring 14. The protection circuit 31 is provided.

In addition, in the step of forming the third-layer metal wiring 14c, the formation of the protection circuit 31 is completed by forming the upper-layer wiring portion 31h, and the drain region of the MOS transistor 12 'of the output cell 12 is not provided until after. 1
2 a and the gate electrode 13 a of the MOS transistor 13 ′ of the input cell 13 are connected via the multilayer metal wiring 14.

In this case, the input cell 13 is not connected to the multi-layer metal wiring 14 until the upper-layer wiring portion 31h is formed. Therefore, the electric charge 18 generated when the multi-layer metal wiring 14 is formed by reactive ion etching. In addition, it is possible to prevent excessive accumulation at the gate electrode 13a of the MOS transistor 13 'of the input cell 13.

Therefore, the charge 18 generated by the reactive ions is excessively accumulated in the gate electrode 13a, and the charge 18 is destroyed.
The 3 ′ gate oxide film 13b can be protected.

In particular, in the semiconductor integrated circuit device described above, as a design method of the protection circuit 31, for example, an upper wiring portion 31h formed of the same wiring layer as the uppermost layer of the multilayer metal wiring 14 via a contact with a gate electrode is provided. Is prepared in advance and this is selected as the input cell 13 at the design stage, the wiring structure of the multi-layer metal wiring 14 is kept as it is, and the gate insulating film is destroyed. Can be prevented, and without the need for trouble such as design changes,
Can be easily realized.

As described above, it is possible to prevent the charge generated during the formation of the multilayer metal wiring by reactive ion etching from excessively flowing into the gate electrode of the MOS transistor of the input cell connected to the multilayer metal wiring. .

That is, a protection circuit is provided between the input cell and the multilayer metal wiring, and the third metal wiring of the multilayer metal wiring is provided between the gate electrode of the MOS transistor of the input cell and the first metal wiring of the multilayer metal wiring. The connection is made via an upper wiring section of the protection circuit, which is formed of the same wiring layer as the layer metal wiring.

As a result, the gate electrode is connected to the multi-layered metal wiring at the time of forming the upper-layer wiring portion, so that in the step of forming the multi-layered metal wiring, the charges generated by the reactive ions excessively flow into the gate electrode. Can be stopped.

Therefore, it is possible to protect the gate insulating film of the MOS transistor of the input cell from damage caused by excessive accumulation of charges generated by the reactive ions in the gate electrode, thereby improving the yield and reliability of the semiconductor integrated circuit device. It can improve the performance.

In the embodiment described above,
The case where the contact is formed by burying an electrode material such as tungsten in the contact hole has been described as an example. However, the present invention is not limited to this. For example, a wiring material such as Al is buried in the contact hole and the contact and the metal wiring are formed. It is also possible to integrally form using the same material.

The wiring structure of the multilayer metal wiring and the total number of wirings are not limited at all.
Of course, various modifications can be made without departing from the scope of the present invention.

[0072]

As described above in detail, according to the present invention, in the case where the drain region of the first transistor and the gate electrode of the second transistor are connected by a multilayer wiring, A semiconductor integrated circuit device capable of preventing a gate insulating film of a second transistor connected to the wiring from being destroyed when a wiring having a multilayer structure is formed by reactive ion etching and capable of improving yield and reliability; and The design method can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a basic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view similarly illustrating a step of forming a multilayer metal wiring in the semiconductor integrated circuit device.

FIG. 3 is shown to explain the prior art and its problems;
FIG. 1 is a schematic diagram of a semiconductor integrated circuit device.

FIG. 4 is a diagram showing a conventional semiconductor integrated circuit device.
FIG. 4 is a schematic cross-sectional view shown for explaining a step of forming a multilayer metal wiring.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Substrate 12 ... Output cell 12 '... MOS transistor 12a ... Drain region 13 ... Input cell 13' ... MOS transistor 13a ... Gate electrode 13b ... Gate oxide film 14 ... Multilayer metal wiring 14a ... First layer metal wiring 14b ... Second-layer metal wiring 14c Third-layer metal wiring 15 Interlayer insulating film 16 Contact hole 16 'Drain contact 17 Contact hole 17' Gate contact 18 Charge 19, 20 Contact hole 19 ', 20' Contact 21, 22 Contact hole 21 ', 22' Contact 31 Protection circuit 31a Lower wiring 31b, 31c Contact hole 31b ', 31c' Contact 31d, 31e Intermediate wiring 31f, 31g Contact hole 31f ', 31g' ... contact 31h ... upper layer arrangement Part

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) AB02 AC03 BA01 BB05 BF02 BF07 BF12 BF15 BF16 BF19 CC06 CC11 CC13 CC15 CC19

Claims (11)

[Claims] 1. A semiconductor integrated circuit device in which a drain region of a first transistor and a gate electrode of a second transistor are connected by a multilayer wiring, wherein the gate electrode of the second transistor and the wiring of the wiring are connected to each other. A semiconductor integrated circuit device, wherein a protection circuit is provided between a lowermost wiring layer. 2. The semiconductor integrated circuit device according to claim 1, wherein said first transistor forms an output cell. 3. The semiconductor integrated circuit device according to claim 1, wherein said second transistor forms an input cell. 4. The protection circuit according to claim 1, wherein at least a lower wiring portion including a wiring layer of the same layer as a lowermost wiring layer of the wiring,
A pair of contact portions respectively connected to the lower wiring portion and a wiring layer on the second transistor formed of the lowermost wiring layer of the wiring; and a pair of the wiring portions connecting the pair of contact portions to each other. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is configured by an upper wiring portion including an upper wiring layer and the same wiring layer. 5. The protection circuit according to claim 1, wherein the protection circuit includes a lower wiring portion including the same wiring layer as a lowermost wiring layer of the wiring, and the second transistor including the lower wiring portion and a lowermost wiring layer of the wiring. A pair of first contact portions respectively connected to an upper wiring layer, a pair of intermediate wiring portions each connected to the first contact portion and formed of the same wiring layer as the wiring layer of the intermediate layer of the wiring, And a pair of second contact portions respectively connected to the intermediate wiring portion, and an upper wiring portion which connects the second contact portions to each other and which is formed of the same wiring layer as the uppermost wiring layer of the wiring. The semiconductor integrated circuit device according to claim 1, wherein: 6. The semiconductor integrated circuit according to claim 4, wherein the lower layer wiring portion is connected to a gate electrode of the second transistor via a gate contact. Circuit device. 7. The semiconductor integrated circuit according to claim 4, wherein a gate electrode of said second transistor and said upper wiring portion are connected with a shortest distance. Circuit device. 8. The semiconductor according to claim 1, wherein a drain region of the first transistor is connected to a wiring layer formed of a lowermost wiring layer of the wiring via a drain contact. Integrated circuit device. 9. A method for designing a semiconductor integrated circuit device in which a drain region of a first transistor and a gate electrode of a second transistor are connected by a wiring having a multilayer structure, wherein the wiring is formed by reactive ion etching. Sometimes, in order to prevent the charge generated by the reactive ions from being excessively accumulated in the gate electrode of the second transistor, the gate electrode is contacted with the uppermost wiring layer of the wiring via a contact. A method for designing a semiconductor integrated circuit device, characterized in that a transistor connected to an upper wiring portion composed of a plurality of wiring layers is used as the second transistor. 10. The method of designing a semiconductor integrated circuit device according to claim 9, wherein said gate electrode and said upper wiring portion are connected with a shortest distance. 11. The method according to claim 11, wherein the upper layer wiring section is connected to a wiring layer formed of a lowermost wiring layer of the wiring via a contact, so that the charge generated by the reactive ions at the time of forming the wiring is reduced. The method of designing a semiconductor integrated circuit device according to claim 9, wherein a protection circuit for preventing excessive accumulation in a gate electrode of the second transistor is configured.